CN103677081B

CN103677081B - The processing method and processing meanss of data signal

Info

Publication number: CN103677081B
Application number: CN201310745643.4A
Authority: CN
Inventors: 黄帅; 王焕东; 陈新科
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2017-03-15
Anticipated expiration: 2033-12-30
Also published as: CN103677081A

Abstract

The invention discloses a kind of processing method of data signal and processing meanss.Wherein, the method includes：5th data signal and the 6th data signal are obtained according to the first data signal, the second data signal, the 3rd data signal and the 4th data signal；Obtain the 3rd clock signal, and when second clock signal is located at the first pre-set interval relative to the phase contrast of the 3rd clock signal, the 5th data signal and the 6th data signal are gathered using the rising edge of the 3rd clock signal, when phase contrast is located at the second pre-set interval, the 5th data signal and the 6th data signal is gathered using the trailing edge of the 3rd clock signal；9th data signal is obtained according to the 8th data signal obtained by the 6th data signal of the 7th data signal obtained by the 5th data signal of collection and collection.The present invention solves the technical problem of timing margins of the uncontrollable data signal in the transmission path that cross clock domain is transmitted in prior art.

Description

Data signal processing method and processing device

Technical Field

The present invention relates to the field of electronic circuits, and in particular, to a method and an apparatus for processing a data signal.

Background

In the conventional scheme of clock domain crossing transmission of data signals, transition edges of one clock signal are usually used to acquire a data signal corresponding to another clock signal, so as to obtain a data signal corresponding to a previous clock signal. However, in this scheme, the timing margin of the data signal on the transmission path of the cross-clock domain transmission is uncontrollable and uncertain, the timing margin may be larger in one case or smaller in another case, and when the timing margin is smaller, the data state is relatively unstable due to the shorter duration of the updated value of the data signal as the acquisition object, and therefore the acquired data is also inaccurate, thereby affecting the reliability of the cross-clock domain transmission of the data signal. In other words, the conventional scheme cannot guarantee that the requirement on the timing margin is met, and the reason for the requirement can be summarized as the problem that the timing margin of the data signal on the transmission path of the clock domain crossing transmission cannot be controlled in the prior art.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

The embodiment of the invention provides a processing method and a processing device of a data signal, which are used for at least solving the technical problem that the timing sequence margin of the data signal on a transmission path for clock domain crossing transmission cannot be controlled in the prior art.

According to an aspect of the embodiments of the present invention, there is provided a method for processing a data signal, including: acquiring a fifth data signal and a sixth data signal according to a first data signal, a second data signal, a third data signal and a fourth data signal, wherein the first data signal, the second data signal, the third data signal and the fourth data signal correspond to a first clock signal, the fifth data signal and the sixth data signal correspond to a second clock signal, the second clock signal is a double frequency clock signal of the first clock signal, and a rising edge of the first clock signal is aligned with a rising edge of the second clock signal, wherein the fifth data signal corresponds to the first data signal when the first clock signal is 1, the sixth data signal corresponds to the third data signal, and the fifth data signal corresponds to the second data signal when the first clock signal is 0, the sixth data signal corresponds to the fourth data signal; acquiring a third clock signal, and acquiring the fifth data signal and the sixth data signal using a rising edge of the third clock signal when a phase difference of the second clock signal with respect to the third clock signal is in a first preset interval, and acquiring the fifth data signal and the sixth data signal using a falling edge of the third clock signal when the phase difference is in a second preset interval, wherein a clock cycle of the third clock signal is the same as a clock cycle of the second clock signal; and obtaining a ninth data signal from a seventh data signal obtained by acquiring the fifth data signal and an eighth data signal obtained by acquiring the sixth data signal, wherein the ninth data signal corresponds to the seventh data signal when the third clock signal is 1, and the ninth data signal corresponds to the eighth data signal when the third clock signal is 0.

According to another aspect of the embodiments of the present invention, there is also provided a data signal processing apparatus, including: an obtaining unit configured to obtain a fifth data signal and a sixth data signal according to a first data signal, a second data signal, a third data signal and a fourth data signal, wherein the first data signal, the second data signal, the third data signal and the fourth data signal correspond to a first clock signal, the fifth data signal and the sixth data signal correspond to a second clock signal, the second clock signal is a double frequency clock signal of the first clock signal, and a rising edge of the first clock signal is aligned with a rising edge of the second clock signal, wherein the fifth data signal corresponds to the first data signal when the first clock signal is 1, the sixth data signal corresponds to the third data signal, and the fifth data signal corresponds to the second data signal when the first clock signal is 0, the sixth data signal corresponds to the fourth data signal; a selecting unit configured to acquire a third clock signal, acquire the fifth data signal and the sixth data signal using a rising edge of the third clock signal when a phase difference between the second clock signal and the third clock signal is within a first preset interval, and acquire the fifth data signal and the sixth data signal using a falling edge of the third clock signal when the phase difference is within a second preset interval, where a clock cycle of the third clock signal is the same as a clock cycle of the second clock signal; and a processing unit configured to obtain a ninth data signal according to a seventh data signal obtained by acquiring the fifth data signal and an eighth data signal obtained by acquiring the sixth data signal, wherein the ninth data signal corresponds to the seventh data signal when the third clock signal is 1, and the ninth data signal corresponds to the eighth data signal when the third clock signal is 0.

In the embodiment of the present invention, a method of selecting, according to a phase difference between a second clock signal and a third clock signal, between acquiring a fifth data signal and a sixth data signal corresponding to the second clock signal by using a rising edge or a falling edge of the third clock signal is adopted to obtain a ninth data signal corresponding to the third clock signal, transmitted at a double rate with respect to the third clock signal, and meeting a requirement for a timing margin transmitted across a clock domain on a transmission path, wherein control over the timing margin can be achieved by combining the selection mechanism with setting of a first preset interval and a second preset interval, thereby solving a technical problem that the timing margin on the transmission path transmitted across the clock domain of the data signal cannot be controlled in the prior art. Further, in the embodiment of the present invention, the design requirement for clock domain crossing transmission of the data signal can be met by reasonably setting the first preset interval and the second preset interval, and the clock domain crossing transmission reliability of the data signal is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of a method of processing a data signal according to an embodiment of the invention;

FIG. 2 is a schematic diagram of cross-clock domain transmission of a data signal according to the prior art;

FIG. 3 is a schematic diagram of another clock domain crossing transmission of a data signal according to the prior art;

FIG. 4 is a schematic diagram of cross-clock domain transmission of a data signal according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another cross-clock domain transmission of a data signal according to an embodiment of the invention;

fig. 6 is a schematic diagram of a data signal processing apparatus according to an embodiment of the present invention;

fig. 7 is a schematic diagram of another data signal processing apparatus according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

Example 1

According to an embodiment of the present invention, there is provided a processing method of a data signal, as shown in fig. 1, the processing method including:

s102: acquiring a fifth data signal and a sixth data signal according to the first data signal, the second data signal, the third data signal and the fourth data signal, wherein the first data signal, the second data signal, the third data signal and the fourth data signal correspond to a first clock signal, the fifth data signal and the sixth data signal correspond to a second clock signal, and the second clock signal is a double-frequency clock signal of the first clock signal, wherein when the first clock signal is 1, the fifth data signal corresponds to the first data signal, the sixth data signal corresponds to the third data signal, when the first clock signal is 0, the fifth data signal corresponds to the second data signal, and the sixth data signal corresponds to the fourth data signal;

s104: acquiring a third clock signal, acquiring a fifth data signal and a sixth data signal by using the rising edge of the third clock signal when the phase difference of the second clock signal relative to the third clock signal is in a first preset interval, and acquiring the fifth data signal and the sixth data signal by using the falling edge of the third clock signal when the phase difference is in a second preset interval, wherein the clock period of the third clock signal is the same as the clock period of the second clock signal;

s106: and obtaining a ninth data signal according to a seventh data signal obtained by collecting the fifth data signal and an eighth data signal obtained by collecting the sixth data signal, wherein the ninth data signal corresponds to the seventh data signal when the third clock signal is 1, and the ninth data signal corresponds to the eighth data signal when the third clock signal is 0.

It should be clear that one of the technical problems to be solved by the technical solutions of the present invention is to provide a method for processing a data signal, so as to implement frequency-doubled cross-clock domain transmission of data carried by 4 paths of data signals, in an embodiment of the present invention, the 4 paths of data signals may be respectively represented as a first data signal, a second data signal, a third data signal, and a fourth data signal, and output data as a processing result may be a ninth data signal carrying data carried by the first to fourth data signals, where the first to fourth data signals correspond to a first clock signal, the ninth data signal corresponds to a double-frequency clock signal of a third clock signal, and a clock period of the first clock signal is twice a clock period of the third clock signal.

In the embodiment of the present invention, the corresponding relationship between the first to fourth data signals and the first clock signal may generally show that the first to fourth data signals are aligned with each other, that is, the update frequency of the first to fourth data signals is consistent with the clock frequency of the first clock signal, and the phases of the first to fourth data signals are the same, however, the present invention is not limited to this, for example, in some embodiments of the present invention, the correspondence between the first data signal and the first clock signal may also be manifested as some determined phase relationship, either orthogonal or anti-equal, in this scenario, although the first data signal and the first clock signal are not aligned, since the phase relationship between the two is determined and known, the timing of the first data signal can still be accurately inferred by the first clock signal so that the first data signal can still be considered to be within the clock domain of the first clock signal.

Similarly, in the embodiment of the present invention, the corresponding relationship between the ninth data signal and the third clock signal may also be represented as similar to the corresponding relationship between the first data signal and the first clock signal, however, it should be noted that the two corresponding relationships are not necessarily completely consistent, for example, in the embodiment of the present invention, the first data signal may be aligned with the first clock signal, and the ninth data signal may be inverted with respect to the third clock signal, which is not limited by the present invention.

According to the method for processing a data signal provided in the embodiment of the present invention, in step S102, first, the first to fourth data signals may be processed to obtain a fifth data signal and a sixth data signal, where the fifth data signal and the sixth data signal may correspond to a second clock signal that is a double frequency signal of the first clock signal, the fifth data signal may carry data carried by the first data signal and the second data signal, and the sixth data signal may carry data carried by the third data signal and the fourth data signal. It is easily understood that, in the above scenario, step S102 may also be regarded as combining the first data signal and the second data signal into a fifth data signal with a double frequency, and combining the third data signal and the fourth data signal into a sixth data signal with a double frequency.

In this embodiment of the present invention, there may be multiple specific implementation manners of step S102, for example, as one of optional manners, step S102 may include:

s1: acquiring the first data signal and the third data signal using a falling edge of the first clock signal, and acquiring the second data signal and the fourth data signal using a rising edge of the first clock signal; or, the first data signal and the third data signal are acquired by using a rising edge of the first clock signal, and the second data signal and the fourth data signal are acquired by using a falling edge of the first clock signal;

s2: and when the first clock signal is 1, using a data signal obtained by collecting the first data signal as the fifth data signal, using a data signal obtained by collecting the third data signal as the sixth data signal, when the first clock signal is 0, using a data signal obtained by collecting the second data signal as the fifth data signal, and using a data signal obtained by collecting the fourth data signal as the sixth data signal.

Of course, the above is only an example, and in the embodiment of the present invention, there may be a plurality of other frequency multiplication methods, for example, 0 and 1 as the determination conditions in step S2 may be interchanged, and the present invention is not limited to this.

On the basis of the above description, according to the processing method of the data signal provided by the embodiment of the present invention, in step S104, the clock domain crossing transmission of the fifth data signal and the sixth data signal from the clock domain of the second clock signal to the clock domain of the third clock signal may be further implemented, so as to obtain the processing operation of the ninth data signal corresponding to the double-frequency signal of the third clock signal according to the seventh data signal and the eighth data signal obtained after the clock domain crossing transmission in step S106.

Based on the above description, the problem to be solved by the present invention in step S104 can also be expressed as: and converting a fifth data signal and a sixth data signal corresponding to the second clock signal into a seventh clock signal and an eighth clock signal corresponding to the third clock signal, respectively, wherein the fifth data signal and the seventh data signal have the same content but different time sequence, and similarly, the sixth data signal and the eighth data signal have the same content but different time sequence. Since the cross-clock-domain transmission of the fifth data signal to the seventh data signal is similar to the cross-clock-domain transmission of the sixth data signal to the eighth data signal, the scheme of the embodiment of the present invention will be mainly described below around the cross-clock-domain transmission of the fifth data signal to the seventh data signal.

In order to implement the above-mentioned cross-clock-domain transmission, in the prior art, a transition edge of the third clock signal is usually used to acquire the fifth data signal to obtain the seventh data signal, for example, in fig. 2, the fifth data signal shown in row 2 may be acquired by using a rising edge of the third clock signal shown in row 3, and the acquired data signal shown in row 4 may be used as the seventh data signal, where as can be seen from fig. 2, the fifth data signal corresponds to the second clock signal, and the seventh data signal corresponds to the third clock signal, so as to implement the cross-clock-domain transmission of the data signal.

It is easy to see that in fig. 2, the timing margin T1 on the transmission path of the fifth data signal shown in row 2 to the seventh data signal shown in row 4 is greater than half the clock cycle T/2, where T represents the clock cycle of the second clock signal, that is, when the fifth data signal is acquired using the rising edge of the third clock signal, the duration of the state in which the fifth data signal is updated to the value a exceeds T/2, so that the data state is relatively easier to recover from the glitch or the like generated by the value update and to transition to a more stable state, and the data acquired using the rising edge of the third clock signal is more accurate, which is advantageous for the transmission of the data signal across the clock domain.

However, in fact, with the above-mentioned prior art scheme, the timing margin of the data signal on the transmission path of the data signal transmitted across the clock domain is uncertain, and in one scenario, such as the scenario shown in fig. 2, the timing margin is large, and in another scenario, such as the scenario shown in fig. 3, the timing margin t2 is relatively small, at least less than half a clock cycle, when the fifth data signal is acquired by using the rising edge of the third clock signal in the scenario, because the duration of updating the fifth data signal to the value a is short, the data state of the fifth data signal may not be stable, and thus the acquired data is also inaccurate, thereby affecting the reliability of the data signal transmitted across the clock domain. In other words, the manner of acquiring the fifth data signal using the rising edge of the third clock signal to generate the seventh data signal cannot guarantee that the requirement for the timing margin is met, and correspondingly, the manner of acquiring the fifth data signal using the falling edge of the third clock signal to generate the seventh data signal also has a similar problem, and the reason for this is summarized as the problem that the timing margin of the data signal on the transmission path of the cross-clock domain transmission cannot be controlled in the prior art.

To solve this problem, in the embodiment of the present invention, a manner of acquiring a fifth data signal by using a third clock signal to generate a seventh data signal may be performed, and the fifth data signal and the third clock signal may be acquired in step S102, however, unlike the prior art, according to the processing method provided in the embodiment of the present invention, in step S104, a selection may be performed between using a rising edge and a falling edge of the third clock signal according to a phase relationship between the second clock signal and the third clock signal, where if a phase difference between the second clock signal and the third clock signal is in a first preset interval, the fifth data signal may be acquired by using the rising edge of the third clock signal, and if the phase difference is in a second preset interval, the fifth data signal may be acquired by using the falling edge of the third clock signal. In other words, in the embodiment of the present invention, instead of statically acquiring the fifth data signal using the rising edge or the falling edge of the third clock signal, one of the rising edge and the falling edge may be selected for different situations to perform acquisition relatively dynamically, so as to control the timing margin of the data signal on the transmission path of the cross-clock transmission, and further meet the requirement of the timing margin.

It should be noted that the "dynamically" selection is not limited to a real-time selection, in the embodiment of the present invention, a period for selecting between the "rising edge acquisition" and the "falling edge acquisition" may be a shorter time period or a longer time period, and the selected mechanism may be further coupled to other mechanisms, for example, a judgment mechanism, wherein the selection may also be triggered according to a result generated by the judgment mechanism, and the like, which is not limited in the present invention. In addition, as an alternative embodiment, the selection mechanism may be implemented by hardware logic, such as a logic circuit, and may be further packaged in a physical interface to improve the integration level and the processing speed and reduce the processing pressure of the processor, or may be implemented by software logic, such as programming a programmable platform, such as an MCU, an FPGA, or a PLC, which is not limited in this disclosure.

The working principle of the solution of an embodiment of the invention will be explained in detail below with reference to fig. 4 and 5. In an embodiment of the present invention, the first preset interval may be set to (T/2, T), and the second preset interval may be set to (0, T/2). In the present application, the phase difference of the second clock signal with respect to the third clock signal indicates the amount of advance of the second clock signal with respect to the third clock signal, and for example, when the second clock signal is advanced 1/4 clock cycles with respect to the third clock signal, the phase difference of the second clock signal with respect to the third clock signal is 1/4 clock cycles.

As shown in fig. 4, in one scenario of the embodiment of the present invention, the second clock signal may be the clock signal shown in line 1, the fifth data signal may be the data signal shown in line 2, and the third clock signal may be the clock signal shown in line 3. In the above scenario, the phase difference of the second clock signal relative to the third clock signal is greater than half a clock cycle, that is, the second clock signal is located in the first preset interval (T/2, T), so that according to step S104, the fifth data signal may be collected by using the rising edge of the third clock signal, and the data signal shown in row 4 is obtained as the seventh data signal. It is easy to see that in the above scenario, the fifth data signal corresponds to the second clock signal, the seventh data signal corresponds to the third clock signal, and the data content of the seventh data signal is identical to the fifth data signal, i.e. a clock domain crossing transmission of the fifth data signal is achieved, on the other hand, the timing margin on the transmission path of the cross-clock domain transmission is equal to the phase difference, and the phase difference is located in the first predetermined interval and is greater than half a clock cycle, so the timing margin is greater than half a clock cycle, that is, in the embodiment of the present invention, the control of the timing margin can be partly realized by the first preset interval, so that the requirement of the timing margin can be met through reasonable setting of the first preset interval, therefore, the effects of accurately acquiring data and improving the reliability of clock domain crossing transmission of the data signals are achieved.

In contrast, in the above scenario, if the falling edge of the third clock signal is selected to acquire the fifth data signal, the acquired data signal may be the data signal as shown by the dashed line in fig. 4, line 5, and it is easy to see that the timing margin of the acquired data signal with respect to the fifth data signal is less than half a clock cycle, and does not meet the requirement for the timing margin corresponding to the first preset interval, which may further cause a problem of low reliability of the data signal transmission across the clock domain.

As shown in fig. 5, in another scenario of the embodiment of the present invention, the second clock signal may be the clock signal shown in line 1, the fifth data signal may be the data signal shown in line 2, and the third clock signal may be the clock signal shown in line 3. In the above scenario, the phase difference between the second clock signal and the third clock signal is less than half a clock cycle, that is, the second clock signal is located in a second preset interval (0, T/2), so that according to step S104, the fifth data signal can be collected by using the falling edge of the third clock signal, and the data signal shown in line 5 is obtained as the seventh data signal. It is easy to see that, in the above scenario, on the basis of implementing the clock domain crossing transmission of the fifth data signal, the timing margin on the transmission path of the clock domain crossing transmission is equal to the phase difference plus a half clock cycle, and the phase difference is within the second preset interval and less than a half clock cycle, so that the timing margin is greater than a half clock cycle, that is, in the embodiment of the present invention, the control of the timing margin may be partially implemented by the second preset interval, so that the requirement for the timing margin may be met by reasonably setting the second preset interval, and the effects of accurately acquiring data and improving the reliability of the clock domain crossing transmission of the data signal are achieved.

In contrast, in the above scenario, if the rising edge of the third clock signal is selected to acquire the fifth data signal, the acquired data signal may be the data signal as shown by the dashed line in fig. 5, row 4, and it is easy to see that the timing margin of the acquired data signal with respect to the fifth data signal is less than half a clock cycle, and does not meet the requirement for the timing margin corresponding to the second preset interval, which may further cause a problem of low reliability of the data signal transmission across the clock domain.

Through the above embodiments, the working principle of the scheme of the embodiment of the present invention is explained. Correspondingly, in the embodiment of the present invention, the sixth data signal may also be processed in a similar manner to obtain the eighth data signal, and the same problem may be solved and the same effect may be achieved, which is not described herein in detail.

It should be noted that, in the embodiment of the present invention, for the first preset interval, the timing margin defined by the first preset interval is usually the first preset interval itself, and for the second preset interval, when the partial interval in the second preset interval is set to be located at (0, T/2), the timing margin defined by the partial interval is the partial interval plus a half clock cycle, and when the partial interval in the second preset interval is set to be located at (T/2, T), the timing margin defined by the partial interval will actually be represented as the partial interval minus a half clock cycle. That is, if the timing margin of the data signal transmitted across the clock domain on the transmission path is required to be large, the first preset interval may be set within (T/2, T), and the second preset interval may be set within (0, T/2), otherwise, the first preset interval may be set within (0, T/2), and the second preset interval may be set within (T/2, T). The specific settings and applications of the first preset interval and the second preset interval are not limited in any way.

Of course, the above conclusion is mainly derived based on the corresponding relationship between the fifth data signal and the second clock signal, and the seventh data signal and the third clock signal are aligned, in some other embodiments of the present invention, for other expressions of the corresponding relationship, the determined phase relationship between the fifth data signal and the second clock signal and the determined phase relationship between the seventh data signal and the third clock signal may be combined to obtain the range of timing margins defined by the first preset interval and the second preset interval after two offsets corresponding to the two phase relationships, respectively, and a similar processing manner may also be applied to the process of transmitting the sixth data signal to the eighth data signal across the clock domain, which is not described herein in detail.

On the basis of the above description, according to the processing method of the data signal provided by the embodiment of the invention, in step S106, a ninth data signal may be obtained from the seventh data signal and the eighth data signal, in the embodiment of the present invention, the implementation of step S106 may adopt a frequency doubling processing manner similar to the implementation of step S102, or according to specific design requirements, possible further processing is performed on the seventh data signal and the eighth data signal before the ninth data signal is obtained, e.g., delayed, inverted, reacquired, registered one or more beats, etc., and generates a ninth data signal from the processed data signal, it should be understood, however, in the above processing, all should belong to the processing in the clock domain of the third clock signal, i.e. the obtained ninth data signal should still correspond to the third clock signal.

For example, optionally, in the embodiment of the present invention, step S106 may include:

s3: the following operations are performed N times: acquiring the data signal acquired in the previous operation of the N times of operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired in the previous operation of the N times of operations is the seventh data signal, and N is greater than or equal to 1; and/or the presence of a gas in the gas,

s4: performing the following operations M times: acquiring the data signal acquired by the previous operation in the M operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired by the previous operation in the M operations is the eighth data signal, and M is greater than or equal to 1;

s5: and when the third clock signal is 1, taking the seventh data signal or the data signal acquired after the N operations as the ninth data signal, and when the first clock signal is 0, taking the eighth data signal or the data signal acquired after the M operations as the ninth data signal.

In the above scenario, after the fifth data signal and the sixth data signal are collected through step S104, the fifth data signal and/or the sixth data signal are acquired again in step S3 and/or step S4, and this "reacquisition" operation may be repeated N and M times, respectively, N, M being greater than or equal to 1, it should be noted that, in the embodiment of the present invention, the N operations are not limited to "using the rising edge of the third clock signal" or "using the falling edge of the third clock signal", in one embodiment, for example, one of the N operations may use rising edge acquisition, the next operation of the operation may use a falling edge acquisition, and similarly, the above M operations are not limited to using a rising edge or a falling edge, and the present invention is not limited thereto.

It should be understood that in the embodiment of the present invention, the data signals obtained by the N and M reacquisition operations respectively performed by using the transition edge of the third clock signal will still be in the clock domain of the third clock signal, and the ninth data signal obtained thereby will also be in the clock domain of the third clock signal. In general, in the case where the above-mentioned "previous acquisition" including the acquisition operation of the fifth data signal and the sixth data signal described in step S104 uses the rising edge of the third clock signal, for the reacquisition performed after the previous acquisition, if the rising edge of the third clock signal is still used, it is equivalent to delaying the data signal acquired in the previous acquisition by one clock cycle or registering one beat, and if the falling edge of the third clock signal is used instead, it is equivalent to delaying the data signal acquired in the previous acquisition by half a clock cycle or registering one beat, and accordingly, similar effects can be obtained also in the case where the falling edge of the third clock signal is used for the previous acquisition. In the method, no matter whether half-beat, one-beat or multi-beat is registered, the timing margin in the secondary acquisition is at least half clock period, so that the problem of accuracy and reliability reduction caused by insufficient timing margin of the data signal on a transmission path can be avoided.

Further, in order to facilitate the acquisition of the ninth data signal in step S5, the present invention provides the following two alternative embodiments, which define the above-mentioned N operations and M operations, so as to implement the pre-processing of the seventh data signal and/or the eighth data signal in steps S3 and/or S4:

1) if the phase difference is within the first preset interval, the N operations in step S3 may be: the seventh data signal is collected again by using the falling edge of the third clock signal, and the M operations in step S4 may be: acquiring the eighth data signal again by using the rising edge of the third clock signal;

if the phase difference is within the second predetermined interval, the M operations in step S4 are: the eighth data signal is reacquired using the rising edge of the third clock signal.

2) If the phase difference is within the first preset interval, the M operations in step S4 may be: the eighth data signal is collected again by using the falling edge of the third clock signal;

if the phase difference is within the second predetermined interval, the N operations in step S3 may be: the seventh data signal is collected again by using the rising edge of the third clock signal, and the M operations in step S4 may be: the eighth data signal is reacquired using the falling edge of the third clock signal.

The present invention is illustrated in two alternative embodiments by the above examples, however, it should be understood that the above examples are only for understanding the technical solutions of the present invention, and should not be construed as limiting the present invention. In the embodiments of the present invention, there may be other possible embodiments, which are not described herein, and it should be understood that these embodiments are all considered to be within the scope of the present invention.

Based on the above description, more specifically, in the embodiment of the present invention, the first clock signal may be a system clock of a memory controller, the second clock signal is a double-frequency clock of the system clock, the third clock signal may be a write data clock of the memory controller, the first data signal, the second data signal, the third data signal, and the fourth data signal may be data to be transmitted by the memory controller, and the ninth data signal may be write data transmitted to the memory chip by the memory controller, where clock cycles of the write data clock and the memory clock of the memory chip may be the same, and a preset timing requirement may be satisfied between the write data clock and the memory clock.

In this scenario, in combination with the method for processing a data signal provided in the embodiment of the present invention, effective transmission of data to be transmitted from a memory controller to a memory chip may be achieved, where the data to be transmitted may be a data signal corresponding to a system clock acquired or generated by the memory controller, and write data obtained through the above processing operation may be a data signal corresponding to a write data clock, so as to facilitate receiving and identifying the write data by the memory. Although the write data clock may also be obtained or generated by the memory controller, the write data clock and the memory clock should meet the predetermined timing requirement. The adjustment operation for the write data clock will be given in the subsequent embodiment.

Generally, in the embodiment of the present invention, the preset timing requirement may be expressed as: the write data generated according to the write data clock advances by K clock cycles relative to the memory clock when reaching the memory chip, where K is an arbitrary value between 0 and 1. Such a requirement is generally associated with the DDR protocol, for example, the current DDR protocol provides that when write data arrives at the memory chip, a transition edge of the memory clock should be located in the middle of the write data obtained by the memory chip, or the write data arrives at the memory chip about 1/4 or 3/4 clock cycles ahead of the memory clock, so that K may be set to 1/4 or 3/4, but the present invention is not limited to this, and in other embodiments of the present invention, the specific value of K may be set to other values between 0 and 1 for different memory data transmission protocols.

Further optionally, in this embodiment of the present invention, before step S102, the processing method may further include:

s6: repeatedly executing the following operations for P times before meeting the execution termination condition corresponding to the preset time sequence requirement:

s7, adjusting the write data clock or the fourth clock signal lagging K clock cycles with respect to the write data clock forward or backward, and transmitting a tenth data signal corresponding to the adjusted write data clock or the adjusted fourth clock signal to the memory chip;

s8, receiving an eleventh data signal returned by the memory chip according to the tenth data signal, and judging whether the execution termination condition is met according to the received eleventh data signal; wherein P is greater than or equal to 1.

One loop formed by steps S7 and S8 can be summarized as: the eleventh data signal fed back to the memory chip according to the tenth data signal fed to the memory chip may generally carry information corresponding to "whether a termination execution condition is satisfied" or whether a preset timing requirement is satisfied between the write data clock and the memory clock ", so that whether a cycle is terminated may be determined by identifying and determining the eleventh data signal, and the write data clock obtained after the above-mentioned P operations or the write data clock determined according to the fourth clock signal obtained after the P operations may be used as the third clock signal determined before the clock domain crossing transmission of the data signal is performed, so as to be the basis for the selection according to the phase difference in step S104. It is noted that the above-described loop may also have other equivalent variations, for example, an equivalent loop may also be summarized as: the present invention is not limited to the division of a single operation or a cycle of P operations, and the embodiments described above should be considered within the scope of the present invention.

In general, in an embodiment of the present invention, the condition for ending the execution of the P operations may correspond to achievement of a predetermined timing requirement, for example, in an embodiment, the tenth data signal may be set as a pulse signal aligned with a rising edge or a falling edge of the fourth clock signal, and the eleventh data signal may represent a data signal obtained by the memory chip using the pulse signal to acquire the memory clock, where if the rising edges of the tenth data signal and the fourth clock signal are aligned, the condition for ending the execution may be: the received eleventh data signal changes from 0 to 1; if the tenth data signal is aligned with the falling edge of the fourth clock signal, the abort condition may be: the received eleventh data signal changes from 1 to 0.

Since the fourth clock signal lags behind the write data clock by K clock cycles, if the write data generated according to the write data clock is required to be advanced by K clock cycles relative to the memory clock when reaching the memory chip, the tenth data signal generated according to the fourth clock signal should be required to be aligned with the memory clock when reaching the memory chip. On the other hand, when the eleventh data signal obtained by the memory chip collecting the memory clock according to the tenth data signal received by the memory chip changes from 0 to 1, it can be considered that the pulse signal as the tenth data signal captures a rising edge of the eleventh data signal, and when the eleventh data signal changes from 1 to 0, it can be considered that the pulse signal captures a falling edge of the eleventh data signal. Therefore, if the rising edges of the tenth data signal and the fourth clock signal are aligned, the termination execution condition corresponding to the preset timing requirement may be set to capture the rising edge of the memory clock when the tenth data signal reaches the memory chip, that is, the eleventh data signal is changed from 0 to 1, and if the falling edges of the tenth data signal and the fourth clock signal are aligned, the termination execution condition corresponding to the preset timing requirement may be set to capture the falling edge of the memory clock when the tenth data signal reaches the memory chip, that is, the eleventh data signal is changed from 1 to 0.

In particular, for DDR3, in some embodiments of the present invention, the write level function provided by the DDR3 memory may be utilized, and in this scenario, the DDR3 memory may be first placed in the write level mode, and the write data strobe signal (write DQS) is used as the fourth clock signal, so as to perform the above-mentioned P operations.

Further, in the embodiment of the present invention, since the adjustment of the write data clock and/or the fourth clock signal in step S7 may reflect the phase shift of the write data clock as the third clock signal, the phase difference between the second clock signal and the third clock signal, which is used as the basis for selection in step S104, may also be obtained according to the adjustment performed by the above-mentioned P operations. Wherein, optionally,

before executing the P operations, the processing method may further include: s9, taking the clock signal aligned with the system clock as the initial value of the write data clock or the fourth clock signal;

when performing P operations, the adjusting the write data clock and/or the fourth clock signal forward or backward in step S7 may include: s10, delaying the write data clock or the fourth clock signal for 1/L clock cycles as the adjusted write data clock or the fourth clock signal, wherein L is a positive integer; and the number of the first and second groups,

after performing the P operations, the processing method may further include: s11, if the clock signal aligned with the system clock is used as the write data clock, the phase difference is obtained according to the following formula: Δ = (P/L) × T; s16, if the clock signal aligned with the system clock is used as the fourth clock signal, the phase difference is obtained according to the following formula: Δ = (P/L-K) × T; where Δ represents the phase difference and T represents the clock period.

In the above scenario, the larger the value of L is, the smaller the adjustment amount of the write data clock or the fourth clock signal in a single operation is, the more accurate the calibration of the write data clock or the fourth clock signal is, the closer the timing between the write data clock and the memory clock is to the preset timing requirement, and on the other hand, the more accurate the phase difference Δ obtained according to the calibration is, so that the more accurate the control of the timing margin on the transmission path of the data signal across the clock domain by the processing method of the data signal is.

The present invention is further explained by providing a preferred embodiment, but it should be noted that the preferred embodiment is only for better describing the present invention and should not be construed as unduly limiting the present invention.

Example 2

According to an embodiment of the present invention, there is also provided a data signal processing apparatus for implementing the above data signal processing method, as shown in fig. 6, the processing apparatus including:

1) an obtaining unit 602, configured to obtain a fifth data signal and a sixth data signal according to a first data signal, a second data signal, a third data signal, and a fourth data signal, where the first data signal, the second data signal, the third data signal, and the fourth data signal correspond to a first clock signal, the fifth data signal and the sixth data signal correspond to a second clock signal, and the second clock signal is a double-frequency clock signal of the first clock signal, where when the second clock signal is 1, the fifth data signal corresponds to the first data signal, the sixth data signal corresponds to the third data signal, and when the second clock signal is 0, the fifth data signal corresponds to the second data signal, and the sixth data signal corresponds to the fourth data signal;

2) the selecting unit 604 is configured to acquire a third clock signal, acquire a fifth data signal and a sixth data signal using a rising edge of the third clock signal when a phase difference of the second clock signal with respect to the third clock signal is in a first preset interval, and acquire the fifth data signal and the sixth data signal using a falling edge of the third clock signal when the phase difference is in a second preset interval, where a clock cycle of the third clock signal is the same as a clock cycle of the second clock signal;

3) the processing unit 606 is configured to obtain a ninth data signal according to a seventh data signal obtained by collecting the fifth data signal and an eighth data signal obtained by collecting the sixth data signal, where the ninth data signal corresponds to the seventh data signal when the third clock signal is 1, and the ninth data signal corresponds to the eighth data signal when the third clock signal is 0.

It should be clear that one of the technical problems to be solved by the technical solutions of the present invention is to provide a device for processing a data signal, so as to implement frequency-doubled cross-clock domain transmission of data carried by 4 paths of data signals, in an embodiment of the present invention, the 4 paths of data signals may be respectively represented as a first data signal, a second data signal, a third data signal, and a fourth data signal, and output data as a processing result may be a ninth data signal carrying data carried by the first to fourth data signals, where the first to fourth data signals correspond to a first clock signal, the ninth data signal corresponds to a double-frequency clock signal of a third clock signal, and a clock period of the first clock signal is twice a clock period of the third clock signal.

According to the apparatus for processing a data signal provided in the embodiment of the present invention, in the obtaining unit 602, first, the first to fourth data signals may be processed to obtain a fifth data signal and a sixth data signal, where the fifth data signal and the sixth data signal may correspond to a second clock signal that is a double frequency signal of the first clock signal, the fifth data signal may carry data carried by the first data signal and the second data signal, and the sixth data signal may carry data carried by the third data signal and the fourth data signal. It is to be easily understood that, in the above scenario, the obtaining unit 602 may also be regarded as combining the first data signal and the second data signal into a fifth data signal with a double frequency, and combining the third data signal and the fourth data signal into a sixth data signal with a double frequency.

In this embodiment of the present invention, specific implementations of the obtaining unit 602 may be multiple, for example, as one of optional implementations, the obtaining unit 602 may include:

1) a first acquisition module, configured to acquire the first data signal and the third data signal using a falling edge of the first clock signal, and acquire the second data signal and the fourth data signal using a rising edge of the first clock signal; or, the first data signal and the third data signal are acquired by using a rising edge of the first clock signal, and the second data signal and the fourth data signal are acquired by using a falling edge of the first clock signal;

2) the first processing module is configured to, when the first clock signal is 1, use a data signal obtained by acquiring the first data signal as the fifth data signal, use a data signal obtained by acquiring the third data signal as the sixth data signal, when the first clock signal is 0, use a data signal obtained by acquiring the second data signal as the fifth data signal, and use a data signal obtained by acquiring the fourth data signal as the sixth data signal.

On the basis of the above description, according to the data signal processing apparatus provided by the embodiment of the present invention, in the selection unit 604, clock domain crossing transmission of the fifth data signal and the sixth data signal from the clock domain of the second clock signal to the clock domain of the third clock signal may be further implemented, so as to obtain, in the processing unit 606, a processing operation of the ninth data signal corresponding to the double-frequency signal of the third clock signal according to the seventh data signal and the eighth data signal obtained after clock domain crossing transmission.

Based on the above description, the problem to be solved by the present invention in the selection unit 604 can also be expressed as: and converting a fifth data signal and a sixth data signal corresponding to the second clock signal into a seventh clock signal and an eighth clock signal corresponding to the third clock signal, respectively, wherein the fifth data signal and the seventh data signal have the same content but different time sequence, and similarly, the sixth data signal and the eighth data signal have the same content but different time sequence. Since the cross-clock-domain transmission of the fifth data signal to the seventh data signal is similar to the cross-clock-domain transmission of the sixth data signal to the eighth data signal, the scheme of the embodiment of the present invention will be mainly described below around the cross-clock-domain transmission of the fifth data signal to the seventh data signal.

To solve the problem, in the embodiment of the present invention, a manner of acquiring a fifth data signal by using a third clock signal to generate a seventh data signal may be performed, and the fifth data signal and the third clock signal may be acquired in the acquiring unit 602, however, unlike the prior art, according to the processing apparatus provided in the embodiment of the present invention, in the selecting unit 604, a selection may be performed between a rising edge and a falling edge of the third clock signal according to a phase relationship between the second clock signal and the third clock signal, wherein if a phase difference between the second clock signal and the third clock signal is in a first preset interval, the fifth data signal may be acquired by using the rising edge of the third clock signal, and if the phase difference is in a second preset interval, the fifth data signal may be acquired by using the falling edge of the third clock signal. In other words, in the embodiment of the present invention, instead of statically acquiring the fifth data signal using the rising edge or the falling edge of the third clock signal, one of the rising edge and the falling edge may be selected for different situations to perform acquisition relatively dynamically, so as to control the timing margin of the data signal on the transmission path of the cross-clock transmission, and further meet the requirement of the timing margin.

As shown in fig. 4, in one scenario of the embodiment of the present invention, the second clock signal may be the clock signal shown in line 1, the fifth data signal may be the data signal shown in line 2, and the third clock signal may be the clock signal shown in line 3. In the above scenario, the phase difference of the second clock signal relative to the third clock signal is greater than half a clock cycle, that is, the second clock signal is located in the first preset interval (T/2, T), so that according to the selection unit 604, the fifth data signal can be collected by using the rising edge of the third clock signal, and the data signal shown in the 4 th row is obtained as the seventh data signal. It is easy to see that in the above scenario, the fifth data signal corresponds to the second clock signal, the seventh data signal corresponds to the third clock signal, and the data content of the seventh data signal is identical to the fifth data signal, i.e. a clock domain crossing transmission of the fifth data signal is achieved, on the other hand, the timing margin on the transmission path of the cross-clock domain transmission is equal to the phase difference, and the phase difference is located in the first predetermined interval and is greater than half a clock cycle, so the timing margin is greater than half a clock cycle, that is, in the embodiment of the present invention, the control of the timing margin can be partly realized by the first preset interval, so that the requirement of the timing margin can be met through reasonable setting of the first preset interval, therefore, the effects of accurately acquiring data and improving the reliability of clock domain crossing transmission of the data signals are achieved.

As shown in fig. 5, in another scenario of the embodiment of the present invention, the second clock signal may be the clock signal shown in line 1, the fifth data signal may be the data signal shown in line 2, and the third clock signal may be the clock signal shown in line 3. In the above scenario, the phase difference between the second clock signal and the third clock signal is less than half a clock cycle, that is, the second clock signal is located in a second preset interval (0, T/2), so that according to the selection unit 604, the fifth data signal can be collected by using the falling edge of the third clock signal, and the data signal shown in line 5 is obtained as the seventh data signal. It is easy to see that, in the above scenario, on the basis of implementing the clock domain crossing transmission of the fifth data signal, the timing margin on the transmission path of the clock domain crossing transmission is equal to the phase difference plus a half clock cycle, and the phase difference is within the second preset interval and less than a half clock cycle, so that the timing margin is greater than a half clock cycle, that is, in the embodiment of the present invention, the control of the timing margin may be partially implemented by the second preset interval, so that the requirement for the timing margin may be met by reasonably setting the second preset interval, and the effects of accurately acquiring data and improving the reliability of the clock domain crossing transmission of the data signal are achieved.

On the basis of the above description, according to the processing device of the data signal provided by the embodiment of the invention, in the processing unit 606, a ninth data signal may be obtained from the seventh data signal and the eighth data signal, in the embodiment of the present invention, the implementation of the processing unit 606 may adopt a frequency multiplication processing manner similar to the implementation manner of the obtaining unit 602, or according to specific design requirements, possible further processing is performed on the seventh data signal and the eighth data signal before the ninth data signal is obtained, e.g., delayed, inverted, reacquired, registered one or more beats, etc., and generates a ninth data signal from the processed data signal, it should be understood, however, in the above processing, all should belong to the processing in the clock domain of the third clock signal, i.e. the obtained ninth data signal should still correspond to the third clock signal.

For example, optionally, in the embodiment of the present invention, the processing unit 606 may include:

1) a second acquisition module for performing the following operations N times: acquiring the data signal acquired in the previous operation of the N times of operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired in the previous operation of the N times of operations is a seventh data signal, and N is more than or equal to 1; and/or performing the following operations M times: acquiring the data signal acquired by the previous operation in the M operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired by the previous operation in the M operations is an eighth data signal, and M is more than or equal to 1;

2) and the second processing module is used for taking the seventh data signal or the data signal acquired after N times of operations as a ninth data signal when the third clock signal is 1, and taking the eighth data signal or the data signal acquired after M times of operations as the ninth data signal when the first clock signal is 0.

In the above scenario, after the fifth data signal and/or the sixth data signal are acquired by the selection unit 604, the fifth data signal and/or the sixth data signal may be acquired again in the second acquisition module, and the operation of "acquiring again" may be repeatedly performed N times and M times, respectively, where N, M is greater than or equal to 1, where, in an embodiment of the present invention, the above N operations are not limited to all being "using a rising edge of the third clock signal" or "using a falling edge of the third clock signal", for example, in an embodiment, a certain operation of the N operations may use rising edge acquisition, a next operation of the operation may use falling edge acquisition, and similarly, the above M operations are not limited to all being using rising edges or falling edges, and the present invention is not limited thereto.

It should be understood that in the embodiment of the present invention, the data signals obtained by the N and M reacquisition operations respectively performed by using the transition edge of the third clock signal will still be in the clock domain of the third clock signal, and the ninth data signal obtained thereby will also be in the clock domain of the third clock signal. In general, in the case where the above-mentioned "previous acquisition" including the acquisition operation of the fifth data signal and the sixth data signal described in the selection unit 604 uses the rising edge of the third clock signal, for the reacquisition performed after the previous acquisition, if the rising edge of the third clock signal is still used, it is equivalent to delaying the data signal acquired in the previous acquisition by one clock cycle or registering one beat, and if the falling edge of the third clock signal is used instead, it is equivalent to delaying the data signal acquired in the previous acquisition by half a clock cycle or registering one beat, and accordingly, similar effects can be obtained also in the case where the falling edge of the third clock signal is used for the previous acquisition. In the method, no matter whether half-beat, one-beat or multi-beat is registered, the timing margin in the secondary acquisition is at least half clock period, so that the problem of accuracy and reliability reduction caused by insufficient timing margin of the data signal on a transmission path can be avoided.

Further, in order to facilitate the acquisition of the ninth data signal in the second processing module, the invention provides the following two alternative embodiments to limit the above-mentioned N operations and M operations, so as to implement the preprocessing of the seventh data signal and/or the eighth data signal in the second acquisition module:

1) if the phase difference is within a first preset interval, the N operations in the second acquisition module may be: and acquiring the seventh data signal again by using the falling edge of the third clock signal, wherein the M operations can be: acquiring the eighth data signal again by using the rising edge of the third clock signal;

if the phase difference is within a second preset interval, the M operations in the second acquisition module may be: the eighth data signal is reacquired using the rising edge of the third clock signal.

2) If the phase difference is within a first preset interval, the M operations in the second acquisition module may be: the eighth data signal is collected again by using the falling edge of the third clock signal;

if the phase difference is within a second preset interval, the N operations in the second acquisition module may be: and acquiring the seventh data signal again by using the rising edge of the third clock signal, wherein the M operations can be as follows: the eighth data signal is reacquired using the falling edge of the third clock signal.

In this scenario, in combination with the data signal processing apparatus provided in the embodiment of the present invention, effective transmission of data to be transmitted from a memory controller to a memory chip may be achieved, where the data to be transmitted may be a data signal that is acquired or generated by the memory controller and corresponds to a system clock, and write data obtained through the processing operation may be a data signal that corresponds to a write data clock, so as to facilitate receiving and identifying the write data by the memory. Although the write data clock may also be obtained or generated by the memory controller, the write data clock and the memory clock should meet the predetermined timing requirement. The adjustment operation for the write data clock will be given in the subsequent embodiment.

Further optionally, in this embodiment of the present invention, before the obtaining unit 602, the processing apparatus may further include:

1) an adjusting unit, configured to repeatedly execute P times of the following operations before a termination execution condition corresponding to a preset timing requirement is satisfied: adjusting the write data clock or a fourth clock signal lagging the write data clock by K clock cycles forward or backward, and transmitting a tenth data signal corresponding to the adjusted write data clock or the adjusted fourth clock signal to the memory chip; receiving an eleventh data signal returned by the memory chip according to the tenth data signal, and judging whether the execution termination condition is met according to the received eleventh data signal; wherein P is greater than or equal to 1.

One cycle formed in the adjustment unit can be summarized as: the eleventh data signal fed back to the memory chip according to the tenth data signal fed to the memory chip may generally carry information corresponding to "whether a termination execution condition is satisfied" or whether a preset timing requirement is satisfied between the write data clock and the memory clock ", so that whether a cycle is terminated may be determined by identifying and determining the eleventh data signal, and the write data clock obtained after the above-mentioned P operations or the write data clock determined according to the fourth clock signal obtained after the P operations may be used as the third clock signal determined before the clock domain crossing transmission of the data signal is performed, so as to be used as the basis for the selection according to the phase difference in the selection unit 604. It is noted that the above-described loop may also have other equivalent variations, for example, an equivalent loop may also be summarized as: the present invention is not limited to the division of a single operation or a cycle of P operations, and the embodiments described above should be considered within the scope of the present invention.

Further, in the embodiment of the present invention, since the adjustment of the write data clock and/or the fourth clock signal in the adjustment unit may reflect the phase shift of the write data clock as the third clock signal, the phase difference between the second clock signal and the third clock signal according to the selection in the selection unit 604 may also be obtained according to the adjustment completed by the above-mentioned P operations. Wherein, optionally,

the processing apparatus may further include: an initialization unit configured to use a clock signal aligned with a system clock as an initial value of a write data clock or a fourth clock signal; wherein,

the adjusting unit may include: the delay module is used for delaying the write data clock or the fourth clock signal for 1/L clock cycles as the adjusted write data clock or the fourth clock signal, and L is a positive integer; wherein,

the processing apparatus may further include: a calculating module, configured to obtain the phase difference according to the following formula when a clock signal aligned with a system clock is used as a write data clock: Δ = (P/L) × T; when the clock signal aligned with the system clock is taken as the fourth clock signal, the phase difference is obtained according to the following equation: Δ = (P/L-K) × T; where Δ represents the phase difference and T represents the clock period.

In the above scenario, the larger the value of L is, the smaller the adjustment amount of the write data clock or the fourth clock signal in a single operation is, the more accurate the calibration of the write data clock or the fourth clock signal is, the closer the timing between the write data clock and the memory clock is to the preset timing requirement, and on the other hand, the more accurate the phase difference Δ obtained according to the calibration is, so that the more accurate the processing apparatus of the data signal controls the timing margin on the transmission path of the data signal which is transmitted across the clock domain.

Example 3

According to an embodiment of the present invention, there is also provided an apparatus for processing a data signal implemented by hardware logic, as shown in fig. 7, the apparatus may include:

1) registers REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8, and REG 9;

2) selector MUX1, MUX2, MUX3, MUX4, and MUX 5;

fig. 7 may be referred to for connection relationships between the devices, which is not described in detail herein.

As shown in fig. 7, the clock inputs of REG1 and REG3 may be both the inverse of the clock signal clk1, and the clock inputs of REG2 and REG4 may be both clk1, where clk1 may be the first clock signal as described in embodiment 2. The data input of REG1 may be data signal dq1, the data input of REG2 may be data signal dq2, and the combination of dq1 and dq2 may be implemented by selector MUX1, so as to obtain one-way data signal dq5 carrying data of dq1 and dq2, where the transmission rate of dq5 is twice that of dq1 and dq 2. Similarly, the data input of REG3 may be data signal dq3, the data input of REG4 may be data signal dq4, and the combination of dq3 and dq4 may be implemented by selector MUX2, so as to obtain one-way data signal dq6 carrying data of dq3 and dq4, where the transmission rate of dq6 is twice that of dq3 and dq 4. Specifically, in an embodiment of the present invention, dq1 to dq6 may correspond to the first to sixth data signals described in embodiment 2, respectively, where dq1 to dq4 correspond to clk1, and dq5 and dq6 correspond to clk2 as the second clock signal described in embodiment 2.

The REGs 1 to REG4 and the MUX1 and MUX2 can implement the four-way data signal synchronized with the first clock signal and the two-way data signal synchronized with the second clock signal, in other words, the embodiment of the present invention provides a feasible hardware implementation of the obtaining unit as described in embodiment 2, while the obtaining of the third clock signal required to be performed by the selecting unit as described in embodiment 2 can be implemented simply through one terminal, for example, the terminal marked with clk3 on the left side in fig. 7, for the input of the clock signal clk3, wherein clk3 can be used as the third clock signal as described in embodiment 2.

Further, in the embodiment of the present invention, the selective capture operation required to be performed by the selection unit as described in embodiment 2 may be implemented by REG5, REG6, REG7, and REG8, and selectors MUX3 and MUX 4.

As shown in fig. 7, the clock inputs of REG5, REG6, REG7, and REG8 may all be clock signals clk 3. The data inputs of REG5 and REG8 may be dq5, and the data inputs of REG6 and REG7 may be dq6, so that REG5, REG6, REG7, and REG8 may all function to collect the data signal dq5 or dq6 located in the clock domain of clk2 to obtain the data signal located in the clock domain of clk3, i.e., to enable clock domain crossing transmission of the data signal.

Specifically, as shown in fig. 7, the clock inputs of REG5 and REG6 are clk3 directly, that is, using the rising edge of clk3 for acquisition, and the clock inputs of REG7 and REG8 are each input to clk3 through an inverter, that is, using the falling edge of clk3 for acquisition, as to which of the rising edge and the falling edge of clk3 is specifically used for acquisition, may be accomplished through a selector MUX3 and MUX4, wherein the low level inputs of MUX3 and MUX4 may correspond to the acquisition mode using the rising edge of clk3, the high level input may correspond to the acquisition mode using the falling edge of clk3, the control input may be used to input an electrical signal pm corresponding to the phase difference between clk2 and clk3, where the phase difference is located at (T/2, T) which is the first preset interval as described in embodiment 2, pm may be low level, and further the rising edge of 3 may be used to acquire the data signal corresponding to clk2, when the phase difference is at (0, T/2) which is the second preset interval as described in embodiment 2, pm may be high, and the falling edge of clk3 may be used to acquire the data signal corresponding to clk 2.

By the above selective acquisition manner, the timing margin of the data signals dq1 to dq4 on the clock domain crossing transmission path can be ensured, thereby improving the accuracy of data transmission, which will not be described in detail herein.

Further, as shown in fig. 7, after the data signal in the clock domain of clk2 is collected by REG5, REG6 or REG7, the collected data signal may be collected again, where pm is low when the phase difference is in the first preset interval, the data signal obtained by collecting dq5 by REG5 may be collected again by REG8 using the falling edge of clk3 to obtain dq7 of the seventh data signal as described in embodiment 2, and the data signal obtained by collecting dq6 by REG6 may be collected again by REG9 using the rising edge of clk3 to obtain the eighth data signal dq8 as described in embodiment 2. Of course, the processing unit as described in embodiment 2 may also directly output the data signal obtained by first collecting clk3, for example, as shown in fig. 7, when the phase difference is in the second preset interval, pm is high level, and dq5 directly passes through REG8, and obtains the seventh data signal dq7 in the second data signal as described in embodiment 2 after one collection of the falling edge of clk3, which is not limited by the invention. Specifically, in the embodiment of the present invention, dq7 and dq8 may correspond to the seventh data signal and the eighth data signal described in embodiment 2, respectively, where dq7 and dq8 correspond to clk 3.

The invention in fact gives a hardware implementation of the second acquisition module as described in example 2, by means of a circuit as shown in fig. 7. Among them, as an optimized design, in the embodiment of the present invention, REG8 is used as a part of the selection unit and the processing unit as described in embodiment 2 respectively under different situations, thereby saving at least one register, and increasing the processing speed of the processing device while reducing the loss, and it is noted that such equivalents or modifications to the embodiment of the present invention should be considered to be within the protection scope of the present invention.

Considering the double speed transmission requirement of DDR, dq7 or dq1 and dq2, and dq8 or dq3 and dq4 can be further combined together and output as a single data signal dq9, specifically, as shown in fig. 7, the combination of dq7 and dq8 can be realized by a selector MUX5, where the high level input of MUX5 can be the data output of REG8, the low level input of MUX5 can be the data output of REG9, and the control input can be clk3, so that when clk3 is high level, MUX5 or processing device can output dq7, and when clk3 is low level, MUX5 or processing device can output dq8, which satisfies the requirement of DDR for data transmission, and gives a feasible hardware implementation of the processing unit as described in embodiment 2, and this invention is not described in detail herein.

Further, in the embodiment of the present invention, the processing apparatus shown in fig. 7 may be used as a part of a physical PHY module of a memory controller, and since the processing apparatus has a simple structure and a small delay, the processing speed of the memory controller using the PHY module of the processing apparatus is significantly increased compared to the existing memory controller or a memory controller implemented by software logic and having the same function. Specifically, clk1 may be a system clock of a memory controller, clk3 may be a memory clock, dq1 to dq4 may be four-way data for transmission, and dq9 may be memory write data transmitted to a memory, where the write data is formed by combining data contents of dq1 to dq4, and a data transmission rate of the data is four times a frequency of the system clock.

It should be noted that the foregoing embodiments are only used for understanding the technical solution of the present invention, and should not be construed as constituting any unnecessary limitation to the present invention, for example, in the processing apparatus shown in fig. 7, more registers may be added on the transmission path to achieve the purpose of performing one-beat or multi-beat registration on the data signal, and similar embodiments do not affect the implementation of the technical solution of the present invention and the implementation of the technical effect thereof, and the present invention is not limited thereto. It should be understood that similar extensions and extensions of the present invention are contemplated as falling within the scope of the present invention.

From the above description, it can be seen that the present invention achieves the following technical effects:

1) the method selects a mode between the acquisition of a fifth data signal and a sixth data signal corresponding to the second clock signal by using the rising edge or the falling edge of the third clock signal according to the phase difference between the second clock signal and the third clock signal to obtain a ninth data signal which corresponds to the third clock signal, is transmitted at a double rate relative to the third clock signal and meets the requirement of a timing margin on a transmission path of clock domain crossing transmission, thereby realizing the control of the timing margin of the data signal on the transmission path of the clock domain crossing transmission;

2) through reasonable arrangement of the first preset interval and the second preset interval, the design requirement for clock domain crossing transmission of the data signals can be met, and the clock domain crossing transmission reliability of the data signals is improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for processing a data signal, comprising:

acquiring a fifth data signal and a sixth data signal according to a first data signal, a second data signal, a third data signal and a fourth data signal, wherein the first data signal, the second data signal, the third data signal and the fourth data signal correspond to a first clock signal, the fifth data signal and the sixth data signal correspond to a second clock signal, the second clock signal is a double-frequency clock signal of the first clock signal, and a rising edge of the first clock signal is aligned with a rising edge of the second clock signal, wherein when the first clock signal is 1, the fifth data signal corresponds to the first data signal, the sixth data signal corresponds to the third data signal, and when the first clock signal is 0, the fifth data signal corresponds to the second data signal, the sixth data signal corresponds to the fourth data signal;

acquiring a third clock signal, acquiring a fifth data signal and a sixth data signal by using a rising edge of the third clock signal when a phase difference of the second clock signal relative to the third clock signal is in a first preset interval, and acquiring the fifth data signal and the sixth data signal by using a falling edge of the third clock signal when the phase difference is in a second preset interval, wherein a clock period of the third clock signal is the same as a clock period of the second clock signal;

obtaining a ninth data signal according to a seventh data signal obtained by collecting the fifth data signal and an eighth data signal obtained by collecting the sixth data signal, wherein the ninth data signal corresponds to the seventh data signal when the third clock signal is 1, and the ninth data signal corresponds to the eighth data signal when the third clock signal is 0,

the first preset interval is (T/2, T), the second preset interval is (0, T/2), and T represents a clock period of the second clock signal.

2. The processing method of claim 1, wherein said deriving a fifth data signal and a sixth data signal from the first data signal, the second data signal, the third data signal, and the fourth data signal comprises:

acquiring the first data signal and the third data signal using a falling edge of the first clock signal, and acquiring the second data signal and the fourth data signal using a rising edge of the first clock signal; or, the first data signal and the third data signal are acquired by using a rising edge of the first clock signal, and the second data signal and the fourth data signal are acquired by using a falling edge of the first clock signal;

and when the first clock signal is 1, using a data signal obtained by collecting the first data signal as the fifth data signal, using a data signal obtained by collecting the third data signal as the sixth data signal, when the first clock signal is 0, using a data signal obtained by collecting the second data signal as the fifth data signal, and using a data signal obtained by collecting the fourth data signal as the sixth data signal.

3. The processing method of claim 1, wherein obtaining a ninth data signal from a seventh data signal obtained by acquiring the fifth data signal and an eighth data signal obtained by acquiring the sixth data signal comprises:

the following operations are performed N times: acquiring the data signal acquired in the previous operation of the N times of operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired in the previous operation of the N times of operations is the seventh data signal, and N is greater than or equal to 1; and/or performing the following operations M times: acquiring the data signal acquired by the previous operation in the M operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired by the previous operation in the M operations is the eighth data signal, and M is greater than or equal to 1;

and when the third clock signal is 1, taking the seventh data signal or the data signal acquired after the N operations as the ninth data signal, and when the first clock signal is 0, taking the eighth data signal or the data signal acquired after the M operations as the ninth data signal.

4. The processing method according to claim 3,

if the phase difference is within the first preset interval, the N operations include: reacquiring the seventh data signal using a falling edge of the third clock signal, the M operations comprising: reacquiring the eighth data signal using a rising edge of the third clock signal; if the phase difference is within the second preset interval, the M operations include: reacquiring the eighth data signal using a rising edge of the third clock signal; or,

if the phase difference is within the first preset interval, the M operations include: reacquiring the eighth data signal using a falling edge of the third clock signal; if the phase difference is within the second preset interval, the N operations include: reacquiring the seventh data signal using a rising edge of the third clock signal, the M operations comprising: and using the falling edge of the third clock signal to perform collection again on the eighth data signal.

5. The method according to any one of claims 1 to 4, wherein the first clock signal is a system clock of a memory controller, the second clock signal is a double-frequency clock of the system clock, the third clock signal is a write data clock of the memory controller, the first data signal, the second data signal, the third data signal and the fourth data signal are data to be transmitted by the memory controller, and the ninth data signal is write data transmitted to a memory chip by the memory controller, wherein the write data clock has the same clock cycle as the memory clock of the memory chip, and the write data clock and the memory clock meet a predetermined timing requirement.

6. The method of claim 5, wherein the predetermined timing requirement is that the write data generated according to the write data clock is advanced by K clock cycles relative to the memory clock when arriving at the memory chip, where K is any value between 0 and 1, and wherein before the obtaining the third clock signal, the method further comprises:

repeatedly executing the following operations for P times before meeting the execution termination condition corresponding to the preset time sequence requirement: adjusting the write data clock or a fourth clock signal lagging K clock cycles relative to the write data clock forward or backward, and transmitting a tenth data signal corresponding to the adjusted write data clock or the adjusted fourth clock signal to the memory chip; receiving an eleventh data signal returned by the memory chip according to the tenth data signal, and judging whether the execution termination condition is met according to the received eleventh data signal; wherein P is greater than or equal to 1.

7. The method according to claim 6, wherein the tenth data signal is a pulse signal aligned with a rising edge or a falling edge of the fourth clock signal, and the eleventh data signal is a data signal obtained by the memory chip acquiring the memory clock using the pulse signal, wherein if the tenth data signal is aligned with a rising edge of the fourth clock signal, the condition for terminating execution is: the received eleventh data signal is changed from 0 to 1;

if the falling edges of the tenth data signal and the fourth clock signal are aligned, the termination condition is: the received eleventh data signal is changed from 1 to 0.

8. The method of claim 6,

before performing the P operations, the method further comprises: taking a clock signal aligned with the system clock as an initial value of the write data clock or the fourth clock signal;

while performing the P operations, the adjusting the write data clock and/or the fourth clock signal forward or backward comprises: delaying the write data clock or the fourth clock signal by 1/L clock cycles as the adjusted write data clock or the fourth clock signal, L being a positive integer;

after performing the P operations, the method further comprises: if the clock signal aligned with the system clock is used as the write data clock, the phase difference is obtained according to the following formula: Δ ═ (P/L) × T; if the clock signal aligned with the system clock is taken as the fourth clock signal, the phase difference is obtained according to the following formula: Δ ═ (P/L-K) × T; where Δ represents the phase difference and T represents the clock period.

9. An apparatus for processing a data signal, comprising:

an obtaining unit, configured to obtain a fifth data signal and a sixth data signal according to a first data signal, a second data signal, a third data signal and a fourth data signal, where the first data signal, the second data signal, the third data signal and the fourth data signal correspond to a first clock signal, the fifth data signal and the sixth data signal correspond to a second clock signal, the second clock signal is a double-frequency clock signal of the first clock signal, and a rising edge of the first clock signal is aligned with a rising edge of the second clock signal, where the fifth data signal corresponds to the first data signal when the first clock signal is 1, the sixth data signal corresponds to the third data signal, and the fifth data signal corresponds to the second data signal when the first clock signal is 0, the sixth data signal corresponds to the fourth data signal;

the selection unit is used for acquiring a third clock signal, acquiring a fifth data signal and a sixth data signal by using a rising edge of the third clock signal when a phase difference of the second clock signal relative to the third clock signal is in a first preset interval, and acquiring the fifth data signal and the sixth data signal by using a falling edge of the third clock signal when the phase difference is in a second preset interval, wherein a clock cycle of the third clock signal is the same as a clock cycle of the second clock signal;

a processing unit, configured to obtain a ninth data signal according to a seventh data signal obtained by collecting the fifth data signal and an eighth data signal obtained by collecting the sixth data signal, where the ninth data signal corresponds to the seventh data signal when the third clock signal is 1, and the ninth data signal corresponds to the eighth data signal when the third clock signal is 0,

10. The processing apparatus according to claim 9, wherein the acquisition unit includes:

a first acquisition module, configured to acquire the first data signal and the third data signal using a falling edge of the first clock signal, and acquire the second data signal and the fourth data signal using a rising edge of the first clock signal; or, the first data signal and the third data signal are acquired by using a rising edge of the first clock signal, and the second data signal and the fourth data signal are acquired by using a falling edge of the first clock signal;

the first processing module is configured to, when the first clock signal is 1, use a data signal obtained by acquiring the first data signal as the fifth data signal, use a data signal obtained by acquiring the third data signal as the sixth data signal, when the first clock signal is 0, use a data signal obtained by acquiring the second data signal as the fifth data signal, and use a data signal obtained by acquiring the fourth data signal as the sixth data signal.

11. The processing apparatus according to claim 9, wherein the processing unit comprises:

a second acquisition module for performing the following operations N times: acquiring the data signal acquired in the previous operation of the N times of operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired in the previous operation of the N times of operations is the seventh data signal, and N is greater than or equal to 1; and/or performing the following operations M times: acquiring the data signal acquired by the previous operation in the M operations again by using the rising edge or the falling edge of the third clock signal, wherein the initial value of the data signal acquired by the previous operation in the M operations is the eighth data signal, and M is greater than or equal to 1;

and the second processing module is configured to use the seventh data signal or the data signal acquired after the N operations as the ninth data signal when the third clock signal is 1, and use the eighth data signal or the data signal acquired after the M operations as the ninth data signal when the first clock signal is 0.

12. The processing apparatus according to claim 11,

if the phase difference is within the first preset interval, the N operations include: reacquiring the seventh data signal using a falling edge of the third clock signal, the M operations comprising: reacquiring the eighth data signal using a rising edge of the third clock signal; if the phase difference is within the second preset interval, the M operations include: reacquiring the eighth data signal using a rising edge of the third clock signal; or, if the phase difference is located in the first preset interval, the M operations include: reacquiring the eighth data signal using a falling edge of the third clock signal; if the phase difference is within the second preset interval, the N operations include: reacquiring the seventh data signal using a rising edge of the third clock signal, the M operations comprising: and using the falling edge of the third clock signal to perform collection again on the eighth data signal.

13. The apparatus of any of claims 9-12, wherein the first clock signal is internal

The second clock signal is a double-frequency clock of the system clock, the third clock signal is a write data clock of the memory controller, the first data signal, the second data signal, the third data signal and the fourth data signal are data to be transmitted of the memory controller, and the ninth data signal is write data transmitted to a memory chip by the memory controller, wherein the write data clock has the same clock cycle as the memory clock of the memory chip, and the write data clock and the memory clock meet a preset timing requirement.

14. The apparatus of claim 13, wherein the predetermined timing requirement is that the write data generated according to the write data clock is advanced by K clock cycles relative to the memory clock when arriving at the memory chip, where K is any value between 0 and 1, and wherein before the obtaining of the third clock signal, the apparatus further comprises:

an adjusting unit, configured to repeatedly execute P times of the following operations before a termination execution condition corresponding to the preset timing requirement is met: adjusting the write data clock or a fourth clock signal lagging K clock cycles relative to the write data clock forward or backward, and transmitting a tenth data signal corresponding to the adjusted write data clock or the adjusted fourth clock signal to the memory chip; receiving an eleventh data signal returned by the memory chip according to the tenth data signal, and judging whether the execution termination condition is met according to the received eleventh data signal; wherein P is greater than or equal to 1.

15. The apparatus of claim 14, wherein the tenth data signal is a pulse signal aligned with a rising edge or a falling edge of the fourth clock signal, and the eleventh data signal is a data signal obtained by the memory chip acquiring the memory clock using the pulse signal, wherein if the tenth data signal is aligned with a rising edge of the fourth clock signal, the condition for terminating execution is: the received eleventh data signal is changed from 0 to 1;

16. The apparatus of claim 14,

the device further comprises: an initialization unit configured to use a clock signal aligned with the system clock as an initial value of the write data clock or the fourth clock signal;

the adjusting unit includes: a delay module, configured to delay the write data clock or the fourth clock signal by 1/L clock cycle, where L is a positive integer, and the write data clock or the fourth clock signal is used as the adjusted write data clock or the adjusted fourth clock signal;

the device further comprises: a calculating module, configured to obtain the phase difference according to the following formula when a clock signal aligned with the system clock is used as the write data clock: Δ ═ (P/L) × T; when a clock signal aligned with the system clock is taken as the fourth clock signal, the phase difference is obtained according to the following equation: Δ ═ (P/L-K) × T; where Δ represents the phase difference and T represents the clock period.