CN109871611A - A kind of matched method of asynchronous circuit automatically delaying - Google Patents
A kind of matched method of asynchronous circuit automatically delaying Download PDFInfo
- Publication number
- CN109871611A CN109871611A CN201910120574.5A CN201910120574A CN109871611A CN 109871611 A CN109871611 A CN 109871611A CN 201910120574 A CN201910120574 A CN 201910120574A CN 109871611 A CN109871611 A CN 109871611A
- Authority
- CN
- China
- Prior art keywords
- asynchronous circuit
- delay
- clock
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention can be implemented as the binding data asynchronous circuit based on Click unit and carry out automatic delay matching, allow it to work normally.The asynchronous circuit of binding data needs to carry out delay matching so that circuit can work normally, but designer can not directly complete this work using mature business eda tool.In order to solve this problem, the present invention provides the method that one kind can be captured all timing paths based on Synopsys Design Compiler (DC) tool and carry out delay matching to the binding data asynchronous circuit based on Click unit automatically.The present invention automatically can carry out delay matching so that asynchronous circuit can work normally for binding data asynchronous circuit, substantially reduce Asynchronous circuit design difficulty.
Description
Technical field
The invention belongs to IC design technical field, in particular to a kind of matched side of asynchronous circuit automatically delaying
Method.
Background technique
With the continuous promotion of integrated circuit fabrication process, asynchronous circuit has low-power consumption compared with synchronous circuit, at high speed
And the advantages that without clock distribution problem.However, asynchronous circuit is since type is more, and different types of asynchronous circuit is designing
Variant in method, mature eda tool only supports synchronous circuit to design in addition, these all bring to Asynchronous circuit design
It is difficult.Binding data asynchronous circuit based on Click unit is the most similar to synchronous circuit, therefore can be by mature EDA
Tool is designed.Binding data Asynchronous circuit design, which carries out delay matching, could make circuit meet temporal constraint, allow
Circuit can work normally.Due to not having clock, DC tool can not capture the timing path in binding data asynchronous circuit,
This brings difficulty to delay matching.
Summary of the invention
In order to overcome the disadvantages of the above prior art, reduce the difficulty of Asynchronous circuit design, it is an object of the invention to mention
For a kind of matched method of asynchronous circuit automatically delaying, the binding data based on the Click unit closest with synchronous circuit
Asynchronous circuit structure can be designed by mature eda tool, can be realized the automatically delaying matching of asynchronous circuit.
To achieve the goals above, the technical solution adopted by the present invention is that:
A kind of matched method of asynchronous circuit automatically delaying, using Verilog code to the binding number based on Click unit
Hardware description is carried out according to asynchronous circuit, is then integrated using DC tool, in comprehensive process, in asynchronous circuit control unit
Between insertion delay chain so that asynchronous circuit can satisfy timing requirements, which is characterized in that created in comprehensive Tcl script
Clock to capture timing path all in circuit automatically, then passes through the progress automatically delaying matching of Tcl script.
The Click unit is all represented using the Handshake Protocol of two phase place, the i.e. overturning each time of request signal
Primary request, request requests Click unit that can generate a fire pulse signal, the fire pulse signal each time
It can be considered as clock, for carrying out capturing and storaging data, in the binding data asynchronous circuit based on Click unit, i_r1
As input request signal, a pulse signal fire1 can all be generated each time by overturning, and it overturns can pass each time
Defeated to arrive i_r2, as the request signal of the second level, the overturning each time of i_r2 can all generate pulse signal a fire2, fire1
Signal and fire2 signal serve as clock, capture and storage to data.
The side for carrying out hardware description to the binding data asynchronous circuit based on Click unit using Verilog code
Formula is to carry out example to Click unit, and fire signal caused by Click unit is treated as clock.Others are to asynchronous circuit
Hardware description mode it is identical as synchronous circuit.
It is described carry out comprehensive to be completed by script using DC tool, it is indicated in comprehensive script comprising number order
How circuit should will be integrated.
The delay chain that is inserted between asynchronous circuit control unit is by the set_min_delay order in DC tool
Come what is realized.
The clock creation can according to Click unit generate fire signal and fire signal between relationship come into
Row, wherein the relationship between fire signal is embodied in above waveform.For example, fire1 and fire2 have 5ns delay, and its
Pulsewidth is 2, then the creation of clock, and one is { 02 }, the other is { 57 }, the digital representation rising edge of braces the inside front
Time, behind digital representation failing edge time.Even n pulse signal, also it is referred to this method and carries out clock
Creation.
When the Click unit is three, the mode that clock is created in comprehensive Tcl script is as follows:
create_clock–period 30-name fire1–waveform{0 2}[get_pins click1/fire]
create_clock–period 30-name fire2–waveform{5 7}[get_pins click2/fire]
create_clock–period 30-name fire3–waveform{10 12}[get_pins click3/
fire]
set_min_delay 5../..
set_min_delay 5../..
。
After obtaining delay path all in circuit, it is as follows that the matched method of automatically delaying is carried out by Tcl script:
At the beginning, it is assumed that circuit has n timing path, and n variable is created in Tcl, first assumes that all paths are prolonged
All be late it is identical, i.e., all variate-values are set to identical value as being delayed, are carried out with this identical is delayed
Then the creation of clock observes delay and the slack of each path to obtain all timing paths using order, then
The adjustment of n variable is carried out, and delay matching is carried out based on this, circuit is integrated again, then reexamines timing, until
Circuit meet demand.
The present invention by dexterously carrying out the creation of clock in comprehensive Tcl script, it is automatic capture it is all in circuit
Timing path；Automatic delay matching is carried out by Tcl script again.The difficulty for greatly reducing Asynchronous circuit design, realizes
The automatically delaying of binding data asynchronous circuit based on Click unit matches.
Compared with prior art, the present invention can be implemented as the progress of the binding data asynchronous circuit based on Click unit certainly
Dynamic delay matching allows it to work normally.The asynchronous circuit of binding data needs to carry out delay matching so that circuit
It can work normally, but designer can not directly complete this work using mature business eda tool.In order to solve this
Problem, the present invention, which provides one kind, to capture all timing paths simultaneously based on Synopsys Design Compiler (DC) tool
Automatically the method for delay matching being carried out to the binding data asynchronous circuit based on Click unit.The present invention can be automatically bundle
It ties up data asynchronous circuit and carries out delay matching so that asynchronous circuit can work normally, substantially reduce Asynchronous circuit design hardly possible
Degree.
Detailed description of the invention
Fig. 1 is Click element circuit schematic diagram used in the present invention.
Fig. 2 is Click unit waveform diagram used in the present invention.
Fig. 3 is the binding data asynchronous circuit used in the present invention based on Click unit.
Fig. 4 is the schematic diagram for the fire signal relation that Click unit used in the present invention generates.
It is method that asynchronous circuit carries out delay matching that Fig. 5 is used in the present invention automatically, and the th in figure indicates threshold value,
Its selection needs to consider the wire delay after placement-and-routing.
Specific embodiment
The embodiment that the present invention will be described in detail with reference to the accompanying drawings and examples.
The structure of Click unit is as shown in Figure 1, its waveform diagram is as shown in Figure 2.It is mono- to can be seen that Click from Fig. 1 and Fig. 2
Member all represents primary request using the Handshake Protocol of two phase place, the i.e. overturning each time of request signal.Each time
Request request Click unit can all generate a fire pulse signal.This fire pulse signal can actually be considered as
Clock, for carrying out capturing and storaging data.
Binding data asynchronous circuit can be designed using Click unit, the structure of circuit is as shown in figure 3, " binding data "
Refer to data-signal using Boolean type numerical value, request (request) and response (acknowledge) line be separated from each other and with number
According to bundling.
In the electronic circuit as shown in figure 3, for i_r1 as input request signal, a pulse letter can all be generated each time by overturning
Number fire1, and it overturns each time can be transferred to i_r2, the request signal as the second level.Circuit shown in Fig. 3
In, fire1 signal and fire2 signal have acted in effect as clock, to capture and storage to data.It can be from Fig. 3
Out, in order to enable the input data of its d type flip flop can be ready to when fire2 signal pulse generates, the request in two-stage is needed
It is inserted into delay chain between signal, and the delay of delay chain should be made greater than the delay of following combinational logic circuit.In this way
Operation be called delay matching.The timing path between two-stage fire signal must be obtained by carrying out delay matching, due to asynchronous electricity
Road does not have clock, so the timing path between two-stage fire can not be obtained.In order to solve this problem, it is proposed that a kind of side
Method, i.e., fire signal is treated as is clock, and is these fire signal creation clocks in the comprehensive script of Tcl, comprehensive in this way
Tool can capture the timing path between two-stage.Assuming that there are three Click control units in a circuit, and assume
Relationship between fire signal is as shown in Figure 4.
Then clock can be created in the following way in comprehensive Tcl script and carry out the insertion of delay chain.
create_clock–period 30-name fire1–waveform{0 2}[get_pins click1/fire]
create_clock–period 30-name fire2–waveform{5 7}[get_pins click2/fire]
create_clock–period 30-name fire3–waveform{10 12}[get_pins click3/
fire]
set_min_delay 5../..
set_min_delay 5../..
Create clock by mode above, DC tool will check between each rising edge clock created when
Sequence path, and check that circuit whether there is the fault of setup and hold.It thus can directly be obtained by ordering all
Timing path does not need to specify timing path by manually again.
Delay path all in circuit can be obtained by above method.Based on this method, the present invention is further
Propose a kind of matched method of progress automatically delaying.At the beginning, it is assumed that circuit has 3 Click control units, then circuit has
2 timing paths create 2 variables in Tcl.It is identical for first assuming all path delays all, that is, all
Variate-value is set to identical value, and the creation of clock is carried out with this identical delay, all this makes it possible to obtain
Timing path, then observe delay and the slack of each path using order, then carries out the adjustment of 2 variables, and is based on
This carries out delay matching, is integrated again to circuit, then reexamines timing, and until circuit meet demand, whole process is such as
Shown in Fig. 5.
By such method, it can be realized the inspection in all paths of circuit and carry out delay matching automatically for circuit, make
The design difficulty for obtaining the binding data asynchronous circuit based on Click unit substantially reduces.
Claims (8)
1. a kind of matched method of asynchronous circuit automatically delaying, using Verilog code to the binding data based on Click unit
Asynchronous circuit carry out hardware description, then integrated using DC tool, in comprehensive process, asynchronous circuit control unit it
Between insertion delay chain so that asynchronous circuit can satisfy timing requirements, which is characterized in that when being created in comprehensive Tcl script
Clock to capture timing path all in circuit automatically, then passes through the progress automatically delaying matching of Tcl script.
2. the matched method of asynchronous circuit automatically delaying according to claim 1, which is characterized in that the Click unit is adopted
It is the Handshake Protocol of two phase place, i.e. the overturning each time of request signal all represents primary request, each time request
Request Click unit can all generate a fire pulse signal, and the fire pulse signal can be considered as clock, for carrying out
Data are captured and storaged, in the binding data asynchronous circuit based on Click unit, i_r1 is each as input request signal
Secondary overturning can all generate a pulse signal fire1, and it overturns each time can be transferred to i_r2, as asking for the second level
Seek signal, the overturning each time of i_r2 can all generate pulse signal fire2, fire1 a signal and when fire2 signal serves as
Clock captures and storages data.
3. the matched method of asynchronous circuit automatically delaying according to claim 1, which is characterized in that described to use Verilog
The mode that code carries out hardware description to the binding data asynchronous circuit based on Click unit is to carry out example to Click unit,
Fire signal caused by Click unit is treated as into clock.Hardware description mode and synchronous circuit of the others to asynchronous circuit
It is identical.
4. the matched method of asynchronous circuit automatically delaying according to claim 1, which is characterized in that it is described using DC tool into
Comprehensive row is completed by script.
5. the matched method of asynchronous circuit automatically delaying according to claim 1, which is characterized in that described in asynchronous circuit control
Delay chain is inserted between unit processed to be realized by the set_min_delay order in DC tool.
6. the matched method of asynchronous circuit automatically delaying according to claim 1, which is characterized in that produced according to Click unit
Relationship between raw fire signal and fire signal carries out the creation of clock, and wherein the relationship between fire signal is embodied in
On waveform.
7. the matched method of asynchronous circuit automatically delaying according to claim 6, which is characterized in that when the Click unit
It is three, fire1 and fire2 have 5ns delay, and fire2 and fire3 have 5ns delay, and its pulsewidth is 2, then comprehensive
The mode that clock is created in Tcl script is as follows:
create_clock–period 30-name fire1–waveform{0 2}[get_pins click1/fire]
create_clock–period 30-name fire2–waveform{5 7}[get_pins click2/fire]
create_clock–period 30-name fire3–waveform{10 12}[get_pins click3/fire]
set_min_delay 5../..
set_min_delay 5../..
Wherein, inside braces the digital representation rising edge of front time, behind digital representation failing edge time.
8. the matched method of asynchronous circuit automatically delaying according to claim 1, which is characterized in that own in obtaining circuit
Delay path after, by Tcl script carry out the matched method of automatically delaying it is as follows:
At the beginning, it is assumed that circuit has n timing path, and n variable is created in Tcl, first assumes all path delays all
Be it is identical, i.e., all variate-values are set to identical value as delay, clock are carried out with this identical delay
Creation then observe delay and the slack of each path using order, then carry out n to obtain all timing paths
The adjustment of a variable, and delay matching is carried out based on this, circuit is integrated again, timing is then reexamined, until circuit
Meet demand.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910120574.5A CN109871611B (en) | 2019-02-18 | 2019-02-18 | Method for automatic delay matching of asynchronous circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910120574.5A CN109871611B (en) | 2019-02-18 | 2019-02-18 | Method for automatic delay matching of asynchronous circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109871611A true CN109871611A (en) | 2019-06-11 |
| CN109871611B CN109871611B (en) | 2021-06-08 |
Family
ID=66918827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910120574.5A Active CN109871611B (en) | 2019-02-18 | 2019-02-18 | Method for automatic delay matching of asynchronous circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109871611B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023279341A1 (en) * | 2021-07-08 | 2023-01-12 | 华为技术有限公司 | Method for designing asynchronous circuit, and electronic device |
| CN116384309A (en) * | 2023-05-31 | 2023-07-04 | 华中科技大学 | Four-phase latching asynchronous handshake unit applied to low-power chip design |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239622B1 (en) * | 1999-05-05 | 2001-05-29 | Sun Microsystems, Inc. | Self-timed domino circuit |
| CN101303643A (en) * | 2008-06-06 | 2008-11-12 | 清华大学 | Arithmetic logic unit using asynchronous circuit to implement |
| CN101776936A (en) * | 2009-12-21 | 2010-07-14 | 西安电子科技大学 | Global asynchronous local synchronous (GALS) asynchronous encapsulated circuit based on standard unit |
| CN101809869A (en) * | 2007-09-24 | 2010-08-18 | 高通股份有限公司 | Delay circuits matching delays of synchronous circuits |
| CN105046014A (en) * | 2015-08-06 | 2015-11-11 | 电子科技大学 | AMS based asynchronous sequential circuit design method |
-
2019
- 2019-02-18 CN CN201910120574.5A patent/CN109871611B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239622B1 (en) * | 1999-05-05 | 2001-05-29 | Sun Microsystems, Inc. | Self-timed domino circuit |
| CN101809869A (en) * | 2007-09-24 | 2010-08-18 | 高通股份有限公司 | Delay circuits matching delays of synchronous circuits |
| CN101303643A (en) * | 2008-06-06 | 2008-11-12 | 清华大学 | Arithmetic logic unit using asynchronous circuit to implement |
| CN101776936A (en) * | 2009-12-21 | 2010-07-14 | 西安电子科技大学 | Global asynchronous local synchronous (GALS) asynchronous encapsulated circuit based on standard unit |
| CN105046014A (en) * | 2015-08-06 | 2015-11-11 | 电子科技大学 | AMS based asynchronous sequential circuit design method |
Non-Patent Citations (3)
| Title |
|---|
| WEIJIA CHEN，ET AL: "An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture", 《IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE》 * |
| 何安平等: "基于约束数据捆绑两相握手协议的8位异步Booth乘法器设计", 《电子学报》 * |
| 王友瑞等: "基于同步EDA工具的异步电路设计流程", 《基于同步EDA工具的异步电路设计流程》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023279341A1 (en) * | 2021-07-08 | 2023-01-12 | 华为技术有限公司 | Method for designing asynchronous circuit, and electronic device |
| CN116384309A (en) * | 2023-05-31 | 2023-07-04 | 华中科技大学 | Four-phase latching asynchronous handshake unit applied to low-power chip design |
| CN116384309B (en) * | 2023-05-31 | 2023-08-11 | 华中科技大学 | Four-phase latching asynchronous handshake circuit applied to low-power chip design |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109871611B (en) | 2021-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9830418B2 (en) | Clock-tree transformation in high-speed ASIC implementation | |
| Muttersbach et al. | Practical design of globally-asynchronous locally-synchronous systems | |
| US7827454B2 (en) | Semiconductor device | |
| CN102375472B (en) | Clock trees for pulse latches | |
| US20190313938A1 (en) | Circuit for meeting setup and hold times of a control signal with respect to a clock | |
| CN109871611A (en) | A kind of matched method of asynchronous circuit automatically delaying | |
| CN104795091B (en) | System and method for realizing ZBT (zero bus turnaround) reading and writing timing sequence stability in FPGA (field programmable gate array) | |
| CN109815619A (en) | A method of asynchronous circuit is converted by synchronous circuit | |
| US6518788B2 (en) | Logic circuit design method and logic circuit | |
| US7545896B2 (en) | Asynchronous multi-clock system | |
| Elboim et al. | A clock-tuning circuit for system-on-chip | |
| Takizawa et al. | A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs | |
| CN104639124A (en) | Method and circuit for improving margin for setup time and hold time of input signal of time sequence device | |
| Sharif et al. | Quantitative analysis of state-of-the-art synchronizers: Clock domain crossing perspective | |
| WO2003038687A2 (en) | Optimization of the design of a synchronous digital circuit | |
| US20080069277A1 (en) | Method and apparatus for modeling signal delays in a metastability protection circuit | |
| US10312886B2 (en) | Asynchronous clock gating circuit | |
| US7080335B2 (en) | Methods for modeling latch transparency | |
| US6262612B1 (en) | Using storage elements with multiple delay values to reduce supply current spikes in digital circuits | |
| CN118297013B (en) | Simulation test auxiliary circuit, simulation design unit and simulation test circuit | |
| Yoshimi et al. | A delay adjustment method for asynchronous circuits with bundled-data implementation considering a latency constraint | |
| Santhanam et al. | Generic methodolgy and solution for Additive Jitter correction in Mesh based clock architectures | |
| JP5942417B2 (en) | Simulation device, simulation method, and simulation program | |
| EP1308862A1 (en) | Optimization of the design of a synchronous digital circuit | |
| JP2000353939A (en) | Clock signal synchronous flip flop circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |