WO2023279341A1

WO2023279341A1 - Method for designing asynchronous circuit, and electronic device

Info

Publication number: WO2023279341A1
Application number: PCT/CN2021/105326
Authority: WO
Inventors: 李智宇; 虞志益; 肖山林; 唐样洋; 黄宇皓; 乔冰涛
Original assignee: 华为技术有限公司
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2023-01-12
Also published as: CN117651933A

Abstract

A method for designing an asynchronous circuit. The method comprises: respectively determining, as a plurality of clock signals, a plurality of pulse signals that are generated by a plurality of asynchronous controllers in an asynchronous circuit, wherein the plurality of clock signals are derived from the same initial clock signal, and there is only phase shift between the clock signals. The method further comprises: determining the propagation time difference between any two of the plurality of clock signals, and calculating a data transmission time period between corresponding sequential logic devices. The method further comprises: comparing the propagation time difference with the data transmission time period, so as to determine whether a data signal arrives at sequential logic gates ahead of the clock signals, and according to the comparison result, setting a corresponding delay between the two asynchronous controllers. By means of the above method, the timing of a combinational logic portion and a control portion of the asynchronous circuit may be simultaneously analyzed, such that relative timing constraints of the asynchronous circuit can be converted into static timing analysis that can be identified by a traditional EDA tool. On this basis, the EDA tool may be used to perform circuit optimization and implement timing constraints on the asynchronous circuit, so as to effectively improve the efficiency of designing an asynchronous single-rail circuit. Therefore, the method is applicable to large-scale asynchronous circuit design.

Description

Method and electronic device for designing asynchronous circuits

technical field

The present disclosure relates to the field of circuits, and more particularly relates to a design method of an asynchronous circuit and an electronic device.

Background technique

Various application scenarios such as Internet of Things (IoT) and neural network computing have high requirements on the power consumption of chips. Asynchronous circuits have the characteristics of low power consumption and strong robustness. Therefore, asynchronous circuit designs are suitable for use in chip designs for these applications.

However, the biggest obstacle encountered in the industrialization of asynchronous circuits is the lack of support from electronic design automation (EDA) tools. Traditional EDA tools analyze and optimize the timing of chips based on the global clock, while the relative timing of asynchronous circuits follows Constraints (relative timing constraints, RTC) are currently not well recognized by EDA tools. Asynchronous circuits can be divided into single-rail circuits and dual-rail circuits, where the data of the dual-rail circuit itself can represent its validity. Dual-rail circuits have lower timing requirements and are more robust, but have more than twice the area of corresponding synchronous circuits. The monorail circuit has a data path similar to that of a synchronous circuit, and its area is similar to that of a synchronous circuit. It is suitable for migrating to a synchronous EDA tool for design. The key to single-rail circuits is the delay matching of data and handshake protocols, which has higher timing requirements than dual-rail circuits. Due to the advantages of area, more existing chips choose single-rail circuits for asynchronous design.

The current mainstream approach is to convert the RTC of an asynchronous monorail circuit into a static timing analysis (STA) that can be recognized by EDA tools. On this basis, the researchers tried to separate the combinational logic part and the control part of the asynchronous circuit to make sure that the delay of the control part is greater than that of the corresponding combinational logic part. However, the method of separating constraints does not consider the integrity of asynchronous circuits, so it is difficult to use in large-scale integrated circuits.

Contents of the invention

In view of the above problems, embodiments of the present disclosure aim to provide a method and an electronic device for designing an asynchronous circuit.

According to a first aspect of the present disclosure, a method for designing an asynchronous circuit is provided. The method includes determining a first pulse signal generated by a first asynchronous controller in the asynchronous circuit as a first clock signal; and determining a second pulse signal generated by a second asynchronous controller in the asynchronous circuit as a second clock signal. A second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is offset by a first predetermined amount of time relative to the first clock signal. The method also includes generating a first clock propagation difference corresponding to the first clock signal and the second clock signal, and determining a first data propagation time period between the first sequential logic gate and the second sequential logic gate. The first sequential logic gate is coupled to the first asynchronous controller and operates based on the first pulse signal, and the second sequential logic gate is coupled to the second asynchronous controller and operates based on the second pulse signal. The method further includes generating a delay report related to the first data propagation time period and the first clock propagation difference. By representing the pulse signals of various asynchronous controllers used to control the operation of sequential logic devices as clock signals derived from the same source clock but with different phases and different transmission paths, conventional EDA design tools therefore treat them as synchronous clocks and calculate Timing paths for individual clock signals. In addition, conventional EDA tools can analyze the timing of data propagation in the combinational logic portion of an asynchronous circuit. On this basis, by comparing the propagation delay of the control part and the combinational logic part, the delay setting of the asynchronous circuit can be determined accordingly and the timing correctness of the asynchronous circuit can be ensured. Since the timing of the combinational logic part and the control part of the asynchronous circuit is uniformly analyzed through the above method, the relative timing constraints of the asynchronous circuit can be converted into a static timing analysis that can be recognized by traditional EDA tools. On this basis, EDA tools can be used to optimize the circuit and schedule constraints on the asynchronous circuit, so as to effectively improve the efficiency of designing the asynchronous single-rail circuit. Therefore, the method can be applied to large-scale asynchronous circuit design.

In a possible implementation manner, generating the first clock propagation difference corresponding to the first clock signal and the second clock signal includes: determining the first clock propagation time period of the first clock signal and the second clock propagation time period of the second clock signal Clock propagation time period, the first clock propagation time period represents the time period from the first asynchronous controller receiving the first input request to the first asynchronous controller generating the first pulse signal, the second clock propagation time period represents the period from the first asynchronous a time period from when the controller receives the first input request to when the second asynchronous controller generates the second pulse signal; and determining a first clock propagation difference between the first clock propagation time period and the second clock propagation time period.

In a possible implementation manner, generating a delay report related to the first data propagation time period and the first clock propagation difference includes: generating a first data propagation time value representing the first data propagation time period; subtracting the propagation time value and the first clock propagation difference value to determine a first delay value; and generating a delay report including the first delay value.

In a possible implementation manner, generating a delay report related to the first data propagation time period and the first clock propagation difference includes: generating a first data propagation time value representing the first data propagation time period; The propagation time value is compared to the first clock propagation difference value to generate a comparison result; and a delay report including the comparison result is generated.

In a possible implementation manner, the method further includes determining a delay setting between the first asynchronous controller and the second asynchronous controller based on the first clock propagation difference and the first data propagation time period.

In a possible implementation manner, based on the first clock propagation difference and the first data propagation time period, determining the delay setting between the first asynchronous controller and the second asynchronous controller includes responding to the first data propagation time period is greater than the first clock propagation difference, a delay circuit is set between the first asynchronous controller and the second asynchronous controller; or in response to the first data propagation time period being not greater than the first clock propagation difference, the There is no delay circuit between the controller and the second asynchronous controller. By setting a delay circuit between the asynchronous controllers, it can be ensured that the data signal arrives at the sequential logic device before the pulse signal to achieve the correct timing.

In a possible implementation manner, the circuit design of the combinational logic device between the sequential logic devices may be optimized, so as to ensure that the data signal reaches the lower sequential logic device before the pulse signal.

In a possible implementation manner, setting the delay circuit between the first asynchronous controller and the second asynchronous controller in response to the first data propagation time period being greater than the first clock propagation difference includes determining the first clock propagation difference and The first path difference between the first data propagation differences; determine the unit delay period of the delay circuit; based on the first path difference and the unit delay period, set one or more delay circuits in series, so that one or more The total delay period of the delay circuits connected in series is not lower than the first path difference. By arranging one or more unit delay circuits in series before the asynchronous controller, it can be ensured in a simple manner that the data signal arrives at the sequential logic device before the pulse signal to ensure the realized timing. In addition, it is also possible to add one unit delay circuit at a time, and then repeat the previous judgment process. When the timing requirement is not met, a unit delay circuit is added again, which is connected in series with the previously added unit delay circuit between the two asynchronous controllers, and the previous judging process is repeated until the timing requirement is met. In this way, the setting of the delay circuit can be done automatically by the processor without human intervention. Therefore, the design of an asynchronous circuit can be simplified.

In a possible implementation, the method further includes determining the Mth pulse signal generated by the Mth asynchronous controller of the asynchronous circuit as the Mth clock signal, where M represents an integer greater than 0; The Nth pulse signal generated by the controller is determined as the Nth clock signal, the first asynchronous controller to the Nth asynchronous controller are coupled step by step, and any two adjacent asynchronous controllers from the first asynchronous controller to the Nth asynchronous controller Offset from each other by a first predetermined amount of time, the output of the Nth asynchronous controller is coupled to the input of the Mth asynchronous controller, where N represents an integer greater than M; and a timing period P is determined, where P represents a time period between N and M difference; based on the timing cycle P, determine the delay setting between the Nth asynchronous controller and the Mth asynchronous controller. By using multiple cycles to analyze non-sequential asynchronous circuits, timing analysis can also be implemented for asynchronous circuits including non-sequential pipeline architectures, thereby extending the scope of application of the present disclosure.

In a possible implementation, based on the timing cycle P, determining the delay setting between the Nth asynchronous controller and the Mth asynchronous controller includes determining the Nth clock propagation time period of the Nth clock signal, the Nth clock propagation time The segment represents the time period from the first asynchronous controller receiving the first input request to the Nth asynchronous controller generating the Nth pulse signal; determine the time period of the Mth asynchronous controller in the Pth timing cycle after the Mth clock signal is generated Clock propagation period; determine the Nth clock propagation difference between the Nth clock propagation period and the clock propagation period in the Pth timing cycle; determine the Nth clock propagation difference between the Nth sequential logic gate and the Mth sequential logic gate During the N data transmission period, the Nth sequential logic gate is coupled to the Nth asynchronous controller and operates based on the Nth pulse signal, the Mth sequential logic gate is coupled to the Mth asynchronous controller and operates based on the Mth pulse signal; and based on The Nth clock propagation time period and the Nth data propagation time period determine the delay setting between the Nth asynchronous controller and the Mth asynchronous controller. By using multiple cycles to analyze non-sequential asynchronous circuits, timing analysis can also be implemented for asynchronous circuits including non-sequential pipeline architectures, thereby extending the scope of application of the present disclosure.

In one possible implementation, the method also includes maintaining the structure of the asynchronous circuit during synthesis of the asynchronous circuit. By maintaining the asynchronous circuit during synthesis, it is ensured that the structure of the asynchronous circuit is not optimized by the EDA tool. Because there is a loop in the asynchronous controller, if it is not maintained, the integrated circuit may be different from the expected one, which will affect the function of the asynchronous circuit.

In a possible implementation manner, determining the delay setting between the first asynchronous controller and the second asynchronous controller based on the first clock propagation difference and the first data propagation time period includes The first clock propagation difference and the first data propagation time period determine a delay setting between the first asynchronous controller and the second asynchronous controller. Affected by process voltage and temperature (process voltage and temperature, PVT), the same chip has different delays under different operating conditions, which is very important for the delay matching process of asynchronous circuits. Under propagation timing constraints, static timing analysis analyzes circuit functions for timing models at different process corners to ensure that the constrained circuits can meet timing requirements under any conditions.

In a possible implementation manner, the method further includes determining the first pulse width of the first pulse signal and the second pulse width of the second pulse signal; and responding to the first pulse width or the second pulse width being lower than the pulse width Threshold, the pulse stretching circuit is correspondingly set in the first asynchronous controller or the second asynchronous controller to widen the width of the first pulse signal or the second pulse signal. Propagation timing constraints treat the handshake process of asynchronous circuits as the clock propagation process, and there are combinational logic and registers on this path, so static timing analysis cannot obtain the pulse width of the actually generated local pulse single-shot (click) signal. After satisfying other timing constraints, the timing simulation of the asynchronous circuit after implementation can determine whether the click pulse width of each stage actually meets the minimum pulse width requirement of the register. If the width of the local pulse needs to be extended, a buffer unit can be added to the output pin of the register in the asynchronous controller to further ensure the timing correctness of the asynchronous circuit.

In a possible implementation manner, the asynchronous circuit includes a single-rail asynchronous circuit; the first asynchronous controller is an initial asynchronous controller; and both the first asynchronous controller and the second asynchronous controller include a phase decoupling controller.

In a possible implementation manner, the second asynchronous controller is further coupled to a fourth asynchronous controller in the asynchronous circuit. The method further includes determining the fourth pulse signal generated by the fourth asynchronous controller as the fourth clock signal; determining the second pulse signal generated by the second asynchronous controller in response to the request from the fourth asynchronous controller as the fifth clock signal , the fifth clock signal is offset by a second predetermined amount of time relative to the fourth clock signal; the second clock signal is assigned to the first clock group and the fifth clock signal is assigned to the second clock group, the second clock group being different from the first clock group A clock grouping; determine the fifth clock propagation time period of the fourth clock signal and the fifth clock propagation time period of the fifth clock signal, the fifth clock propagation time period represents receiving the fourth input request from the fourth asynchronous controller to the first The time period during which the four asynchronous controllers generate the fourth pulse signal, the fifth clock propagation time period represents the time period from the fourth asynchronous controller receiving the fourth input request to the second asynchronous controller generating the fifth pulse signal; determine the fourth A fourth clock propagation difference between the clock propagation time period and the fifth clock propagation time period; determine the fourth data propagation time period between the fourth sequential logic gate and the fifth sequential logic gate, the fourth sequential logic gate is coupled to a fourth asynchronous controller and operating based on a fourth pulse signal, a fifth sequential logic gate coupled to the second asynchronous controller and operating based on a fifth pulse signal; and based on a fourth clock propagation difference and a fourth data propagation time period , to determine a delay setting between the fourth asynchronous controller and the second asynchronous controller. In this implementation, multiple clocks are defined on the same port, and the clocks defined later will not overwrite the existing clocks, and the clocks that do not physically exist at the same time are grouped to interrupt the timing analysis between them. The circuit is then constrained by one-to-one correspondence of multiple clocks with different inputs, and the delay is calculated. In this way, correct timing analysis can also be implemented for conditionally selected asynchronous circuits including multiplexers and demultiplexers, and corresponding delay settings can be performed according to the timing analysis results, thereby expanding the application range of the present disclosure.

In a possible implementation manner, the first predetermined amount of time is less than a first proportion of the period of the pulse signal, for example less than one hundredth, one thousandth or one ten thousandth. By setting the predetermined amount of time to be much shorter than the period of the pulse signal, it is possible to prevent a plurality of pulse signals from interfering with each other.

According to a second aspect of the present disclosure, a computer readable storage medium is provided. The computer-readable storage medium stores a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method according to the first aspect.

According to a third aspect of the present disclosure, a computer program product is provided. The computer program product comprises a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method according to the first aspect.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising one or more processors; a memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform aspects of the method.

According to a fifth aspect of the present disclosure, there is provided an electronic device including a clock signal determining unit, a clock propagation difference generating unit, a data propagation time period determining unit, and a delay report generating unit. The clock signal determination unit is used to determine the first pulse signal generated by the first asynchronous controller in the asynchronous circuit as the first clock signal; determine the second pulse signal generated by the second asynchronous controller in the asynchronous circuit as the second clock signal, the second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is offset by a first predetermined amount of time relative to the first clock signal. The clock propagation difference generating unit is configured to generate a first clock propagation difference corresponding to the first clock signal and the second clock signal. The data propagation time period determining unit is used to determine a first data propagation time period between the first sequential logic device and the second sequential logic device, the first sequential logic device is coupled to the first asynchronous controller and operates based on the first pulse signal , the second sequential logic device is coupled to the second asynchronous controller and operates based on the second pulse signal. The delay report generating unit is configured to generate a delay report related to the first data propagation time period and the first clock propagation difference.

By representing the pulse signals of various asynchronous controllers used to control the operation of sequential logic devices as clock signals derived from the same source clock but with different phases and different transmission paths, conventional EDA design tools therefore treat them as synchronous clocks and calculate Timing paths for individual clock signals. In addition, conventional EDA tools can analyze the timing of data propagation in the combinational logic portion of an asynchronous circuit. On this basis, by comparing the propagation delay of the control part and the combinational logic part, the delay setting of the asynchronous circuit can be determined accordingly and the timing correctness of the asynchronous circuit can be ensured. Since the timing of the combinational logic part and the control part of the asynchronous circuit is uniformly analyzed through the above method, the relative timing constraints of the asynchronous circuit can be converted into a static timing analysis that can be recognized by traditional EDA tools. On this basis, EDA tools can be used for circuit optimization and timing constraints on asynchronous circuits to effectively improve the efficiency of designing asynchronous single-rail circuits. Therefore, the method can be applied to large-scale asynchronous circuit design.

In a possible implementation manner, the clock propagation difference generating unit includes: a clock propagation time period determining unit, configured to determine a first clock propagation time period of the first clock signal and a second clock propagation time period of the second clock signal , the first clock propagation time period represents the time period from the first asynchronous controller receiving the first input request to the first asynchronous controller generating the first pulse signal, and the second clock propagation time period represents the time period from the first asynchronous controller receiving The time period from the first input request to the second asynchronous controller generating the second pulse signal; and a clock propagation difference determination unit, configured to determine the first clock propagation between the first clock propagation time period and the second clock propagation time period difference.

In a possible implementation manner, the electronic device further includes a delay setting determination unit, configured to determine the delay between the first asynchronous controller and the second asynchronous controller based on the first clock propagation difference and the first data propagation time period. delay settings.

In a possible implementation manner, the delay setting determination unit is further configured to set a delay circuit between the first asynchronous controller and the second asynchronous controller in response to the first data propagation time period being greater than the first clock propagation difference; Or in response to the fact that the first data propagation time period is not greater than the first clock propagation difference, no delay circuit is provided between the first asynchronous controller and the second asynchronous controller. By setting a delay circuit between the asynchronous controllers, it can be ensured that the data signal arrives at the sequential logic device before the pulse signal to achieve the correct timing.

In a possible implementation manner, the clock signal determination unit is further configured to determine the Mth pulse signal generated by the Mth asynchronous controller of the asynchronous circuit as the Mth clock signal, where M represents an integer greater than 0; the asynchronous circuit The Nth pulse signal generated by the Nth asynchronous controller is determined as the Nth clock signal, the first asynchronous controller to the Nth asynchronous controller are coupled step by step, and any two of the first asynchronous controller to the Nth asynchronous controller Adjacent asynchronous controllers are offset from each other by a first predetermined amount of time, an output of an Nth asynchronous controller is coupled to an input of an Mth asynchronous controller, where N represents an integer greater than M. The electronic device further includes a timing period determining unit, configured to determine a timing period P, where P represents a difference between N and M. The delay setting determination unit is further configured to determine the delay setting between the Nth asynchronous controller and the Mth asynchronous controller based on the timing cycle P. By using multiple cycles to analyze non-sequential asynchronous circuits, timing analysis can also be implemented for asynchronous circuits including non-sequential pipeline architectures, thereby extending the scope of application of the present disclosure.

In a possible implementation manner, the electronic device further includes a maintaining unit, configured to maintain the structure of the asynchronous circuit during synthesis of the asynchronous circuit. By maintaining the asynchronous circuit during synthesis, it is ensured that the structure of the asynchronous circuit is not optimized by the EDA tool. Because there is a loop in the asynchronous controller, if it is not maintained, the integrated circuit may be different from the expected one, which will affect the function of the asynchronous circuit.

In a possible implementation manner, the delay setting determination unit is further configured to determine, based on the first clock propagation difference and the first data propagation time period of the asynchronous circuit at different process angles, to determine Delay settings between controllers. Affected by process voltage and temperature (process voltage and temperature, PVT), the same chip has different delays under different operating conditions, which is very important for the delay matching process of asynchronous circuits. Under propagation timing constraints, static timing analysis analyzes circuit functions for timing models at different process corners to ensure that the constrained circuits can meet timing requirements under any conditions.

In a possible implementation manner, the electronic device further includes a pulse stretching unit. The pulse stretching unit is used to determine the first pulse width of the first pulse signal and the second pulse width of the second pulse signal; and in response to the first pulse width or the second pulse width being lower than the pulse width threshold, in the first asynchronous controller Or a pulse stretching circuit is correspondingly set in the second asynchronous controller to widen the width of the first pulse signal or the second pulse signal. Propagation timing constraints regard the handshake process of asynchronous circuits as the clock propagation process, and there are combinational logic and registers on this path, so static timing analysis cannot obtain the pulse width of the actually generated local pulse click signal. After satisfying other timing constraints, the timing simulation of the asynchronous circuit after implementation can determine whether the pulse width of the click signal of each stage actually meets the minimum pulse width requirement of the register. If the width of the local pulse needs to be extended, a buffer unit can be added to the output pin of the register in the asynchronous controller to further ensure the timing correctness of the asynchronous circuit.

In a possible implementation manner, the second asynchronous controller is further coupled to the fourth asynchronous controller in the asynchronous circuit; the clock signal determining unit is further configured to determine the fourth pulse signal generated by the fourth asynchronous controller as the fourth a clock signal; determining a second pulse signal generated by the second asynchronous controller in response to a request from the fourth asynchronous controller as a fifth clock signal, the fifth clock signal being offset by a second predetermined amount of time relative to the fourth clock signal; electronically The device also includes a clock assigning unit for assigning the second clock signal to the first clock group and assigning the fifth clock signal to the second clock group, the second clock group being different from the first clock group; the clock propagation period determining unit Further used to determine the fifth clock propagation time period of the fourth clock signal and the fifth clock propagation time period of the fifth clock signal, the fifth clock propagation time period indicates that the fourth input request is received from the fourth asynchronous controller to the fourth The time period when the asynchronous controller generates the fourth pulse signal, and the fifth clock propagation time period represents the time period from when the fourth asynchronous controller receives the fourth input request to when the second asynchronous controller generates the fifth pulse signal; the clock propagation difference The determining unit is further used to determine the fourth clock propagation difference between the fourth clock propagation time period and the fifth clock propagation time period; the data propagation time period is further used to determine the difference between the fourth sequential logic gate and the fifth sequential logic gate The fourth data propagation time period, the fourth sequential logic gate is coupled to the fourth asynchronous controller and operates based on the fourth pulse signal, and the fifth sequential logic gate is coupled to the second asynchronous controller and operates based on the fifth pulse signal; And the delay setting determining unit is further configured to determine a delay setting between the fourth asynchronous controller and the second asynchronous controller based on the fourth clock propagation difference and the fourth data propagation time period. In this implementation, multiple clocks are defined on the same port, and the clocks defined later will not overwrite the existing clocks, and the clocks that do not physically exist at the same time are grouped to interrupt the timing analysis between them. The circuit is then constrained by one-to-one correspondence of multiple clocks with different inputs, and the delay is calculated. In this way, correct timing analysis can also be implemented for conditionally selected asynchronous circuits including multiplexers and demultiplexers, and corresponding delay settings can be performed according to the timing analysis results, thereby expanding the application range of the present disclosure.

It should be understood that what is described in the Summary of the Invention is not intended to limit the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, identical or similar reference numerals denote identical or similar elements, wherein:

FIG. 1 shows a schematic block diagram of a circuit system according to some embodiments of the present disclosure;

2 shows a schematic circuit diagram of an asynchronous circuit of a pipeline architecture according to some embodiments of the present disclosure;

Figure 3 shows a schematic circuit diagram of an asynchronous controller according to some embodiments of the present disclosure;

Fig. 4 shows a schematic circuit diagram of an asynchronous controller according to other embodiments of the present disclosure;

Fig. 5 shows a schematic diagram of a clock signal propagation path according to some embodiments of the present disclosure;

Fig. 6 shows a schematic block diagram of clock signal propagation of a sequential circuit according to some embodiments of the present disclosure;

Fig. 7 shows a schematic block diagram of clock signal propagation of a non-sequential circuit according to some embodiments of the present disclosure;

Fig. 8 shows a schematic block diagram of clock signal propagation of a condition selection circuit according to some embodiments of the present disclosure;

Fig. 9 shows a schematic circuit diagram of an asynchronous controller according to other embodiments of the present disclosure;

Fig. 10 shows a schematic circuit diagram of an asynchronous controller according to other embodiments of the present disclosure;

FIG. 11 shows a schematic flowchart of a method according to some embodiments of the present disclosure;

Figure 12 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure; and

Figure 13 shows a block diagram of an example device that may be used to implement some embodiments of the present disclosure.

detailed description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below. It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

As mentioned above, in the process of designing an asynchronous circuit, conventional schemes separate and constrain the combinational logic part and the control part of the asynchronous circuit, so as to ensure that the delay of the control part is greater than that of the corresponding combinational logic part. However, such separation constraints do not consider the integrity of asynchronous circuits, and often require multiple manual iterations to meet the timing, which is difficult to use in large-scale integrated circuits.

In some embodiments of the present disclosure, by representing the pulse signals of each asynchronous controller used to control the operation of sequential logic devices as clock signals originating from the same source clock but having different phases and different transmission paths, conventional EDA design tools So treat it as a synchronous clock and calculate the timing paths of the individual clock signals. In addition, conventional EDA tools can analyze the timing of data propagation in the combinational logic portion of an asynchronous circuit. On this basis, by comparing the propagation delay of the control part and the combinational logic part, the delay setting of the asynchronous circuit can be determined accordingly and the timing correctness of the asynchronous circuit can be ensured. In the embodiment of the present disclosure, since the timing of the combinational logic part and the control part of the asynchronous circuit is uniformly analyzed in the above-mentioned manner, the relative timing constraints of the asynchronous circuit can be converted into a static timing analysis that can be recognized by traditional EDA tools . On this basis, EDA tools can be used for circuit optimization and timing constraints on asynchronous circuits to effectively improve the efficiency of designing asynchronous single-rail circuits. Therefore, embodiments of the present disclosure may be applicable to large-scale asynchronous circuit designs.

FIG. 1 shows a schematic block diagram of a circuit system 100 according to some embodiments of the present disclosure. The circuit system 100 includes a first device 10 , an asynchronous circuit 20 and a second device 30 . The first device 10 is, for example, a source device, and the second device 30 is, for example, a sink device. In one embodiment, circuitry 100 may be integrated into a single chip. Alternatively, the first device 10, the asynchronous circuit 20 and the second device 30 may be implemented in different chips or devices. This disclosure is not limited in this regard. In the case of unidirectional transmission (eg, the circuit system 100 is a pipeline system), the first device 10 sends a data signal to the asynchronous circuit 20 . The asynchronous circuit 20 sends the processed data to the second device 30 for use or further processing by the second device 30 . In order to realize asynchronous processing, the first device 10 also sends a request signal to the asynchronous circuit 20 in addition to sending the data signal, and the asynchronous circuit 20 processes the data signal after receiving the request and simultaneously sends an acknowledgment signal to the first device 10 to determine A data signal is received. In order to ensure that the data can be processed correctly, the data signal usually arrives at the asynchronous circuit 20 earlier than the request signal. Similarly, the asynchronous circuit 20 also sends a request signal to the second device 30 in addition to sending the data signal, and the second device 30 processes or uses the data signal after receiving the request and simultaneously sends an acknowledgment signal to the asynchronous circuit 20 to determine A data signal is received. In order to ensure that the data can be processed correctly, the data signal usually arrives at the second device 30 earlier than the request signal. It can be understood that in some embodiments, data can be transmitted bidirectionally in the circuit system 100, that is, depending on the direction of data transmission, the first device 10 can be a sink device or a source device, and the second device 30 can be a source device or a sink device.

FIG. 2 shows a schematic circuit diagram of an asynchronous circuit 200 of a pipeline architecture according to some embodiments of the present disclosure. In an embodiment, the asynchronous circuit 200 may be a specific implementation of the asynchronous circuit 20 in FIG. 1 . It can be understood that the asynchronous circuit of the present disclosure is not limited to the asynchronous circuit 200, but may have other implementation forms. Asynchronous circuit 200 includes a data path and a timing path. The timing path includes a first asynchronous controller 24 , a second asynchronous controller 26 , and a third asynchronous controller 28 cascadedly coupled to each other. The data path includes a first sequential logic device 21 , a first functional circuit 23 , a second sequential logic device 25 , a second functional circuit 27 and a third sequential logic device 29 . It can be understood that the data path may include more or less sequential logic devices and functional circuits, which is not limited in the present disclosure. In one embodiment, functional circuits may be implemented by one or more combinational logic devices. As used herein, "sequential logic device" means a logic device with clocked inputs or pulsed control signals. The output of a sequential logic device at any time not only depends on the input signal at that time, but also depends on the clock signal and the original state of the sequential logic device, in other words, it can also be related to the previous input. Sequential logic devices include, for example, flip-flops, registers, registers, and the like. In contrast, "combinational logic device" means a logic device that does not have clocked inputs or pulsed control signals. The output of a combinational logic device at any moment depends only on the input at that moment, and has nothing to do with the original state of the combinational logic device. Combination logic gates include, for example, AND gates, OR gates, NAND gates, XOR gates, NOT gates, and buffers.

In one embodiment, the first asynchronous controller 24 receives a request signal In_Req from an upstream device, and accordingly sends an acknowledgment signal In_Ack to the upstream device. The second asynchronous controller 26 receives the request signal req1 from the first asynchronous controller 24 and sends an acknowledgment signal ack1 to the first asynchronous controller 24 accordingly. The third asynchronous controller 28 receives the request signal req2 from the second asynchronous controller 26 and sends an acknowledgment signal ack2 to the second asynchronous controller 26 accordingly. In the case of sending a data signal to a downstream device, the third asynchronous controller 28 sends a request signal Out_Req to the downstream device, and receives an acknowledgment signal Out_Ack from the downstream device. In one embodiment, the upstream device is, for example, the first device 10 and the downstream device is, for example, the third device 30 . The first asynchronous controller 24, the second asynchronous controller 26 and the third asynchronous controller 28 have the same configuration, for example, the first asynchronous controller 24, the second asynchronous controller 26 and the third asynchronous controller 28 are phase solution coupled click circuit. Alternatively, the first asynchronous controller 24 , the second asynchronous controller 26 and the third asynchronous controller 28 may be implemented by different asynchronous controllers, which is not limited in the present disclosure.

In the data path, the first sequential logic device 21 is coupled to the upstream device and receives the data signal In_Data, and transmits the data signal In_Data to the first functional circuit 23 in response to the first pulse signal from the first asynchronous controller 24 . The first functional circuit 23 receives the data signal In_Data and transmits the processed first data signal to the second sequential logic device 25 . The second sequential logic device 25 transmits the first data signal to the second functional circuit 27 in response to the second pulse signal from the second asynchronous controller 26 . The second functional circuit 27 receives the first data signal from the second sequential logic device 25 and transmits the processed second data signal to the third sequential logic device 29 . The third sequential logic device 29 transmits the second data signal to the downstream device in response to the third pulse signal from the third asynchronous controller 28 . In one embodiment, the first sequential logic device 21, the second sequential logic device 25 and the third sequential logic device 29 have the same configuration, for example, the first sequential logic device 21, the second sequential logic device 25 and the third sequential logic device Devices 29 are all registers. Alternatively, the first sequential logic device 21 , the second sequential logic device 25 and the third sequential logic device 29 may be implemented by different sequential logic devices, which is not limited in the present disclosure.

In order to ensure the correctness of the work of the asynchronous circuit, in terms of timing, the data signal should arrive at the sequential logic device before the pulse signal. For example, the data signal In_Data needs to reach the first sequential logic device 21 before the first pulse signal output by the first asynchronous controller 24 . Similarly, the first data signal from the first functional circuit 23 needs to reach the second sequential logic device 25 before the second pulse signal output from the second asynchronous controller 26, and the second data signal from the second functional circuit 27 It needs to reach the third sequential logic device 29 before the third pulse signal output from the third asynchronous controller 28 . Therefore, in the design stage of the asynchronous circuit, it is necessary to analyze the timing of each component of the asynchronous circuit to ensure the correct operation of the asynchronous circuit.

FIG. 3 shows a schematic circuit diagram of the asynchronous controller 24 according to some embodiments of the present disclosure. In one embodiment, the asynchronous controller 24 has an exclusive OR gate 31 , an exclusive OR gate 32 and an AND gate 33 , a first phase register 34 and a second phase register 35 . The exclusive OR gate 31 , the exclusive OR gate 32 and the AND gate 33 are configured to generate local pulse signals. The pulse signal will drive the phase registers 34, 35 and the first sequential logic device 21 for buffering data and starting the next handshake protocol. When the upstream device needs to send valid data, it will flip the In_Req signal once. The input request signal In_Req and the input acknowledgment signal In_Ack are subjected to an exclusive OR operation at the exclusive OR gate 31 to generate a high level. When the downstream device (such as the second asynchronous controller 26 ) receives the valid data sent by the asynchronous controller 24 , it will invert the output acknowledgment signal Out_Ack. This signal is NORed with the output request signal Out_Req at the NOR gate 32 to obtain a high level. When the input request signal In_Req is not equal to the input confirmation signal In_Ack and the output request signal Out_Req is equal to the output confirmation signal Out_Ack, the AND gate 33 will generate a high click signal as the clock signal of the first sequential logic device 21 to capture and store data. At the same time, the click signal will flip the phase registers 34 and 35, and change the values of the input confirmation signal In_Ack and the output request signal Out_Req, thereby completing a handshake protocol. In addition, this handshake protocol is two-phase, that is, each flip of the input confirmation signal In_Req represents the arrival of a valid data, rather than a high level. Although a schematic circuit diagram of a specific asynchronous controller is shown in FIG. 3 , the present disclosure is not limited thereto, and other asynchronous controllers may also be used.

FIG. 4 shows a schematic circuit diagram of an asynchronous controller 40 according to other embodiments of the present disclosure. In one embodiment, the asynchronous controller 40 has a first AND gate 41 , a second AND gate 42 , an OR gate 43 and a phase register 44 . The first AND gate 41 , the second AND gate 42 and the OR gate 43 are configured to generate local pulse signals. The pulse signal will drive the phase register 44 and the first sequential logic device 21 for buffering data and starting the next handshake protocol. When the upstream device needs to send valid data, it will flip the In_Req signal once. The inversion signal of the input request signal In_Req is ANDed with the input acknowledgment signal In_Ack signal and the output acknowledgment signal Out_Ack at the first AND gate 41, and the inversion of the input request signal In_Req and the input acknowledgment signal In_Ack signal and the output acknowledgment signal Out_Ack The phase signal is ANDed at the second AND gate 42 . The outputs of the first AND gate 41 and the second AND gate 42 are ORed at the OR gate 43 . When the input request signal In_Req is not equal to the input confirmation signal In_Ack and the output request signal Out_Req is equal to the output confirmation signal Out_Ack, the OR gate 43 will generate a high click signal as the clock signal of the first sequential logic device 21 to capture and store data. At the same time, the click signal will flip the phase register 44 to change the values of the input confirmation signal In_Ack and the output request signal Out_Req, thereby completing a handshake protocol. In addition, this handshake protocol is two-phase, that is, each flip of the input confirmation signal In_Req represents the arrival of a valid data, rather than a high level.

The bundled data handshake protocol in the asynchronous circuit needs delay matching to ensure the validity of the data, that is, the delay for the request signal sent by the asynchronous controller to reach the next-level asynchronous controller must be greater than the maximum delay of the corresponding data path to ensure the next Level sequential logic devices can latch to the correct data. However, since the click controller structure uses the output of the phase register as the req signal to generate the clock signal of the next click circuit, this path is not a timing path, so conventional EDA tools cannot perform timing analysis on it. In some embodiments of the present disclosure, the asynchronous circuit can be constrained so that a conventional EDA tool can perform timing analysis on the control part and the data path of the asynchronous circuit at the same time, so as to ensure that the asynchronous circuit can work normally.

A method for designing an asynchronous circuit according to some embodiments of the present disclosure will be described below with reference to an example of an asynchronous circuit. The method can be executed by a processor of an electronic device such as a computer. For example, when loading a netlist file representing an asynchronous circuit into an electronic device, the processor may perform timing analysis on the designed asynchronous circuit according to some embodiments of the present disclosure. When the timing analysis results show that the timing between the various components of the asynchronous circuit is incorrect (for example, the delay between two asynchronous controllers is less than the delay between the corresponding sequential logic devices), the asynchronous circuit can be adjusted based on the timing analysis results , such as adding delay circuit modules between asynchronous controllers. Although the execution of some embodiments of the present disclosure is described herein with a processor, this is for illustration only, and not to limit the scope of the present disclosure. Other computing devices, such as graphics processors, etc., may be used to implement the methods of some embodiments of the present disclosure.

In one embodiment, the processor determines the first pulse signal generated by the first asynchronous controller in the asynchronous circuit as the first clock signal, and determines the second pulse signal generated by the second asynchronous controller in the asynchronous circuit as Second clock signal. A second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is offset by a first predetermined amount of time relative to the first clock signal.

In one embodiment, the processor can use the event starting point of the asynchronous circuit as the first asynchronous controller, that is, select the asynchronous controller that generates the first local pulse signal (for example, the asynchronous controller of the first stage of the pipeline) as the first asynchronous controller. An asynchronous controller. Then the local pulse of the first asynchronous controller is determined as the first clock signal clk1, and its clock cycle and rising and falling edges may have default values. In this case, the first clock signal clk1 is the source clock signal. For example, the processor may set the asynchronous controller 24 in FIG. 2 as the source asynchronous controller, and use the pulse signal generated by the asynchronous controller 24 as the clock signal clk1.

The processor may declare the local pulse generated by the next-level asynchronous controller as the second clock signal clk2, whose source clock signal is the first clock signal clk1. The second clock signal clk2 is shifted by a small amount relative to the first clock signal clk1, so that the second clock signal clk2 will be regarded as shifted by a predetermined value (for example, 0.01 nanoseconds, 0.01 ns) along the propagation path of the first clock signal clk1 ), the second clock signal clk2 has a fixed phase relationship with the first clock signal clk1, and can be regarded as a synchronous clock by the EDA software. The local pulse generated by the next-level controller is regarded as the third clock signal clk3 propagated by the second clock signal clk2. Similarly, the third clock signal clk3 is shifted relative to the second clock signal clk2 by the same small amount. Through this method, an n-stage pipeline can obtain n phase-related clocks clk1, clk2...clkn. Since these n clocks share the same source clock, that is, the clock corresponding to the first clock signal clk1, but the propagation paths are different and have different phase differences, the EDA tool will regard it as a synchronous clock and analyze the relationship between these n clocks. timing path. By setting the offset predetermined value to be much smaller than the period of the pulse signal, it is possible to prevent a plurality of pulse signals from interfering with each other.

FIG. 5 shows a schematic diagram of a clock signal propagation path 500 according to some embodiments of the present disclosure. The first asynchronous controller generates a first pulse signal click1, and the second asynchronous controller generates a second pulse signal click2. The first asynchronous controller provides the first pulse signal click1 to the first sequential logic device 52 , and the second asynchronous controller provides the second pulse signal click2 to the second sequential logic device 56 . The first sequential logic device 52 operates in response to receiving the first pulse signal click1 , such as latching the received data and providing it to the functional circuit 54 . The second sequential logic device 56 operates in response to receiving the second pulse signal click2 , eg, latches and provides the calculated data from the functional circuit 54 to downstream devices.

As mentioned above, in one embodiment, the processor determines the first pulse signal click1 generated by the first asynchronous controller in the asynchronous circuit as the first clock signal clk1, and determines the first pulse signal click1 generated by the second asynchronous controller in the asynchronous circuit The second pulse signal click2 is determined as the second clock signal clk2. The processor may then determine a first clock propagation period of the first clock signal clk1 and a second clock propagation period of the second clock signal clk2, wherein the first clock propagation period represents receipt of the first input from the first asynchronous controller The time period from requesting In_Req to the first asynchronous controller to generate the first pulse signal click1, and the second clock propagation time period means receiving the first input request In_Req from the first asynchronous controller to the second asynchronous controller to generate the second pulse signal click2 time period. For example, the dashed line 51 represents the propagation path of the first clock signal clik1 and has a first propagation period tc1=1 ns, while the dashed line 53 represents the propagation path of the second clock signal clk2 and has a second propagation period tc2=5 ns.

The processor may determine a first clock propagation difference Δt between the first clock propagation time period tc1 and the second clock propagation time period tc2. For example, in the case that the first clock propagation time period tc1 is 1 ns and the second clock propagation time period tc2 is 5 ns, the first clock propagation difference Δtc=tc2−tc1=4 ns.

The processor may determine a first data propagation time period td1 between the first sequential logic device 52 and the second sequential logic device 56 . The first sequential logic device 52 is coupled to the first asynchronous controller and operates based on the first pulse signal, and the second sequential logic device 54 is coupled to the second asynchronous controller and operates based on the second pulse signal. In FIG. 5 , the first data propagation time period td1 from the first sequential logic device 52 to the second sequential logic device 56 is represented by a dotted line 55 .

In one embodiment, based on the first clock propagation difference Δtc and the first data propagation time period td1, the processor may generate a delay report. The delay report can be automatically displayed on the display screen during the asynchronous circuit design process or displayed on the display screen in response to user instructions or input. Alternatively, the delay may not be displayed, but sent to other electronic devices in a wired or wireless manner for analysis. The delay report may include various information related to the first data propagation time period and the first clock propagation difference. For example, the delay report may include a first data propagation time value representing the first data propagation time period td1, a first clock propagation difference Δtc, a phase value representing the first data propagation time period td1 and the first clock propagation difference Δtc The first delay value of the subtraction result, the comparison result of the first data propagation time period td1 and the first clock propagation difference Δtc, the first clock propagation time value representing the first clock propagation time period, or the second clock propagation time The second clock propagation time value for the segment, and so on. The delay report may include any relevant information for determining whether the data signal is earlier than the clock signal. This disclosure is not limited in this regard.

In one embodiment, based on the first clock propagation difference Δtc and the first data propagation time period td1, the processor may determine a delay setting between the first asynchronous controller and the second asynchronous controller. For example, the processor may determine latency settings based on various information in the latency report. To ensure correct timing, the data signal needs to arrive at the device in timing before the pulse signal. For example, at the second sequential logic device, the signal of the data path needs to arrive before the pulse signal click2. Therefore, if the processor determines through the EDA tool that the first data propagation time period td1 is not greater than the first clock propagation difference Δtc, for example, not greater than 4ns, it indicates that the timing of the circuit in Figure 5 is correct and the first asynchronous The current delay setting between the controller and the second asynchronous controller, i.e. no additional delay circuit needs to be added. If the processor determines through the EDA tool that the first data propagation time period td1 is greater than the first clock propagation difference Δtc, for example, greater than 4 ns, it indicates that the timing of the circuit in Figure 5 is wrong, between the first asynchronous controller and the second Additional delay circuits need to be added between asynchronous controllers. In one embodiment, the delay of the added delay circuit is not smaller than the difference between the first data propagation time period td1 and the first clock propagation difference Δtc. In one embodiment, an appropriate delay circuit can be selected based on the difference between the first data propagation time period td1 and the first clock propagation difference Δtc. In another embodiment, a unit delay circuit having a unit delay period may be selected and inserted between the first asynchronous controller and the second asynchronous controller, and the above process is repeated to determine the first data propagation time Whether segment td1 is not greater than the modified first clock propagation difference Δtc. If not, it indicates that the modified asynchronous circuit has met the timing requirements after inserting the delay circuit. If it is greater than, you can continue to add a unit delay circuit between the first asynchronous controller and the second asynchronous controller, so that the newly added unit delay circuit and the previously added unit delay circuit are connected in series between the first asynchronous controller and the second asynchronous controller between the two asynchronous controllers until the timing requirements are met. Alternatively, the circuit design of the functional circuit 54 can also be optimized to ensure that the first data propagation time period td1 is not greater than the first clock propagation difference Δtc.

FIG. 6 shows a schematic block diagram of clock signal propagation in a sequential circuit 600 according to some embodiments of the present disclosure. In one embodiment, the processor configures the first asynchronous controller 62 to define a source clock named clk1. The period of the source clock is 30 ns, the waveform shape is rising at 0 ns and falling at 2 ns, and the defined point is the signal line on which the first asynchronous controller generates the click pulse. The processor sets the second asynchronous controller 64, defines a sub-clock named clk2, and its clock source is the upper-level clock, that is, the clock terminal of the phase register of the first asynchronous controller 62, and the offset is the upper-level clock The clock is shifted backward by 0.01 ns, and the defined point is the signal line where the second asynchronous controller 64 generates the click pulse. Similarly, the processor sets the third asynchronous controller 66 to define a sub-clock called CLK3, whose clock source is the clock terminal of the phase register of the second asynchronous controller 64, and whose offset is backward from the previous clock Moved by 0.01 ns, the defined point is the signal line where the third asynchronous controller 66 generates the click pulse. By analogy, for the local pulse signal generated by the nth click unit, the processor can declare it as a sub-clock generated from the n-1th clock.

The timing situation for sequential asynchronous circuits was described above. However, asynchronous circuits do not only include sequential asynchronous circuits, but may also include other types of asynchronous circuits, such as non-sequential pipeline circuits and conditional selection asynchronous circuits. FIG. 7 shows a schematic block diagram of clock signal propagation in a non-sequential asynchronous circuit 700 according to some embodiments of the present disclosure. The non-sequential asynchronous circuit 700 includes, for example, an Mth asynchronous controller 72 , an M+1th asynchronous controller 74 and an Nth asynchronous controller 76 , where M represents an integer greater than 0, and N represents an integer greater than M. For ease of description, the sequential logic device coupled with the asynchronous controller is not shown in FIG. 7 , but it can be understood that the non-sequential asynchronous circuit 700 includes a sequential logic device corresponding to the asynchronous controller. The Mth asynchronous controller 72 may receive a request signal from an upstream device, and the M+1th asynchronous controller 74 may receive a request signal from the Mth asynchronous controller 72 . Operations of the Mth asynchronous controller 72 and the M+1th asynchronous controller 74 may be similar to those of the first asynchronous controller 62 and the second asynchronous controller 64 in FIG. 6 , and will not be repeated here. In some embodiments, one or more asynchronous controllers may be cascaded between the Mth asynchronous controller 72 and the Nth asynchronous controller 76, for example, the M+1th asynchronous controller. In some embodiments, there may be no M+1th asynchronous controller, and the Nth asynchronous controller is directly cascaded after the Mth controller.

Different from FIG. 6 , the Nth asynchronous controller 76 is not cascaded to downstream devices, but is coupled to the Mth asynchronous controller 72 . In other words, the output of the pulse signal of the Mth asynchronous controller 72 also depends on the request signal of the Nth asynchronous controller. Therefore, the circuit in Fig. 7 constitutes a non-sequential asynchronous circuit. In one embodiment, the processor determines the Nth pulse signal generated by the Nth asynchronous controller of the asynchronous circuit as the Nth clock signal, wherein the first asynchronous controller is coupled to the Nth asynchronous controller in stages, and the first asynchronous controller Any two adjacent asynchronous controllers from the Nth asynchronous controller to the Nth asynchronous controller are offset from each other by a first predetermined amount of time, the output of the Nth asynchronous controller is coupled to the input of the Mth asynchronous controller, where N means greater than M an integer of . The processor then determines the timing period P, where P represents the difference between N and M.

In one embodiment, the register corresponding to the Nth asynchronous controller in the pipeline needs to send data to the register corresponding to the Mth asynchronous controller, which is a non-sequential data transmission. In this case, a correct settling time check should be done between the Nth pulse of the Mth asynchronous controller 72 and the Mth pulse of the Nth asynchronous controller 76 . In conventional EDA timing analysis, the setup time check will check the first pulse of the Mth asynchronous controller 72 and the first pulse of the Nth asynchronous controller 76 , resulting in timing analysis errors. In order to correct this type of timing analysis, in some embodiments of the present disclosure, the processor sets non-sequential data transmission constraints as multi-cycle timing analysis in the EDA timing analysis, so as to ensure the correctness of the timing analysis. The number of cycles of the timing cycle is jointly determined by the sending phase and the receiving phase. When the sending asynchronous controller is N and the receiving asynchronous controller is M, the timing cycle P is N-M. For example, when N=3 and M=1, the processor may determine the number of cycles P to be N-M=2. On this basis, the processor determines the delay setting between the Nth asynchronous controller and the Mth asynchronous controller based on the timing cycle P. For example, when the request transmitted from the Nth asynchronous controller to the Mth asynchronous controller causes the click signal of the Mth asynchronous controller to be transmitted from the sequential logic device corresponding to the Nth asynchronous controller to the corresponding to the Mth asynchronous controller When the data signal of the sequential logic device reaches the sequential logic device corresponding to the Mth asynchronous controller, a delay circuit may be added between the Nth asynchronous controller and the Mth asynchronous controller. The adding method is similar to that described above with respect to FIG. 6 , and will not be repeated here. Following this principle, timing constraints can be imposed on all non-sequentially transmitted data paths to ensure their correctness.

In one embodiment, the processor can set the Mth asynchronous controller, define a source clock name as clkm, the cycle is 30ns, the waveform shape is 0ns rising, 2ns falling, the definition point is that the Mth asynchronous controller generates click Pulse signal line. The processor sets the M+1th asynchronous controller, defines a sub-clock named clkm+1, and its clock source is the upper-level clock, that is, the clock terminal of the phase register of the Mth asynchronous controller, and the offset is the upper The primary clock moves backward by 0.01 ns, and the defined point is the signal line where the M+1th asynchronous controller generates the click pulse. Similarly, the processor defines a sub-clock named clkn for the Nth asynchronous controller, its clock source is the clock terminal of the phase register in the N-1th asynchronous controller, and the offset is 0.01 backwards from the upper-level clock ns, the definition point is the signal line where the Nth asynchronous controller generates the click pulse. For the timing analysis of the Nth asynchronous controller to the Mth asynchronous controller, the processor sets a multi-cycle timing check, and the clock check from clkn to clkm is set to N-M cycles, and the rule is that the number of cycles of the multi-cycle timing analysis is given by The sending phase and the receiving phase are jointly determined. When the sending phase is N and the receiving phase is M, the number of multi-cycle timing analysis is N-M.

As mentioned above, in addition to the conventional data flow controller proposed above, there may be more complex data flow control in the actual asynchronous circuit design, such as conditional selection control multiplexer (Mux) and demultiplexer ( Demultiplexer, DEMUX). For the single-input multiple-output conditional selection asynchronous circuit, it is necessary to ensure that the selection signal is valid before the valid data arrives, which can be guaranteed by delay matching. For multiple inputs and one output conditionally selected asynchronous circuit, the local pulse click can be triggered by any input req signal, and the delays of these different inputs may be different, resulting in the timing of click pulse generation is not fixed of. Therefore, in some embodiments of the present disclosure, multiple clocks can be defined on the same port, and the clocks defined later will not overwrite the existing clocks, and then multiple clocks are one-to-one corresponding to different inputs, according to different The input delay determines the phase relationship between the corresponding sub-clock and the source clock, thereby covering all input timing relationships. However, it is physically impossible for multiple clocks defined on the same port to exist at the same time, so it is necessary to group clocks that do not physically exist at the same time to interrupt the timing analysis between them. Through the conditional selection data flow constraints, the timing analysis of the conditional selection controller can be performed.

FIG. 8 shows a schematic block diagram of clock signal propagation of a condition selection circuit 800 according to some embodiments of the present disclosure. The condition selection circuit 800 includes, for example, a first asynchronous controller 82 , a second asynchronous controller 84 and a third asynchronous controller 86 . For ease of description, the sequential logic device coupled with the asynchronous controller is not shown in FIG. 8 , but it can be understood that the condition selection circuit 800 includes a sequential logic device corresponding to the asynchronous controller. The first asynchronous controller 82 can receive request signals from upstream devices, and both the second asynchronous controller 84 and the third asynchronous controller 86 can receive request signals from the first asynchronous controller 82 . In one embodiment, the processor sets the first asynchronous controller 82, defines a source clock name as clk1, the cycle is 30ns, the waveform shape is 0ns rising, 2ns falling, the definition point is generated by the first asynchronous controller 82 The signal line of the click pulse. The processor sets the second asynchronous controller 84, defines a sub-clock called clk2, and its clock source is the upper-level clock, that is, the clock terminal of the phase register in the first asynchronous controller 82, and the offset is the last The stage clock is shifted backward by 0.01 ns, and the defined point is the signal line where the second asynchronous controller 84 generates the click pulse. Similarly, the processor defines a sub-clock named clk3 for the third asynchronous controller 86, the clock source of which is the clock terminal of the phase register in the first asynchronous controller 82, and the offset is 0.01 backward shifted by the upper-level clock ns, the defined point is the signal line on which the third asynchronous controller 86 generates the click pulse. In addition, the third asynchronous controller 86 defines a second sub-clock called clk4 instead of covering clk3, and its clock source is the clock terminal of the phase register in the second asynchronous controller 84, and the offset is 0.01 backwards from the previous clock ns, and the definition point is consistent with clk3. At the same time, the clock signals clk3 and clk4 are set as clock groups that physically do not exist at the same time, interrupting the timing analysis between the two clocks. Through the above method, the timing of the conditionally selected asynchronous circuit can also be analyzed. For example, the processor may determine a delay setting between the first asynchronous controller 82 and the second asynchronous controller 84 or the third asynchronous controller 86 . For example, whether a delay circuit needs to be inserted between the first asynchronous controller 82 and the second asynchronous controller 84 or the third asynchronous controller 86 . The way of inserting the delay circuit is similar to that described above with respect to FIG. 5 and FIG. 6 , and will not be repeated here.

On the other hand, from the perspective of the third asynchronous controller 86 , it is not only coupled to the second asynchronous controller 84 but also coupled to the first asynchronous controller 82 . In one embodiment, the different pulse signals corresponding to the requests from the first asynchronous controller 82 and the second asynchronous controller 84 can be determined as different clock signals, and each clock signal is offset relative to the upper stage Shift by a predetermined amount of time. Since two pulses or clock signals do not exist at the same time in physical implementation, different clock signals can be assigned to different clock signal groups. The processor then calculates the clock signal propagation delay for each group separately in the different groups and analyzes the existing relationship of the pulse signal to the data signal as described above to determine the delay setting between the asynchronous controllers. Thus, correct timing analysis can be performed on conditionally selected asynchronous circuits.

FIG. 9 shows a schematic circuit diagram of an asynchronous controller 900 according to other embodiments of the present disclosure. The asynchronous controller 900 can be applied to a conditional asynchronous controller that regulates single-input multiple-output in an asynchronous circuit. In one embodiment, the asynchronous controller 900 has a first XOR gate 91, a second XOR gate 96, a first XOR gate 92, a second XOR gate 93, a third XOR gate 99, an AND gate 94, A first phase register 95 , a second phase register 97 and a third phase register 98 . The first XOR gate 91 , the first XOR gate 92 , the second XOR gate 93 and the AND gate 94 are configured to generate local pulse signals. The pulse signal will drive the phase registers 95, 97, 98 and sequential logic devices for buffering data and starting the next handshake protocol. When the upstream device needs to send valid data, it will flip the InA_req signal once. The input request signal InA_req and the input acknowledgment signal InA_ack are subjected to an exclusive OR operation at the first exclusive OR gate 91 to generate a high level. When the first downstream device (such as the second asynchronous controller 26 ) receives the valid data sent by the asynchronous controller 900 , it will invert the output acknowledgment signal OutB_ack. This signal is NORed with the output request signal OutB_req at the first NOR gate 92 to obtain a high level. Similarly, when the second downstream device receives valid data sent by the asynchronous controller 900 , it will toggle the output acknowledgment signal OutC_ack. This signal is NORed with the output request signal OutC_req at the first NOR gate 92 to obtain a high level. When the input request signal InA_req is not equal to the input confirmation signal InA_ack, the output request signal OutB_req is equal to the output confirmation signal OutB_ack and the output request signal OutC_req is equal to the output confirmation signal OutC_ack, the AND gate 97 will generate a high click signal as a sequential logic device The clock signal used to capture and store data. The click signal will flip the first phase register 95 to change the value of the input acknowledgment signal InA_ack. In addition, based on the sel signal, OutB_req signal and OutC_req, the click signal will change the output of the

phase register

97 or 98 to change the value of the output request signal OutB_req or OutC_req, thereby completing a handshake protocol. In addition, this handshake protocol is two-phase, that is, each flip of the input confirmation signal In_Req represents the arrival of a valid data, rather than a high level. To ensure proper operation of the asynchronous circuit, the select signal sel may reach the asynchronous controller 900 before the data signal reaches the sequential logic gates. Although a schematic circuit diagram of a specific asynchronous controller is shown in FIG. 9 , the present disclosure is not limited thereto, and other asynchronous controllers may also be used.

Fig. 10 shows a schematic circuit diagram of an asynchronous controller 1000 according to other embodiments of the present disclosure. The asynchronous controller 1000 can be applied to a conditional asynchronous controller that regulates multiple inputs and single outputs in an asynchronous circuit. In one embodiment, the asynchronous controller 1000 has a first exclusive OR gate 101, a second exclusive OR gate 102, a first exclusive OR gate 103, a second AND gate 104, a second AND gate 105, an OR gate 106, a first Phase register 107 , third XOR gate 108 , second phase register 109 , second XOR gate 110 and third phase register 111 . The first XOR gate 101 , the second XOR gate 102 , the first XOR gate 103 , the second AND gate 104 , the second AND gate 105 and the OR gate 106 are configured to generate local pulse signals. The pulse signal will drive the phase registers 107, 109, 111 and sequential logic devices for buffering data and starting the next handshake protocol. When the upstream device needs to send valid data, it will flip the InA_req or InB_req signal once. The input request signal InA_req or InB_req and the input acknowledgment signal InA_ack or InB_ack are subjected to an exclusive OR operation at the first exclusive OR gate 101 or the second exclusive OR gate 102 to generate a high level. When a downstream device (such as the second asynchronous controller 26 ) receives valid data sent by the asynchronous controller 1000 , it will reverse the output acknowledgment signal OutC_ack. This signal is NORed with the output request signal OutC_req at the first NOR gate 103 to obtain a high level. Based on any high output level of the first AND gate 104 or the second AND gate 105 , the OR gate 107 will generate a pulled high click signal as a clock signal of the sequential logic device for capturing and storing data. The click signal will flip the third phase register 111 to change the value of the input acknowledgment signal InA_ack. In addition, based on the sel signal, InA_ack signal and InB_ack signal, the click signal will flip the

phase register

107 or 109 to change the value of the input acknowledgment signal InA_ack or InB_ack, thereby completing a handshake protocol. To ensure proper operation of the asynchronous circuit, the select signal sel may reach the asynchronous controller 1000 before the data signal reaches the sequential logic gates.

In one embodiment, after the processor completes the timing analysis, the processor may synthesize the asynchronous circuit. Because there is a loop in the asynchronous controller, the synthesized circuit may be different from the expected one, affecting the function of the asynchronous circuit. In order to prevent the synthesized circuit from being different than expected and from affecting the function of the asynchronous circuit, the processor may set the asynchronous circuit not to be optimized before the synthesis process, so as to maintain the structure of the asynchronous circuit during synthesis. In one embodiment, when an asynchronous circuit is synthesized using an EDA tool, the asynchronous circuit may be synthesized and implemented using a conventional EDA tool. This process can be basically the same as the integrated synchronous circuit, or it can be mixed with the synchronous circuit.

In one embodiment, the processor can also perform timing analysis on the asynchronous circuit under multiple process corners. Affected by PVT, the same chip has different delays under different operating conditions, which is very important for the delay matching process of asynchronous circuits. Under the constraint of propagation timing, the static timing analysis of the present disclosure will analyze the circuit function for the timing models under different process corners, that is, multi-angle and multi-mode analysis, to ensure that the constrained circuit can meet the timing requirements under any conditions.

In one embodiment, the processor can also selectively widen the pulse width. Propagation timing constraints regard the handshake process of asynchronous circuits as the clock propagation process. There are combinational logic and registers on this path, so that static timing analysis cannot obtain the pulse width of the actually generated local pulse click. Therefore, the pulse width checking module also performs timing simulation on the asynchronous circuit after other timing constraints are satisfied, to determine whether the click pulse width of each stage actually meets the minimum pulse width requirement of the register. The width of the local pulse is determined by the delay of the combined logic that generates the pulse, and the structure of the click controller ensures that the delay of the combined logic is generally greater than the minimum pulse width of the register, and no special processing is required. In some cases, if the width of the local pulse is stretched, the processor can add a buffer unit on the register output pin in the click unit. The expanded width of the buffer unit can be selected according to actual needs, which is not limited in the present disclosure.

FIG. 11 shows a schematic flowchart of a method 1100 according to some embodiments of the present disclosure. It can be understood that the various aspects described above with respect to FIGS. 1-10 can be selectively applied to the method 1100 . At 1102, determine the first pulse signal generated by the first asynchronous controller in the asynchronous circuit as the first clock signal. At 1104, determine a second pulse signal generated by a second asynchronous controller in the asynchronous circuit as a second clock signal. A second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is offset by a first predetermined amount of time relative to the first clock signal. At 1106, a first clock propagation difference corresponding to the first clock signal and the second clock signal is generated. In one embodiment, generating the first clock propagation difference includes determining a first clock propagation time period of the first clock signal and a second clock propagation time period of the second clock signal. The first clock propagation time period represents the time period from the first asynchronous controller receiving the first input request to the first asynchronous controller generating the first pulse signal, and the second clock propagation time period represents the time period from the first asynchronous controller receiving the first A time period from an input request to the second asynchronous controller generating the second pulse signal. A first clock propagation difference between the first clock propagation time period and the second clock propagation time period is determined. At 1108, a first data propagation time period between the first sequential logic gate and the second sequential logic gate is determined. The first sequential logic gate is coupled to the first asynchronous controller and operates based on the first pulse signal, and the second sequential logic gate is coupled to the second asynchronous controller and operates based on the second pulse signal. At 1110, generate a delay report related to the first data propagation time period and the first clock propagation difference. In one embodiment, the method further includes determining a delay setting between the first asynchronous controller and the second asynchronous controller based on the first clock propagation difference and the first data propagation time period.

FIG. 12 shows a schematic block diagram of an electronic device 1200 according to some embodiments of the present disclosure. Electronic device 1200 may be used in the design of asynchronous circuits. The electronic device 1200 includes a clock signal determination unit 1202 , a clock propagation difference determination generation unit 1204 , a data propagation time period determination unit 1206 , and a delay report generation unit 1208 . The clock signal determination unit 1202 is used to determine the first pulse signal generated by the first asynchronous controller in the asynchronous circuit as the first clock signal; and determine the second pulse signal generated by the second asynchronous controller in the asynchronous circuit as the first clock signal. Two clock signals. A second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is offset by a first predetermined amount of time relative to the first clock signal. The clock propagation difference determining generating unit 1204 is configured to generate a first clock propagation difference corresponding to the first clock signal and the second clock signal. The data propagation time period determining unit 1206 is configured to determine a first data propagation time period between the first sequential logic device and the second sequential logic device, the first sequential logic device is coupled to the first asynchronous controller and based on the The second sequential logic device is coupled to the second asynchronous controller and operates based on the second pulse signal. The delay report generating unit 1208 is configured to generate a delay report related to the first data propagation time period and the first clock propagation difference.

Figure 13 shows a block diagram of an example device that may be used to implement some embodiments of the present disclosure. The device 1300 may be used to implement the electronic device 1200 . As shown, device 1300 includes computing unit 1301, which may be loaded into RAM and/or ROM according to computer program instructions stored in random access memory (RAM) and/or read only memory (ROM) 1302 or from storage unit 1307 1302 to perform various appropriate actions and processes. In the RAM and/or ROM 1302, various programs and data necessary for the operation of the device 1300 may also be stored. The computing unit 1301 and the RAM and/or ROM 1302 are connected to each other via a bus 1303. An input/output (I/O) interface 1304 is also connected to the bus 1303 .

Multiple components in the device 1300 are connected to the I/O interface 1304, including: an input unit 1305, such as a keyboard, a mouse, etc.; an output unit 1306, such as various types of displays, speakers, etc.; a storage unit 1307, such as a magnetic disk, an optical disk, etc. ; and a communication unit 1308, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1308 allows the device 1300 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.

The computing unit 1301 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 1301 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The calculation unit 1301 executes various methods and processes described above, such as the method 1100 . For example, in some embodiments, method 1100 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1307 . In some embodiments, part or all of the computer program may be loaded and/or installed onto device 1300 via RAM and/or ROM and/or communication unit 1308 . When a computer program is loaded into RAM and/or ROM and executed by computing unit 1301, one or more steps of method 1100 described above may be performed. Alternatively, in other embodiments, the computing unit 1301 may be configured to execute the method 1100 in any other suitable manner (for example, by means of firmware).

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

In addition, while operations are depicted in a particular order, this should be understood to require that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations should be performed to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while the above discussion contains several specific implementation details, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method for designing an asynchronous circuit comprising:

determining the first pulse signal generated by the first asynchronous controller in the asynchronous circuit as the first clock signal;

determining a second pulse signal generated by a second asynchronous controller in the asynchronous circuit as a second clock signal, the second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is relatively offsetting the first clock signal by a first predetermined amount of time;

generating a first clock propagation difference corresponding to the first clock signal and the second clock signal;

determining a first data propagation time period between a first sequential logic device coupled to the first asynchronous controller and operating based on the first pulse signal, and a second sequential logic device, the the second sequential logic device is coupled to the second asynchronous controller and operates based on the second pulse signal; and

A delay report is generated relating to the first data propagation time period and the first clock propagation difference.
The method of claim 1, wherein generating a first clock propagation difference corresponding to the first clock signal and the second clock signal comprises:

determining a first clock propagation time period of the first clock signal and a second clock propagation time period of the second clock signal, the first clock propagation time period representing a first clock propagation time period received from the first asynchronous controller The time period from the input request to the generation of the first pulse signal by the first asynchronous controller, the second clock propagation time period represents the time period from receiving the first input request to the second asynchronous controller from the first asynchronous controller a time period during which the controller generates the second pulse signal; and

The first clock propagation difference between the first clock propagation time period and the second clock propagation time period is determined.
The method of claim 1 or 2, wherein generating a delay report related to the first data propagation time period and the first clock propagation difference comprises:

generating a first data propagation time value representing the first data propagation time period;

subtracting the first data propagation time value and the first clock propagation difference value to determine a first delay value; and

The delay report including the first delay value is generated.
The method of claim 1 or 2, wherein generating a delay report related to the first data propagation time period and the first clock propagation difference comprises:

generating a first data propagation time value representing the first data propagation time period;

comparing the first data propagation time value and the first clock propagation difference value to generate a comparison result; and

The latency report is generated including results of the comparison.
The method according to any one of claims 1-4, further comprising:

A delay setting between the first asynchronous controller and the second asynchronous controller is determined based on the first clock propagation difference and the first data propagation time period.
The method of claim 5, wherein determining a delay between the first asynchronous controller and the second asynchronous controller is based on the first clock propagation difference and the first data propagation time period Settings include:

providing a delay circuit between the first asynchronous controller and the second asynchronous controller in response to the first data propagation time period being greater than the first clock propagation difference; or

In response to the first data propagation time period being not greater than the first clock propagation difference, no delay circuit is provided between the first asynchronous controller and the second asynchronous controller.
The method of claim 6, wherein a delay circuit is provided between the first asynchronous controller and the second asynchronous controller in response to the first data propagation time period being greater than the first clock propagation difference include:

determining a first path difference between the first clock propagation difference and the first data propagation difference;

determining the unit delay period of the delay circuit;

Based on the first path difference and the unit delay period, setting one or more delay circuits in series so that the total delay period of the one or more delay circuits in series is not lower than the first A path difference.
The method according to any one of claims 1-7, further comprising:

Determining the Mth pulse signal generated by the Mth asynchronous controller of the asynchronous circuit as the Mth clock signal, where M represents an integer greater than 0;

The Nth pulse signal generated by the Nth asynchronous controller of the asynchronous circuit is determined as the Nth clock signal, the first asynchronous controller is coupled to the Nth asynchronous controller step by step, and the first asynchronous controller to any two adjacent asynchronous controllers of the Nth asynchronous controller offset from each other by the first predetermined amount of time, the output of the Nth asynchronous controller being coupled to the Mth asynchronous controller's Input, where N represents an integer greater than M;

determining a timing period P, where P represents the difference between N and M; and

Based on the timing period P, a delay setting between the Nth asynchronous controller and the Mth asynchronous controller is determined.
The method according to claim 8, wherein based on the timing period P, determining a delay setting between the Nth asynchronous controller and the Mth asynchronous controller comprises:

determining the Nth clock propagation time period of the Nth clock signal, the Nth clock propagation time period representing the first input request received from the first asynchronous controller to the generation of the Nth pulse by the Nth asynchronous controller the time period of the signal;

determining a clock propagation period in a Pth timing cycle after the Mth asynchronous controller generates the Mth clock signal;

determining an Nth clock propagation difference between the Nth clock propagation time period and the clock propagation time period in the Pth timing cycle;

determining an Nth data propagation time period between an Nth sequential logic device and an Mth sequential logic device, the Nth sequential logic device being coupled to the Nth asynchronous controller and operating based on the Nth pulse signal, the the Mth sequential logic device is coupled to the Mth asynchronous controller and operates based on the Mth pulse signal; and

A delay setting between the Nth asynchronous controller and the Mth asynchronous controller is determined based on the Nth clock propagation time period and the Nth data propagation time period.
The method according to any one of claims 1-9, further comprising:

The structure of the asynchronous circuit is maintained during synthesis of the asynchronous circuit.
The method according to any one of claims 5-7, wherein the first asynchronous controller and the second asynchronous controller are determined based on the first clock propagation difference and the first data propagation time period. Delay settings between switches include:

determining a delay between the first asynchronous controller and the second asynchronous controller based on the first clock propagation difference and the first data propagation time period of the asynchronous circuit at different process angles set up.
The method according to any one of claims 1-11, further comprising:

determining a first pulse width of the first pulse signal and a second pulse width of the second pulse signal; and

In response to the first pulse width or the second pulse width being lower than a pulse width threshold, a pulse stretching circuit is correspondingly set in the first asynchronous controller or the second asynchronous controller to widen the first pulse signal or the width of the second pulse signal.
The method of any one of claims 1-12, wherein the asynchronous circuit comprises a single-rail asynchronous circuit;

said first asynchronous controller is an initial asynchronous controller; and

Both the first asynchronous controller and the second asynchronous controller include phase decoupling controllers.
The method according to any one of claims 1-13, wherein the second asynchronous controller is further coupled to a fourth asynchronous controller in the asynchronous circuit; the method further comprising:

determining a fourth pulse signal generated by the fourth asynchronous controller as a fourth clock signal;

determining the second pulse signal generated by the second asynchronous controller in response to the request from the fourth asynchronous controller as a fifth clock signal, where the fifth clock signal is shifted by a second relative to the fourth clock signal a predetermined amount of time;

assigning the second clock signal to a first clock grouping and assigning the fifth clock signal to a second clock grouping, the second clock grouping being different from the first clock grouping;

determining a fifth clock propagation time period of the fourth clock signal and a fifth clock propagation time period of the fifth clock signal, the fifth clock propagation time period indicating that a fourth The time period from the input request to the fourth asynchronous controller generating the fourth pulse signal, the fifth clock propagation time period represents the time period from receiving the fourth input request to the second asynchronous controller from the fourth asynchronous controller the time period during which the controller generates the fifth pulse signal;

determining a fourth clock propagation difference between the fourth clock propagation period and the fifth clock propagation period;

determining a fourth data propagation time period between a fourth sequential logic device coupled to the fourth asynchronous controller and operating based on the fourth pulse signal, and a fifth sequential logic device, the the fifth sequential logic device is coupled to the second asynchronous controller and operates based on the fifth pulse signal; and

A delay setting between the fourth asynchronous controller and the second asynchronous controller is determined based on the fourth clock propagation difference and the fourth data propagation time period.
A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including a program for executing the method described in any one of claims 1-14 method directive.
A computer program product, the computer program product comprising a plurality of programs, the plurality of programs configured to be executed by one or more processors, the plurality of programs comprising a method for performing any one of claims 1-14 Instructions for the method described.
An electronic device comprising:

one or more processors; and

A memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any one of claims 1-14.
An electronic device comprising:

A clock signal determination unit for

determining a first pulse signal generated by a first asynchronous controller in the asynchronous circuit as a first clock signal; and

determining a second pulse signal generated by a second asynchronous controller in the asynchronous circuit as a second clock signal, the second asynchronous controller is coupled to the first asynchronous controller, and the second clock signal is relatively offsetting the first clock signal by a first predetermined amount of time;

a clock propagation difference generating unit, configured to generate a first clock propagation difference corresponding to the first clock signal and the second clock signal;

a data propagation time period determining unit, configured to determine a first data propagation time period between the first sequential logic device and the second sequential logic device, the first sequential logic device is coupled to the first asynchronous controller and based on the operating on the first pulse signal, the second sequential logic device coupled to the second asynchronous controller and operating based on the second pulse signal; and

A delay report generating unit, configured to generate a delay report related to the first data propagation time period and the first clock propagation difference.
The electronic device according to claim 18, wherein the clock propagation difference generating unit comprises:

a clock propagation period determining unit, configured to determine a first clock propagation period of the first clock signal and a second clock propagation period of the second clock signal, the first clock propagation period representing The time period from when the first asynchronous controller receives the first input request to when the first asynchronous controller generates the first pulse signal, and the second clock propagation time period represents receiving the first asynchronous controller from the first asynchronous controller a time period from an input request to the second asynchronous controller generating the second pulse signal; and

A clock propagation difference determining unit, configured to determine a first clock propagation difference between the first clock propagation time period and the second clock propagation time period.
The electronic device according to claim 18 or 19, further comprising:

A delay setting determining unit, configured to determine a delay setting between the first asynchronous controller and the second asynchronous controller based on the first clock propagation difference and the first data propagation time period.
The electronic device according to claim 20, wherein the delay setting determining unit is further configured to

providing a delay circuit between the first asynchronous controller and the second asynchronous controller in response to the first data propagation time period being greater than the first clock propagation difference; or

In response to the first data propagation time period being not greater than the first clock propagation difference, no delay circuit is provided between the first asynchronous controller and the second asynchronous controller.
An electronic device according to any one of claims 20-21, wherein

The clock signal determining unit is further used for

determining the Mth pulse signal generated by the Mth asynchronous controller of the asynchronous circuit as the Mth clock signal, where M represents an integer greater than 0; and

The Nth pulse signal generated by the Nth asynchronous controller of the asynchronous circuit is determined as the Nth clock signal, the first asynchronous controller is coupled to the Nth asynchronous controller step by step, and the first asynchronous controller to any two adjacent asynchronous controllers of the Nth asynchronous controller offset from each other by the first predetermined amount of time, the output of the Nth asynchronous controller being coupled to the Mth asynchronous controller's Input, where N represents an integer greater than M;

The electronic device further includes a timing period determining unit, configured to determine a timing period P, where P represents a difference between N and M; and

The delay setting determining unit is further configured to determine a delay setting between the Nth asynchronous controller and the Mth asynchronous controller based on the timing period P.
The electronic device according to any one of claims 18-22, further comprising:

A maintaining unit for maintaining the structure of the asynchronous circuit during synthesis of the asynchronous circuit.
The electronic device according to any one of claims 20-22, wherein the delay setting determination unit is further configured to be based on the first clock propagation difference of the asynchronous circuit at different process angles and the first A data propagation time period determines a delay setting between the first asynchronous controller and the second asynchronous controller.
The electronic device according to any one of claims 18-24, further comprising:

pulse stretching unit for

determining a first pulse width of the first pulse signal and a second pulse width of the second pulse signal; and

In response to the first pulse width or the second pulse width being lower than a pulse width threshold, a pulse stretching circuit is correspondingly set in the first asynchronous controller or the second asynchronous controller to widen the first pulse signal or the width of the second pulse signal.
The electronic device according to any one of claims 18-25, wherein the second asynchronous controller is further coupled to a fourth asynchronous controller in the asynchronous circuit;

The clock signal determining unit is further used for

determining a fourth pulse signal generated by the fourth asynchronous controller as a fourth clock signal; and

determining the second pulse signal generated by the second asynchronous controller in response to the request from the fourth asynchronous controller as a fifth clock signal, where the fifth clock signal is shifted by a second relative to the fourth clock signal a predetermined amount of time;

The electronic device also includes a clock assigning unit for assigning the second clock signal to the first clock group and assigning the fifth clock signal to a second clock group, the second clock group being different from the first clock grouping;

The clock propagation difference determining unit is further used for

determining a fifth clock propagation time period of the fourth clock signal and a fifth clock propagation time period of the fifth clock signal, the fifth clock propagation time period indicating that a fourth The time period from the input request to the fourth asynchronous controller generating the fourth pulse signal, the fifth clock propagation time period represents the time period from receiving the fourth input request to the second asynchronous controller from the fourth asynchronous controller the time period during which the controller generates the fifth pulse signal;

determining a fourth clock propagation difference between the fourth clock propagation period and the fifth clock propagation period;

The data propagation time period determination unit is further configured to determine a fourth data propagation time period between the fourth sequential logic device and the fifth sequential logic device, the fourth sequential logic device is coupled to the fourth asynchronous controller and operating based on the fourth pulse signal, the fifth sequential logic device coupled to the second asynchronous controller and operating based on the fifth pulse signal; and

The delay report generation unit is further configured to generate a delay report related to the fourth data propagation time period and the fourth clock propagation difference.