CN106096171A - Asynchronous circuit sequential inspection method based on static analysis - Google Patents
Asynchronous circuit sequential inspection method based on static analysis Download PDFInfo
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- CN106096171A CN106096171A CN201610455917.XA CN201610455917A CN106096171A CN 106096171 A CN106096171 A CN 106096171A CN 201610455917 A CN201610455917 A CN 201610455917A CN 106096171 A CN106096171 A CN 106096171A
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- information
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
Abstract
The present invention provides a kind of asynchronous circuit sequential inspection method based on static analysis.Described method includes: analyzes logical design file, sets up sequential chart；Read in temporal constraint file, described sequential chart sets up temporal constraint；Carry out sequential inspection；When sequential checks no abnormal situation, described sequential chart extract asynchronous timing path and is analyzed, calculating the delay information of asynchronous timing path；The delayed data of requirement on devices in delay information according to described asynchronous timing path and library file, calculates time sequence allowance information, judges user designs whether meet timing requirements according to described time sequence allowance information.The present invention can interpolate that whether asynchronous circuit sequence problem occurs, provides reference for IC designer, to ensure designing quality.
Description
Technical field
The present invention relates to programmable integrated circuit design field, particularly relate to a kind of asynchronous electricity based on static analysis
Road sequential inspection method.
Background technology
In the design process of integrated circuit, it usually needs the circuit designed is carried out the analysis in terms of sequential and inspection,
To guarantee to be designed to meet timing requirements.It is said that in general, sequential inspection can be divided into static check and dynamic chek two kinds.Dynamic
State inspection is to be imitated at EDA (Electronic Design Automation, electric design automation) by structure test vector
Carry out on true platform.This inspection degree of accuracy is higher, it is possible to verify function, but is limited by the emulation speed of EDA platform
Degree, checking process is the longest.Function is not emulated by static check, but by the method for exhaustion, uses the side of mathematical calculation
Formula replaces test vector, owing to without using EDA emulation platform, therefore checking speed and checking comprehensively.
At present, static timing analysis technology is used mainly the logic of Synchronization Design to be set up and the retention time
(setup/hold) inspection of aspect, does not analyzes asynchronous circuit.The actually design of asynchronous circuit is to be easier
Go wrong, if sequence problem occurs in asynchronous circuit, whole design unsuccessfully can be caused.
Summary of the invention
The asynchronous circuit sequential inspection method based on static analysis that the present invention provides, it is possible to judge whether asynchronous circuit goes out
Existing sequence problem, provides reference for IC designer, to ensure designing quality.
The present invention provides a kind of asynchronous circuit sequential inspection method based on static analysis, including:
Analyze logical design file, set up sequential chart；
Read in temporal constraint file, described sequential chart sets up temporal constraint；
Carry out sequential inspection；
When sequential checks no abnormal situation, described sequential chart extracts asynchronous timing path and is analyzed,
Calculate the delay information of asynchronous timing path；
The delayed data of requirement on devices in delay information according to described asynchronous timing path and library file, calculates sequential
According to described time sequence allowance information, balance information, judges whether user's design meets timing requirements.
Alternatively, described analysis logical design file, set up sequential chart and include: analyze net meter file and extract and sequential phase
The information closed, by the delay information reactionary slogan, anti-communist poster in timing sequence library to sequential chart.
Alternatively, described reading temporal constraint file, described sequential chart sets up temporal constraint and includes: set up sequential and divide
The necessary time constraints of analysis, sequential exception, input port postpone, output port postpones.
Alternatively, carry out sequential inspection described in include: check unconstrained pin information, combination loop.
Alternatively, described on described sequential chart, extract asynchronous timing path and be analyzed, calculating asynchronous timing path
Delay information include:
All possible timing path terminal in traversal sequential chart, determines that attribute is that asynchronous timing path terminal is as different
The terminal of step timing path, the opposite direction started along signal is propagated from the terminal of described asynchronous timing path scans for, and will search
Clock pins that rope arrives or input port are as the starting point of asynchronous timing path, and the starting point extracting described asynchronous timing path arrives
Path between the terminal of described asynchronous timing path is asynchronous timing path；
Using all cell delay in described asynchronous timing path and line delay sum as described asynchronous timing path
Delay information.
Alternatively, the time delay letter of requirement on devices in the described delay information according to described asynchronous timing path and library file
Breath, calculates time sequence allowance information and includes:
The delayed data that Recovery detects is deducted the delay information of described asynchronous timing path, obtains Recovery inspection
The time sequence allowance information surveyed；
The delay information of described asynchronous timing path is deducted the delayed data of Removal detection, obtains Removal detection
Time sequence allowance information.
Alternatively, the delayed data of described Recovery detection deducts in timing sequence library equal to the cycle information of clock
The Recovery time；
The delayed data of described Removal detection is equal to the Removal time in timing sequence library.
Alternatively, described judge whether user's design meets timing requirements and include according to described time sequence allowance information:
When described time sequence allowance information is less than zero, it is determined that user's design violates timing requirements；
When described time sequence allowance information is more than or equal to zero, it is determined that user's design meets timing requirements.
Alternatively, described method also includes: by the delay information of described asynchronous timing path, the time delay of Recovery detection
The delayed data of information, Removal detection, the time sequence allowance information of Recovery detection and the time sequence allowance of Removal detection
Information carries out display with report form and checks for user.
The asynchronous circuit sequential inspection method based on static analysis that the embodiment of the present invention provides, analyzes logical design literary composition
Part, sets up sequential chart, reads in temporal constraint file, sets up temporal constraint, when sequential inspection does not finds different on described sequential chart
During reason condition, described sequential chart extract asynchronous timing path and be analyzed, calculating the delay information of asynchronous timing path,
The delayed data of requirement on devices in delay information according to described asynchronous timing path and library file, calculates time sequence allowance letter
According to described time sequence allowance information, breath, judges whether user's design meets timing requirements.Compared with prior art, the present invention can
Asynchronous circuit is carried out sequential inspection, it is judged that whether asynchronous circuit sequence problem occurs, provides reference for IC designer,
To ensure that the asynchronous design of integrated circuit occurs without sequence problem, improve quality and the efficiency of design.
Accompanying drawing explanation
Fig. 1 is the flow chart of the asynchronous circuit sequential inspection method based on static analysis that the embodiment of the present invention improves；
The schematic diagram of the Removal time that Fig. 2 provides for the embodiment of the present invention；
The schematic diagram of the Recovery time that Fig. 3 provides for the embodiment of the present invention；
The typical asynchronous Time-Series analysis schematic diagram of one that Fig. 4 provides for the embodiment of the present invention.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
The present invention provides a kind of asynchronous circuit sequential inspection method based on static analysis, as it is shown in figure 1, described method bag
Include:
S11, analysis logical design file, set up sequential chart.
Specifically, analyze net meter file and extract the information relevant to sequential, the delay information reactionary slogan, anti-communist poster in timing sequence library is arrived
On sequential chart.Wherein, the described information relevant to sequential includes the information such as port port, pin foot, net, parameter.
Wherein, described logical design file and temporal constraint file are provided by user, and described timing sequence library is to provide device
The library file of the information such as time delay, is provided by manufacturer.
S12, reading temporal constraint file, set up temporal constraint on described sequential chart.
Specifically, set up time constraints necessary to Time-Series analysis, sequential exception, input port postpones, output port prolongs
Late etc..Wherein said sequential exception refers to not do the situation of Time-Series analysis.
S13, carry out sequential inspection.
Wherein, described sequential inspection includes checking unconstrained pin information, combination loop etc..
S14, when sequential checks no abnormal situation, described sequential chart extracts asynchronous timing path and carries out point
Analysis, calculates the delay information of asynchronous timing path.
Specifically, all possible timing path terminal in traversal sequential chart, determine that attribute is that asynchronous timing path is whole
Point as the terminal (endpoint) of asynchronous timing path, from the terminal of described asynchronous timing path start along signal propagate anti-
Direction scans for, using the clock pins searched or input port as the starting point of asynchronous timing path
(startpoint) starting point, extracting described asynchronous timing path is different to the path between the terminal of described asynchronous timing path
Step timing path；
Using all cell delay in described asynchronous timing path and line delay sum as described asynchronous timing path
Delay information (Arrive Time).
Alternatively, it is also possible to first using the clock pins searched or input port as the starting point of asynchronous timing path,
Then the direction that the starting point from described asynchronous timing path starts along signal is propagated scans for, and in traversal sequential chart, institute is likely
Timing path terminal, determine that attribute is the asynchronous timing path terminal terminal as asynchronous timing path, extract described different
The starting point of step timing path is asynchronous timing path to the path between the terminal of described asynchronous timing path.
S15, according to the delayed data of requirement on devices in the delay information of described asynchronous timing path and library file, calculate
According to described time sequence allowance information, time sequence allowance information, judges whether user's design meets timing requirements.
Specifically, the delayed data (Require Time) detected by Recovery (recovery) deducts described asynchronous sequential road
The delay information (Arrive Time) in footpath, obtains the time sequence allowance information of Recovery detection；By described asynchronous timing path
Delay information (Arrive Time) deducts the delayed data (Require Time) that Removal (withdrawing) detects, and obtains
The time sequence allowance information of Removal detection.
When described time sequence allowance information is less than zero, it is determined that user's design violates timing requirements；When described time sequence allowance is believed
Breath is more than or equal to zero, it is determined that user's design meets timing requirements.
Wherein, the delayed data of described Recovery detection deducts in timing sequence library equal to the cycle information of clock
The Recovery time；The delayed data of described Removal detection is equal to the Removal time in timing sequence library.
For asynchronous control signal, it is necessary first to prolonging between guarantee clock edge to the transition edges of asynchronous signal
There is the time of abundance late, this is because after normal work clock edge starts, timing unit can enter duty, if but
Now have asynchronous control signal, then timing unit enters asynchronous controlling state, and asynchronous control signal must assure that when signal controls
Between long enough without allowing timing unit be again introduced into normal operating conditions after asynchronous control signal discharges, thus ensure asynchronous
Controlling successfully, this is also referred to as the Removal time, as shown in Figure 2.Secondly asynchronous control signal is upon discharge, is still necessary to stay
There is enough time can recover normal in next time before work clock arrival by timing unit, after otherwise work clock arrives, sequential
Unit will be in unknown state thus cause timing unit operational failure, and this is also referred to as the Recovery time, as shown in Figure 3.
Further, after the step s 15, it is also possible to by the delay information (Arrive of described asynchronous timing path
Time), the delayed data (Require Time) of Recovery detection, the delayed data (Require of Removal detection
Time), the time sequence allowance information of Recovery detection and the time sequence allowance information of Removal detection show with report form
Check for user.
The asynchronous circuit sequential inspection method based on static analysis that the embodiment of the present invention provides, analyzes logical design literary composition
Part, sets up sequential chart, reads in temporal constraint file, sets up temporal constraint, when sequential inspection does not finds different on described sequential chart
During reason condition, described sequential chart extract asynchronous timing path and be analyzed, calculating the delay information of asynchronous timing path,
The delayed data of requirement on devices in delay information according to described asynchronous timing path and library file, calculates time sequence allowance letter
According to described time sequence allowance information, breath, judges whether user's design meets timing requirements.Compared with prior art, the present invention can
Asynchronous circuit is carried out sequential inspection, it is judged that whether asynchronous circuit sequence problem occurs, provides reference for IC designer,
To ensure that the asynchronous design of integrated circuit occurs without sequence problem, improve quality and the efficiency of design.
Being illustrated in figure 4 a kind of typical asynchronous Time-Series analysis situation, RS is the asynchronous reset control not controlled by clock CLK
Signal processed.Concrete, asynchronous circuit sequential inspection method based on static analysis based on Fig. 4 includes:
The first step, sets up sequential chart as shown in Figure 4, comprises only timing unit FF0, FF1, and corresponding pin in figure
The time sequence information such as foot, port, net.
Second step, sets up temporal constraint, can create a clock CLK here, this CLK must have the clock cycle (Cycle),
Clock port information.
3rd step, carries out sequential inspection, and check whether there is abnormal conditions (such as loop) need alarm.The present embodiment does not has
Abnormal conditions.
4th step, extracts timing path.In the present embodiment, the terminal of asynchronous timing path is RS, by passing along signal
The opposite direction search broadcast can find the starting point of timing path to be CK, thus has the asynchronous timing path of a CK-> RS.
5th step, when calculating delay information (the Arrive Time) of this asynchronous timing path, by CK-> delay of Q letter
The delay information in the intermediate combination path of breath and arrival RS carries out addition and obtains, as Fig. 4 indicates with arrow.
T_arr=T_ck2q+T_combine
The cycle time (Cycle) that delayed data (Require Time) is CLK of Recovery detection deducts timing sequence library
In the Recovery time:
T_req=T_cycle-T_recpvey
The time sequence allowance information Slack value of Recovery detection is equal to the delayed data (Require of Recovery detection
Time) the delay information (Arrive Time) of this asynchronous timing path is deducted:
T_slack=T_req-T_arr
The delayed data Require Time of Removal detection is the Removal time in timing sequence library:
T_req=T_removal
The time sequence allowance information Slack value of Removal detection is equal to the delay information (Arrive of this asynchronous timing path
Time) deduct Removal detection delayed data (Require Time):
T_slack=T_arr-T_req
If Slack is negative, showing that user designs and violate timing requirements, user needs to modify design；If
Slack is just, then show that user designs and meet timing requirements；If Slack is 0, then shows that user designs and be just met for requirement.
Removal and Recovery checks that result is shown to user by report form and checks, comprises asynchronous timing path letter in report
Breath, Arrive Time, Require Time and Slack information etc..
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any
Those familiar with the art in the technical scope that the invention discloses, the change that can readily occur in or replacement, all answer
Contain within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with scope of the claims.
Claims (9)
1. an asynchronous circuit sequential inspection method based on static analysis, it is characterised in that including:
Analyze logical design file, set up sequential chart；
Read in temporal constraint file, described sequential chart sets up temporal constraint；
Carry out sequential inspection；
When sequential checks no abnormal situation, described sequential chart extract asynchronous timing path and is analyzed, calculating
The delay information of asynchronous timing path；
The delayed data of requirement on devices in delay information according to described asynchronous timing path and library file, calculates time sequence allowance
According to described time sequence allowance information, information, judges whether user's design meets timing requirements.
Method the most according to claim 1, it is characterised in that described analysis logical design file, sets up sequential chart and includes:
Analyze net meter file and extract the information relevant to sequential, by the delay information reactionary slogan, anti-communist poster in timing sequence library to sequential chart.
Method the most according to claim 1, it is characterised in that described reading temporal constraint file, on described sequential chart
Set up temporal constraint to include: set up time constraints necessary to Time-Series analysis, sequential exception, input port delay, output port
Postpone.
Method the most according to claim 1, it is characterised in that described in carry out sequential inspection and include: check unconstrained pipe
Foot information, combination loop.
Method the most according to claim 1, it is characterised in that described extract asynchronous timing path also on described sequential chart
Being analyzed, the delay information calculating asynchronous timing path includes:
All possible timing path terminal in traversal sequential chart, determines that attribute is that asynchronous timing path terminal is as time asynchronous
The terminal in sequence path, the opposite direction started along signal is propagated from the terminal of described asynchronous timing path scans for, and will search
Clock pins or input port as the starting point of asynchronous timing path, extract the starting point of described asynchronous timing path to described
Path between the terminal of asynchronous timing path is asynchronous timing path；
Using all cell delay in described asynchronous timing path and line delay sum as the delay of described asynchronous timing path
Information.
Method the most according to claim 5, it is characterised in that the described delay information according to described asynchronous timing path with
And the delayed data of requirement on devices in library file, calculate time sequence allowance information and include:
The delayed data that Recovery (recovery) detects is deducted the delay information of described asynchronous timing path, obtains Recovery
The time sequence allowance information of detection；
The delay information of described asynchronous timing path is deducted the delayed data that Removal (withdrawing) detects, obtains Removal inspection
The time sequence allowance information surveyed.
Method the most according to claim 6, it is characterised in that the delayed data of described Recovery detection is equal to clock
Cycle information deducts the Recovery time in timing sequence library；
The delayed data of described Removal detection is equal to the Removal time in timing sequence library.
Method the most according to claim 7, it is characterised in that described judge that user designs according to described time sequence allowance information
Whether meet timing requirements to include:
When described time sequence allowance information is less than zero, it is determined that user's design violates timing requirements；
When described time sequence allowance information is more than or equal to zero, it is determined that user's design meets timing requirements.
Method the most according to claim 1, it is characterised in that described method also includes: by described asynchronous timing path
The delayed data of information, Recovery detection, the delayed data of Removal detection, the time sequence allowance information of Recovery detection
Carry out display with the time sequence allowance information of Removal detection with report form to check for user.
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| CN114742001A (en) * | 2022-03-16 | 2022-07-12 | 南京邮电大学 | System static time sequence analysis method based on multiple FPGAs |
| CN115048889A (en) * | 2022-08-16 | 2022-09-13 | 井芯微电子技术(天津)有限公司 | Asynchronous path extraction method and system based on back-end time sequence convergence simulation |
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| CN106682285A (en) * | 2016-12-09 | 2017-05-17 | 深圳市紫光同创电子有限公司 | Static timing analysis method and device |
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| CN110619132A (en) * | 2018-06-20 | 2019-12-27 | 瑞昱半导体股份有限公司 | Method and apparatus for adaptive voltage scaling |
| CN110619132B (en) * | 2018-06-20 | 2023-11-24 | 瑞昱半导体股份有限公司 | Method and apparatus for adaptive voltage scaling |
| CN109901049B (en) * | 2019-01-29 | 2021-05-04 | 厦门码灵半导体技术有限公司 | Method and device for detecting asynchronous path in time sequence path for integrated circuit |
| CN109901049A (en) * | 2019-01-29 | 2019-06-18 | 厦门码灵半导体技术有限公司 | Detect the method, apparatus of asynchronous paths in integrated circuit timing path |
| CN112069752A (en) * | 2020-09-29 | 2020-12-11 | 上海兆芯集成电路有限公司 | Static timing analysis method and device |
| CN112069752B (en) * | 2020-09-29 | 2022-09-27 | 上海兆芯集成电路有限公司 | Static timing analysis method and device |
| CN112241615B (en) * | 2020-10-09 | 2021-05-18 | 广芯微电子（广州）股份有限公司 | Method and system for detecting data balance time sequence and electronic equipment |
| CN112241615A (en) * | 2020-10-09 | 2021-01-19 | 广芯微电子（广州）股份有限公司 | Method and system for detecting data balance time sequence and electronic equipment |
| CN112613262A (en) * | 2020-12-14 | 2021-04-06 | 海光信息技术股份有限公司 | Method and device for rapidly verifying IP (Internet protocol) critical path time sequence and electronic equipment |
| CN112613262B (en) * | 2020-12-14 | 2023-03-24 | 海光信息技术股份有限公司 | Method and device for rapidly verifying IP (Internet protocol) critical path time sequence and electronic equipment |
| CN112685982A (en) * | 2020-12-31 | 2021-04-20 | 海光信息技术股份有限公司 | Circuit detection method, circuit detection device, storage medium and electronic equipment |
| WO2023279341A1 (en) * | 2021-07-08 | 2023-01-12 | 华为技术有限公司 | Method for designing asynchronous circuit, and electronic device |
| CN114742001A (en) * | 2022-03-16 | 2022-07-12 | 南京邮电大学 | System static time sequence analysis method based on multiple FPGAs |
| CN114742001B (en) * | 2022-03-16 | 2023-08-29 | 南京邮电大学 | System static time sequence analysis method based on multiple FPGA |
| CN115048889A (en) * | 2022-08-16 | 2022-09-13 | 井芯微电子技术(天津)有限公司 | Asynchronous path extraction method and system based on back-end time sequence convergence simulation |
| CN115048889B (en) * | 2022-08-16 | 2022-11-01 | 井芯微电子技术(天津)有限公司 | Asynchronous path extraction method and system based on back-end time sequence convergence simulation |
| CN115544929A (en) * | 2022-11-30 | 2022-12-30 | 中科亿海微电子科技（苏州）有限公司 | Method and device for testing path time sequence delay in FPGA EDA software |
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