CN110619132B - Method and apparatus for adaptive voltage scaling - Google Patents
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Abstract
The invention provides a method and a device for adaptive voltage scaling. The method may comprise: reading a circuit simulation network list description file, a circuit design database and a path list; establishing a delay variation database of each minimum unit of the plurality of minimum units of the overall design under a plurality of voltage levels according to the circuit design database; applying an initial voltage level to the overall design, and performing static timing analysis of the overall design to determine whether a timing violation path exists in the path list; and selectively adjusting the voltage level of the driving voltage and re-performing the static timing analysis until no timing violation path exists according to whether the timing violation path exists.
Description
Technical Field
The present invention relates to adaptive voltage scaling, and more particularly, to a method and apparatus for adaptive voltage scaling to eliminate delay variation of an overall design.
Background
In recent years, due to the development of semiconductor process technology, the process variation information provided by the wafer factory helps system developers to perform high-yield system design at the front end. However, the types of components, sizes of components, and operating voltages used in different blocks of the system design may vary depending on the respective design considerations, and the amount of variation may also vary. In addition, if global variation (global variation) and local variation (local variation) are taken into consideration, the conventional corner analysis method cannot accurately determine the variation (too optimistic or too pessimistic) in the system design, so that the yield cannot be increased, and thus, unavoidable additional costs are introduced. Therefore, a novel method is needed to accurately predict the variation of the system design to eliminate the variation of the system design without side effects or less likely to cause side effects.
Disclosure of Invention
It is therefore an objective of the claimed invention to provide a method for adaptive voltage scaling to eliminate delay variations of a complete design and a corresponding analysis device for solving the above-mentioned problems.
It is another object of the present invention to provide a method for adaptive voltage scaling to eliminate delay variations of a complete design and a corresponding analysis apparatus to eliminate variations of the system design without side effects or less likely to cause side effects.
At least one embodiment of the present invention provides a method for adaptive voltage scaling to eliminate delay variations of an overall design. The method comprises the following steps: reading a circuit simulation network list description file (circuit simulation netlist file), a circuit design database, and a path list (path list), wherein the circuit simulation network list description file indicates component information of the overall design, and the path list indicates path information of the overall design; building a delay variation database of each minimum unit of the overall design at a plurality of (variable) voltage levels according to the circuit design database; applying an initial voltage level to the global design using the initial voltage level as a voltage level of a driving voltage of the global design, and performing static timing analysis (static timing analysis, STA) of the global design based on the delay variation database to determine whether at least one timing violation path exists in the path list (timing violation path); and selectively (selectively) adjusting the voltage level of the driving voltage and re-performing the static timing analysis until no timing violation path exists according to whether the at least one timing violation path exists.
At least one embodiment of the present invention provides an analysis device that operates according to the above-described method. The analysis device may include a processing circuit for executing a set of program code corresponding to the method to control the analysis device to operate according to the method.
One of the benefits of the present invention is that the present invention can analyze the delay variation of the complete design with high accuracy and find an adaptive voltage level to eliminate the delay variation, so as to improve the yield. In addition, implementation according to related embodiments of the present invention does not add much extra cost. Accordingly, the problems of the related art can be solved without increasing the overall cost too much. Compared with the related art, the invention can accurately analyze the delay variation of the complete design without side effects or less possibility of side effects, and eliminate the variation of the system design to improve the yield.
Drawings
FIG. 1 is a schematic diagram of an overall design and voltage supply according to an embodiment of the invention.
FIG. 2 is a schematic diagram of an overall design and voltage supply according to another embodiment of the invention.
FIG. 3 is a flow chart of the method in another embodiment of the invention.
FIG. 4 is a schematic diagram of an analysis apparatus according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention provide a method and apparatus (hereinafter, simply referred to as the method and apparatus, respectively) for adaptive voltage scaling to eliminate delay variations of an overall design. Based on at least one of the control schemes of the method (such as the control schemes of the embodiments shown in fig. 1 and 2), the device can solve the problems of variation and the like and can improve the yield.
Fig. 1 is a schematic diagram of a global design 10 and a voltage supply 100 according to an embodiment of the invention, wherein the global design 10 may represent a circuit architecture of an integrated circuit, but the invention is not limited thereto. The overall design 10 may include a plurality of minimum cells, which in this embodiment may be implemented by a plurality of flip-flops FF 1 ～FF N Such as flip-flop { FF } 1 ,FF 2 ,FF 3 ,FF 4 ,FF 5 ,…,FF N-3 ,FF N-2 ,FF N-1 ,FF N A network (N is a positive integer greater than one) formed by coupling the above-mentioned two circuits, in which several triggers are implementedFF 1 ～FF N Each of which is coupled to a voltage supply 100 capable of providing a driving voltage. This is for illustration purposes only and is not a limitation of the present invention (e.g., each of the plurality of minimum cells may be replaced with any of a variety of other types of logic circuit cells, and two of the plurality of minimum cells may be different from each other).
In the present embodiment, a circuit emulation network manifest description file (circuit simulation netlist file) may be generated and indicate component information (e.g., flip-Flop (FF) FF of the overall design 10 1 ～FF N Each of which has a respective input and output). In addition, a path list (path list) may indicate path information for at least a portion (a portion or all) of the overall design 10, such as: the path list may include at least one path in the overall design 10, such as through flip-flop FF 1 FF (FF) 2 PATH of (a) 1 . In the present embodiment, except for the pass flip-flop FF 1 FF (FF) 2 PATH of (a) PATH 1 The path list may further include a pass flip-flop FF 3 FF (FF) 4 PATH of (a) 2 …, pass flip-flop FF N-3 FF (FF) N-2 PATH of (a) M-1 And through flip-flop FF N-3 FF (FF) N-1 PATH of (a) M Etc. (M may be a positive integer), but the present invention is not limited thereto.
In the present embodiment, the plurality of minimum units (such as a plurality of flip-flops FF 1 ～FF N ) The delay variation database for each of the plurality of voltage levels may be built up from a circuit design database. For example: the circuit design database may include process information provided by the wafer mill, specification requirements, and resistance capacitance information in the overall design 10, where the process information may include each minimum cell (such as a plurality of flip-flops FF 1 ～FF N ) The circuit features (e.g.: component characteristics such as process variations). In this embodiment, the device (e.g., it) transmits through statistical methods (e.g., monte Carlo methods)A processing circuit within) may build the delay variation database, such as a mapping table, based on the process information. In particular, for each minimum unit of the overall design 10, the apparatus (e.g. the processing circuit) may determine a delay variation of each minimum unit corresponding to a certain voltage level of the driving voltage by a table mapping method, but the invention is not limited thereto.
The device (e.g., the processing circuit) may then utilize an initial voltage level as a voltage level of the voltage supply 100 coupled to the global design 10 to apply the initial voltage level to the global design 10, and perform static timing analysis (static timing analysis, STA) of the global design 10 based on the delay variation database to determine the PATH { PATH in the PATH list 1 ,PATH 2 ,…,PATH M-1 ,PATH M Whether at least one timing violation path exists (timing violation path), wherein the at least one timing violation path may include (but is not limited to): delay the path that is not within the allowable range of the delay specification requirement.
For example: assuming that the allowable range of the delay specification is set to be within 5% of the delay specification (e.g., 1 ns), the PATH 1 The delay is 1.06ns (i.e. positive 6% error), and the PATH is determined 1 Is a timing violation path. Also for example: assuming that the allowable range of the delay specification is set to be within 5% of the delay specification (e.g., 1 ns), the PATH 1 The PATH is determined when the delay is 0.94ns (i.e., minus 6% error) 1 For the timing violation path. As another example: assuming that the allowable range of the delay specification is set to be within 5% of the delay specification (e.g., 1 ns), the PATH 1 The PATH is determined if the delay is 1.04ns (i.e. positive 4% error) 1 Not a timing violation path.
In addition, the device (e.g., the processing circuit) may selectively (selectively) adjust the voltage level of the driving voltage and re-perform the static timing analysis until no timing violation path exists, depending on whether the at least one timing violation path exists. For example: carry out the first stepAfter a static timing analysis, the timing violation PATH (e.g., PATH) exists in the PATH list 1 Path PATH 2 ) After adjusting the voltage level of the driving voltage to be different from the initial voltage level (for example: 0.9V) of the first voltage level (e.g.: 0.91V) and performing a second static timing analysis, the device (e.g., the processing circuitry) may determine that the timing violation path has been eliminated, the second voltage level (e.g.: 0.91V) can be used as the voltage level of the adaptive voltage that meets the delay specification requirements of the overall design 10. Also for example: after the first static timing analysis, the timing violation PATH (e.g., PATH) exists in the PATH list 1 Path PATH 2 ) After adjusting the voltage level of the driving voltage to be different from the initial voltage level (for example: 0.9V) of the first voltage level (e.g.: 0.91V) and performing a second static timing analysis, the timing violation path still exists in the path list (e.g.: path PATH 1 ) However, after adjusting the voltage level of the driving voltage to be different from the initial voltage level (for example: 0.9V) and the second voltage level (e.g.: after a third voltage level (0.92V) of 0.91V and performing a second static timing analysis, the device (e.g., the processing circuitry) may determine that the timing violation path has been eliminated, the third voltage level (e.g.: 0.92V) can be used as the voltage level of the adaptive voltage that meets the delay specification requirements of the overall design 10. As in the example above, when the timing violation path exists in the path list, the device (e.g., the processing circuit) may adjust the voltage level multiple times and perform the static timing analysis operation until no timing violation path exists. As another example: after performing the first static timing analysis, the timing violation path is not present in the path list, and the device (e.g., the processing circuit) may determine that the initial voltage level (e.g., 0.9V) may be used as the voltage level of the adaptive voltage that meets the delay specification requirements of the overall design 10, but the invention is not limited thereto.
In addition, after finding the voltage level of the driving voltage (such as the voltage level of the adaptive voltage described above) that meets the delay specification requirements of the overall design 10, the device (e.g., the processing circuit) may be verified using a circuit simulator that has transistor-level simulation capabilities (e.g., transistor-level simulation capability) to ensure the accuracy of the voltage level of the driving voltage (e.g., a simulation result of the circuit simulator is consistent with or similar to an analysis result of the static timing analysis described above).
Fig. 2 is a schematic diagram of a global design 20 and a voltage supply 100 according to another embodiment of the invention, wherein the global design 20 may represent a circuit architecture of an integrated circuit, but the invention is not limited thereto. The architecture of the global design 20 shown in FIG. 2 is based on the architecture of the global design 10 shown in FIG. 1, the main difference between the global design 20 and the global design 10 is that a plurality of flip-flops FF 1 ～FF N Each of which is coupled to the flip-flop { FF over a respective resistor (such as 1 ,FF 2 ,FF 3 ,FF 4 ,FF 5 ,…,FF N-3 ,FF N-2 ,FF N-1 ,FF N Resistors { R } p,1 ,R p,2 ,R p,3 ,R p,4 ,R p,5 ,…,R p,N-3 ,R p,N-2 ,R p,N-1 ,R p,N }) is coupled to the voltage supply 100, resulting in a plurality of flip-flops FF for driving 1 ～FF N The respective equivalent voltage levels of the driving voltages of each of (such as corresponding to the flip-flops { FF }, respectively 1 ,FF 2 ,FF 3 ,FF 4 ,FF 5 ,…,FF N-3 ,FF N-2 ,FF N-1 ,FF N Equivalent voltage level { V } eff,1 ,V eff,2 ,V eff,3 ,V eff,4 ,V eff,5 ,…,V eff,N-3 ,V eff,N-2 ,V eff,N-1 ,V eff,N }) is different from the voltage level supplied by the voltage supply 100 (e.g.: the equivalent voltage level is lower than the voltage level supplied by the voltage supply 100) for driving the flip-flops FF 1 ～FF N The respective equivalent voltage level of the driving voltage of each of (e.g., equivalent voltage level V eff,1 ) Can be achieved by coupling to the minimum unit (e.g.: flip-flop FF 1 ) Is a resistor (for example: resistor R p,1 ) And the resistance of the resistor may be determined by the minimum cell (e.g.: flip-flop FF 1 ) The physical layout (physical layout) in the overall design 20 is determined, but the present invention is not limited thereto. Similarly, equivalent voltage level { V eff,2 ,V eff,3 ,V eff,4 ,V eff,5 ,…,V eff,N-3 ,V eff,N-2 ,V eff,N-1 ,V eff,N All of the above-mentioned steps may be determined in a similar manner, and details thereof are not described herein for brevity.
In this embodiment, according to the physical layout of the overall design 20 shown in fig. 2, the device (e.g., the processing circuit) can generate current-resistance drop (IR drop) information of the overall design 20, and the IR drop information can include the information corresponding to the flip-flops { FF }, respectively, in the above embodiment 1 ,FF 2 ,FF 3 ,FF 4 ,FF 5 ,…,FF N-3 ,FF N-2 ,FF N-1 ,FF N Equivalent voltage level { V } eff,1 ,V eff,2 ,V eff,3 ,V eff,4 ,V eff,5 ,…,V eff,N-3 ,V eff,N-2 ,V eff,N-1 ,V eff,N }. Based on the current-to-resistance-drop information, the device (e.g., the processing circuit) may determine an equivalent voltage level applied to each of the minimum cells and determine a delay variation corresponding to each of the minimum cells based on the equivalent voltage level. For example: when the voltage supply 100 supplies a voltage level (e.g., 1V), the device (e.g., the processing circuit) can determine to drive the flip-flop FF according to the current-resistance-drop information 1 Is equivalent to the voltage level (e.g., 0.95V) and can determine flip-flop FF according to the delay variation database 1 The delay variation at the equivalent voltage level is operated for subsequent steps (such as static timing analysis and adaptive voltage scaling as described above). Similar matters of these embodiments to those of the previous embodiments are not repeated here.
FIG. 3 is a workflow of the method in another embodiment of the invention. For illustrative purposes, the workflow shown in FIG. 3 is described with reference to the overall design 20 shown in FIG. 2, but the invention is not so limited. The method can be summarized as follows through the workflow shown in FIG. 3.
Step S1: the apparatus (e.g., the processing circuit) may read a circuit simulation network list description file, a circuit design database, a path list, and current-to-resistance-voltage-drop information.
Step S2: the device (e.g., the processing circuit) may build up a plurality of minimum cells (such as flip-flops FF) of the overall design 20 from the circuit design database 1 ～FF N ) A database of delay variations for each minimum cell at a plurality of (variable) voltage levels.
Step S3: the device (e.g., the processing circuit) may utilize an initial voltage level (e.g., 1V) as a voltage level of a driving voltage of the overall design 20 and determine each of a plurality of minimum cells (e.g., flip-flops FF) applied to the overall design 20 based on the current-resistance-voltage-drop information, respectively 1 ) The respective equivalent voltage levels (e.g.: 0.95V) to apply the equivalent voltage levels to each minimum cell in the overall design 20, respectively, and to perform static timing analysis of the overall design 20 based on the delay variation database.
Step S4: the device (e.g. the processing circuit) may determine whether at least one timing violation path exists in the path list according to an analysis result of the static timing analysis performed in step S3. When the at least one timing violation PATH (e.g., PATH) exists in the PATH list 1 Path PATH 2 ) Step S5 is entered; otherwise, step S7 is entered.
Step S5: the device (e.g., the processing circuit) may adjust the voltage level of the driving voltage to another voltage level (e.g., 1.01V), and determine a respective equivalent voltage level (e.g., 0.96) for each of a plurality of minimum cells of the overall design 20 based on the current-to-resistance-voltage drop information, respectively, to apply the equivalent voltage level to each minimum cell of the overall design 20, respectively, and re-perform the static timing analysis.
Step S6: the device (e.g. the processing circuit) may rely on the quiescence performed in step S5And judging whether at least one timing violation path exists in the path list according to an analysis result of the state timing analysis. When the at least one timing violation PATH (e.g., PATH) exists in the PATH list 1 ) Step S5 is entered; otherwise, step S7 is entered.
Step S7: the device (e.g., the processing circuit) may be verified using a circuit simulator that has transistor-level simulation capabilities to ensure the accuracy of the voltage level of the drive voltage.
It should be noted that one or more steps may be modified, added or deleted in the workflow as long as the implementation of the invention is not hindered. Since one skilled in the art will understand the operation of each step shown in fig. 3 after reading the above paragraphs directed to fig. 1 and 2, the details are not repeated here for brevity.
Fig. 4 is a schematic diagram of an analysis apparatus 400 according to an embodiment of the present invention, wherein the analysis apparatus 400 is used as an example of the apparatus. In this embodiment, the method (e.g., the workflow shown in FIG. 3) may be applied to the analysis device 400. The analysis device 400 may include a processing circuit 410 (which may include at least one processor, memory, chipset, bus …, etc.) and at least one storage device 420 (e.g., one or more hard drives, and/or one or more solid state drives). In particular, the processing circuit 410 may be configured to execute a set of program codes 412 corresponding to the method to control the analysis device 400 to operate according to the method (e.g. the workflow shown in fig. 3), wherein the set of program codes 412 may be implemented as an application program, and the storage device 420 may store the circuit simulation network list description file, the circuit design database, the path list, the current resistance drop information, etc. read by the analysis device 400 in the step S1, and store the delay variation database established by the analysis device 400 in the step S2 for subsequent analysis, but the invention is not limited thereto. Examples of the analysis device 400 may include (but are not limited to): personal computers and servers.
Compared with the traditional design method and corner analysis (corner analysis) method, the method and the device can accurately judge the delay variation of the overall design (the delay variation of the signal path in the overall design) on the premise of not changing the circuit architecture in the overall design, and quickly eliminate the delay variation of the overall design in an adaptive voltage scaling mode, thereby avoiding risks and costs possibly caused by other modes (such as modification of the circuit architecture).
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Symbol description
10,20 overall design
100. Voltage supply device
400. Analysis device
410. Processing circuit
412. Program code
420. Storage device
S1,S2,S3,S4,
S5, S6, S7 step
PATH 1 ,PATH 2 ,…,
PATH M-1 ,PATH M Path
FF 1 ,FF 2, FF 3 ,FF 4 ,FF 5 ,…,
FF N-3 ,FF N-2 ,FF N-1 ,FF N Trigger device
R p,1 ,R p,2 ,R p,3 ,R p,4 ,R p,5 ,…,
R p,N-3 ,R p,N-2 ,R p,N-1 ,R p,N Resistor
V eff,1 ,V eff,2 ,V eff,3 ,V eff,4 ,V eff,5 ,…,
V eff,N-3 ,V eff,N-2 ,V eff,N-1 ,V eff,N Equivalent voltage level.
Claims (6)
1. A method for adaptive voltage scaling to eliminate delay variation of an overall design, the method comprising:
reading a circuit simulation network list description file, a circuit design database, a path list and current resistance voltage drop information, wherein the circuit simulation network list description file indicates the component information of the overall design, and the path list indicates the path information of the overall design;
establishing a delay variation database of each minimum unit in the plurality of minimum units of the overall design under various voltage levels according to the circuit design database, wherein the circuit design database comprises circuit characteristics, specification requirements and resistance-capacitance information of each minimum unit in the overall design;
applying an initial voltage level to the overall design by using the initial voltage level as a voltage level of a driving voltage of the overall design, and performing static timing analysis of the overall design according to the delay variation database to determine whether at least one timing violation path exists in the path list;
selectively adjusting the voltage level of the driving voltage and re-performing the static timing analysis until no timing violation path exists, based on whether the at least one timing violation path exists, without affecting the circuit architecture in the overall design; and
verifying with a circuit simulator to ensure that a simulation result of the circuit simulator is consistent with an analysis result of the static timing analysis, wherein the circuit simulator has transistor-level simulation capability, wherein,
determining respective equivalent operating voltage levels applied to the each minimum cell of the overall design according to the current-to-resistance voltage drop information to apply the equivalent operating voltage levels to the each minimum cell of the overall design, and determining delay variations corresponding to the each minimum cell according to the equivalent operating voltage levels.
2. The method of claim 1, wherein selectively adjusting the voltage level of the driving voltage and re-performing the static timing analysis until no timing violation path exists according to whether the at least one timing violation path exists further comprises:
when the at least one timing violation path exists in the path list, adjusting the voltage level of the driving voltage to another voltage level different from the initial voltage level, and carrying out the static timing analysis again to judge whether the timing violation path is eliminated; otherwise, the voltage level of the driving voltage is not adjusted and the static timing analysis is not performed again.
3. The method of claim 1, wherein selectively adjusting the voltage level of the driving voltage and re-performing the static timing analysis until no timing violation path exists according to whether the at least one timing violation path exists further comprises:
when the at least one timing violation path exists in the path list, the voltage level of the driving voltage is adjusted for multiple times and the static timing analysis is performed again until no timing violation path exists.
4. The method of claim 1, wherein the path list includes at least one path in the overall design.
5. The method of claim 1, wherein the overall design represents a circuit architecture of an integrated circuit.
6. An analysis device operating in accordance with the method of claim 1, the analysis device comprising:
a processing circuit for executing a set of program codes corresponding to the method to control the analysis device to operate according to the method.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7551985B1 (en) * | 2006-10-30 | 2009-06-23 | Cadence Design Systems, Inc. | Method and apparatus for power consumption optimization for integrated circuits |
| CN101765822A (en) * | 2007-07-26 | 2010-06-30 | 高通股份有限公司 | Method and apparatus for adaptive voltage scaling based on instruction usage |
| US8788995B1 (en) * | 2013-03-15 | 2014-07-22 | Cadence Design Systems, Inc. | System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design |
| TW201602819A (en) * | 2014-06-18 | 2016-01-16 | Ａｒｍ股份有限公司 | Method for adjusting a timing derate for static timing analysis |
| CN106096171A (en) * | 2016-06-22 | 2016-11-09 | 深圳市紫光同创电子有限公司 | Asynchronous circuit sequential inspection method based on static analysis |
Family Cites Families (2)
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| JP2009237972A (en) * | 2008-03-27 | 2009-10-15 | Fujitsu Microelectronics Ltd | Semiconductor device, and designing method and designing apparatus thereof |
| US8832616B2 (en) * | 2011-03-18 | 2014-09-09 | Sage Software, Inc. | Voltage drop effect on static timing analysis for multi-phase sequential circuit |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7551985B1 (en) * | 2006-10-30 | 2009-06-23 | Cadence Design Systems, Inc. | Method and apparatus for power consumption optimization for integrated circuits |
| CN101765822A (en) * | 2007-07-26 | 2010-06-30 | 高通股份有限公司 | Method and apparatus for adaptive voltage scaling based on instruction usage |
| US8788995B1 (en) * | 2013-03-15 | 2014-07-22 | Cadence Design Systems, Inc. | System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design |
| TW201602819A (en) * | 2014-06-18 | 2016-01-16 | Ａｒｍ股份有限公司 | Method for adjusting a timing derate for static timing analysis |
| CN106096171A (en) * | 2016-06-22 | 2016-11-09 | 深圳市紫光同创电子有限公司 | Asynchronous circuit sequential inspection method based on static analysis |
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