CN115544929A - Method and device for testing path time sequence delay in FPGA EDA software - Google Patents
Method and device for testing path time sequence delay in FPGA EDA software Download PDFInfo
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Abstract
The invention provides a method and a device for testing path time delay in FPGA EDA software, which are characterized in that a time sequence model file, a chip structure file, a netlist file and a wiring file are obtained and analyzed to calculate the logic delay and the path delay of each time sequence path in the time sequence model file, a time sequence report file is obtained and analyzed to find out the logic delay and the path delay of each time sequence path in the time sequence report file, and finally the logic delay and the path delay calculated by each time sequence path are compared with the logic delay and the path delay of the corresponding time sequence path obtained from a time sequence report to obtain a comparison result and output the comparison result. The invention can quickly verify which timing sequence path is wrong and discover bugs in time, thereby improving the testing efficiency of the FPGA EDA software.
Description
Technical Field
The invention belongs to the field of software testing of a programmable logic device FPGA EDA, and particularly relates to a method and a device for testing path time sequence delay in FPGA EDA software.
Background
The FPGA EDA software is an automatic tool for designing electronic circuits, and has the main functions of converting circuit designs into netlist files, and then performing a series of flow processes such as packaging, layout, wiring, code generation and the like on the netlist files. After wiring, each timing path has logic delay and path delay, the timing paths are usually very many, EDA software processes the logic delay to each port of each module and the path delay passed by each mux, and a tester needs to check whether the delay of each timing path is calculated correctly through a certain rule and a timing model one by one, which is very expensive. If the test method for automatically verifying the time sequence delay is used, the test efficiency of testers can be greatly improved, and the test time can be effectively shortened.
Disclosure of Invention
The invention aims to solve the technical problem of how to test time sequence delay by using a software test technology, and provides a method and a device for testing path time sequence delay in FPGA EDA software.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a method for testing path time sequence delay in FPGA EDA software comprises the following steps:
step 1: acquiring and analyzing a time sequence model file, a chip structure file, a netlist file and a wiring file, and calculating the logic delay and the path delay of each time sequence path in the time sequence model file according to the relationship among modules in each file;
step 2: acquiring and analyzing a time sequence report file, and finding out the logic delay and the path delay of each time sequence path in the time sequence report file;
and step 3: and (3) comparing the logic delay and the path delay calculated by each time sequence path in the step (1) with the logic delay and the path delay of the corresponding time sequence path obtained from the time sequence report in the step (2) to obtain a comparison result and outputting the comparison result.
Further, the method for calculating the logic delay and the path delay of each timing path in the timing model file in step 1 is as follows:
step 1.1: analyzing the time sequence model file to obtain each module, channel delay corresponding to each module, delay, establishing time and holding time of each module port, and generating a time _ mode _ fact of a time sequence model dictionary;
step 1.2: analyzing the chip structure file to obtain coordinate positions of all chips and module names corresponding to each coordinate position, and generating a table _ mux _ dit for storing a module position dictionary;
step 1.3: analyzing the netlist file to obtain all module cells in the netlist, all ports under each module cell and signals passing through all the ports, and generating a module port signal dictionary cell _ fact;
step 1.4: analyzing the wiring file to obtain a source point, a path and a sink point which are passed by each signal, and generating a signal dictionary route _ dit, wherein each source point, path and sink point comprise a coordinate position and a port name;
step 1.5: calculating logic delay: obtaining a time sequence path list in a time sequence report, finding out a path node of a logic delay type, determining a module cell and a port of a first time sequence path node passed by the time sequence path as an input port dstPort1 in a dictionary time _ mode _ dit, then viewing an output port of the module along the time sequence path as a startPort1, finding out the delay of the module port from a module cell, the ports dstPort1 and the startPort1 corresponding to the time sequence model dictionary time _ mode _ dit, and repeating the steps to find out all logic delays in the time sequence path for accumulation;
step 1.6: calculating path delay: finding out the path node of the path delay type in the time sequence path list, obtaining the module cell, the port and the module position location passed by the time sequence path from the path node of the first path delay type, obtaining the signal name passed by the port from the module cell and the port in the module port signal dictionary cell _ dit according to the module cell and the port, wherein the module cell and the port are signal starting points source, and finding out the module name cell, the port and the position location of the next path node of the path delay type from the time sequence path list, the path node is an end point sink, all channels chan passed by the path are found out from a signal dictionary route _ fact according to the signal name, the start point source and the end point sink, all position locations passed by the path are found out according to the channels chan, a module name module _ name is obtained from a module position dictionary table _ mux _ fact according to the position locations, the time delay corresponding to the corresponding module _ name is found out from a time sequence model dictionary time _ module _ fact according to the module name module _ name and is used as the path delay, and all path delays in the time sequence path are found out in sequence and accumulated.
Further, the method for finding out the logic delay and the path delay of each timing path in the timing report file in step 2 is as follows:
acquiring a time sequence report file to obtain all time sequence paths, and storing all the time sequence paths in a time sequence path dictionary path _ fact; the time sequence path dictionary path _ dct includes all time sequence paths under various time sequence path types, all module cells, ports and delays passed by the time sequence path are listed in each time sequence path, delays of the same delay type in the time sequence path are added to obtain path delay and logic delay, and the path delay and the logic delay are added to obtain total delay.
Further, the time sequence path dictionary path _ fact further includes a delay of a start clock, a data delay and a delay of an end clock, where the data delay includes a logic delay and a path delay.
Further, the sequential path types include a simultaneous clock setup path, a simultaneous clock hold path, a cross-clock setup path, a cross-clock hold path, an asynchronous setup path, and an asynchronous hold path.
Further, the calculation of the end point clock delay is to calculate the delay from the clock to the end point register, find out the corresponding module name and the corresponding setup time or hold time of the port from the time _ mode _ dit of the time sequence model dictionary according to the end point module name and the port name of the register, and sum up to obtain the end point clock delay.
Further, calculating the start clock delay is to calculate the delay from the clock to the start register, find out the corresponding module name and the delay corresponding to the port from the time _ mode _ fact of the time sequence model dictionary according to the start module name and the port name of the register, and sum up to obtain the start clock delay.
Further, when calculating the logic delay of the sequential path, if the path is a setup type path, the delay of t _ su needs to be subtracted from the time of all logic delays, and if the path is a hold type path, the delay of t _ h needs to be added to the time of all logic delays.
The invention also provides a device for testing the path time sequence delay in the FPGA EDA software, which comprises the following modules:
and an actual calculation delay module: the system comprises a time sequence model file, a chip structure file, a netlist file and a wiring file, wherein the time sequence model file, the chip structure file, the netlist file and the wiring file are obtained and analyzed, and the logic delay and the path delay of each time sequence path in the time sequence model file are calculated according to the relation among modules in each file;
the time sequence report delay calculation module: the time sequence report file is used for acquiring and analyzing the time sequence report file, and the logic delay and the path delay of each time sequence path in the time sequence report file are found out;
a judging module: and the logic delay and the path delay calculated by each time sequence path in the actual calculation delay module are compared with the logic delay and the path delay of the corresponding time sequence path obtained from the time sequence report in the time sequence report delay calculation module to obtain a comparison result and output the comparison result.
By adopting the technical scheme, the invention has the following beneficial effects:
according to the method and the device for testing the path time sequence delay in the FPGA EDA software, provided by the invention, the position of an error time sequence path is determined by comparing the actual delay in the time sequence report with the delay calculated by the node passed by each path, so that the method and the device are convenient and quick. What is important for the implementation of the present invention is that when the delay is calculated, the relationship between the module ports is determined from a plurality of files, and the expected values of all delays are calculated according to the delays analyzed from the files and compared with the actual delays in the timing report. The problem that due to the fact that each circuit can have hundreds of time sequence paths and each time sequence path can pass through a plurality of cells, logic delay and path delay in each time sequence path are verified manually by a tester, and workload is very large is solved.
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FIG. 1 is a flow chart of the system of the present invention;
FIG. 2 is a diagram of a testing apparatus according to the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Fig. 1 shows a specific embodiment of the method for testing path timing delay in FPGA EDA software according to the present invention, which includes the following steps:
step 1: and acquiring and analyzing the time sequence model file, the chip structure file, the netlist file and the wiring file, and calculating the logic delay and the path delay of each time sequence path in the time sequence model file according to the relationship among the modules in the files.
In this embodiment, the method for calculating the logic delay and the path delay of each time sequence path in the time sequence model file includes:
step 1.1: and analyzing the time sequence model file to obtain each module, the channel delay corresponding to each module, the delay, the establishing time and the holding time of each module port, and generating a time _ mode _ dit of the time sequence model dictionary.
The time sequence model file is a file which is organized by hardware through actual time sequence delay, wherein the time delay to each module port is included, the establishing time (which is the time that data are stable and unchangeable before the rising edge of a clock signal of a trigger arrives), the maintaining time (which is the time that data are stable and unchangeable after the rising edge of the clock signal of the trigger arrives) and the delay to each module are stored in the form of an xml file, all subsequent delay calculation in the invention can be calculated through the file, the xml file is analyzed by introducing a parse module in python, and a time _ mode _ ditct of a time sequence model dictionary is generated after analysis, and the dictionary is as follows:
{CELL：[{(dstPort1, startPort1): [p_delay], (dstPort2, startPort2): [p_delay] , (dstPort3, startPort3): [p_delay]}, {ff_Port: {port1: {t_su: delay, t_h: delay}, port2: {t_su: delay, t_h: delay}, port3: {t_su: delay, t_h: delay}}}], Ram_Block：[{(dstPort1, startPort1): [p_delay], (dstPort2, startPort2): [p_delay] , (dstPort3, startPort3): [p_delay]}, {ff_Port: {port1: {t_su: delay, t_h: delay}, port2: {t_su: delay, t_h: delay}, port3: {t_su: delay, t_h: delay}}}], IO：[{(dstPort1, startPort1): [p_delay], (dstPort2, startPort2): [p_delay] , (dstPort3, startPort3): [p_delay]}, {ff_Port: {port1: {t_su: delay, t_h: delay}, port2: {t_su: delay, t_h: delay}, port3: {t_su: delay, t_h: delay}}}], PLL：[{(dstPort1, startPort1): [p_delay], (dstPort2, startPort2): [p_delay] , (dstPort3, startPort3): [p_delay]}, {ff_Port: {port1: {t_su: delay, t_h: delay}, port2: {t_su: delay, t_h: delay}, port3: {t_su: delay, t_h: delay}}}], MUX: {module_name1: m_delay, module_name2: m_delay, module_name3: m_delay }}。
wherein CELL, ram _ Block, IO, PLL represent module names in the netlist file, dstPort1 represents an input port name in a timing path node, startPort1 represents an output port name in a timing path node, and p _ delay represents the delay from dstPort1 to startPort 1.
In the dictionary, ff _ Port represents an incoming Port, port1 represents a Port from ff _ Port, t _ su is establishment time, t _ h is retention time, and the delays belong to logic delay.
In the dictionary, the delay represented in the MUX is the path delay, the module _ name1 represents the module name, the m _ delay represents the channel delay of the module, and the channel delay belongs to the path delay.
Step 1.2: analyzing the chip structure file to obtain coordinate positions of all chips and module names corresponding to each coordinate position, and generating a module position dictionary, namely, cable _ mux _ dit;
the chip structure file comprises coordinate positions of all chips and module names, a table _ mux _ dit dictionary is generated by analyzing the file, the module name corresponding to each coordinate path is stored, and the dictionary is as follows:
{ loc1: module _ name, loc2: module _ name, loc3: module _ name }, with position as key and module name as attribute value.
Step 1.3: and analyzing the netlist file to obtain all cells in the netlist, all ports under each cell and signals passing through the ports, and generating a module port signal dictionary cell _ dit.
Because the netlist includes all cells, ports and signals, when the netlist file is analyzed, the cell _ name is used as a key, and the port and the signal under the cell are used as value values to be stored in the module port signal dictionary cell _ dit, as follows:
{cell_name1: {port1: [signal…], port2: [signal…], port3: [signal…]}, cell_name2: {port1: [signal…], port2: [signal…], port3: [signal…]}, cell_name2: {port1: [signal…], port2: [signal…], port3: [signal…]}}。
step 1.4: analyzing the wiring file to obtain a source point, a path and a sink point which are passed by each signal, and generating a signal dictionary route _ dit, wherein each source point, each path and each sink point comprise a coordinate position and a port name;
wherein, the routing file stores the signal name as key, the source point, the path, and the sink point passed by the signal as value into the signal dictionary route _ fact, wherein each signal may have multiple sink points, and each path is stored into the list by way of the metaancestor form (one metaancestor is indicated in each small bracket in the dictionary), as follows:
{signal1: [(source, chan…,sink), (source, chan…,sink)…], signal2: [(source, chan…,sink), (source, chan…,sink)…], signal3: [(source, chan…,sink), (source, chan…,sink)…]}。
each source, chan, and sink that passes through includes a coordinate location and a port name, and is stored in a list form: [ loc, port ], loc denotes a coordinate position, and port denotes a port name.
Through the analysis of the sequence model file, the chip structure file, the netlist file and the wiring file, the association with the netlist file can be established through the signal name, the starting module name and the port name in the wiring file, the module corresponding to the channel chan is found from a module position dictionary table _ mux _ dit of the chip structure file through the position of the channel chan in the signal, and the delay among module ports and the module channel delay are further found from a time _ mode _ dit of the sequence model dictionary. The correlation between these files is found, so that the calculation of the logic delay and the path delay is possible, and the logic delay and the path delay can be compared with the actual delay in the timing report.
For the timing report, a timing report pb file is generated by a timing path acquisition, and the data of the pb file can be opened through a sqlite database, so by introducing a sqlite3 library in python, the pb file is opened, and all timing paths are acquired, including a simultaneous setup path, a simultaneous hold path, a cross-clock setup path, a cross-clock hold path, an asynchronous setup path, and an asynchronous hold path, and all generated paths are saved in a path _ fact dictionary, which is as follows:
{path_type1: [path1, path2, path3…], path_type2: [path1, path2, path3…], path_type3: [path1, path2, path3…]}。
the path _ type represents the type of the timing path, including a same-clock setup path, a simultaneous clock hold path, a cross-clock setup path, a cross-clock hold path, an asynchronous setup path, and an asynchronous hold path, and the path1, the path2, and the path3 represent all paths under the type, where the path1, the path2, and the path3 are a list type that lists all module cells, ports, and delays that the timing path passes through, and the list is as follows:
[(delay_type, delay, total_delay, cell, port, location), (delay_type, delay, total_delay, cell, port, location), (delay_type, delay, total_delay, cell, port, location), (delay_type, delay, total_delay, cell, port, location)]。
each primitive (tuple in python, indicated by a small bracket) in the list represents a path, where delay _ type represents a delay type, delay _ type represents a logic delay when being 0, delay _ type represents a path delay when being 1, delay is a delay of a corresponding delay type calculated in a timing report, total _ delay is a sum of all delays in the timing path, and cell refers to a cell name of the path (sometimes, a cell name in a path is not consistent with a cell name obtained in a netlist file, it is necessary to convert the cell name in a path into a cell name in a netlist file), port refers to a port name in a cell of the path, location represents a position of the cell after packing layout, delays of the same delay type in the timing path are added to obtain a path delay and a logic delay, and the path delay and the logic delay are added to obtain a total delay.
The time delays of all time sequence paths are acquired by analyzing the time sequence report and are stored as a time sequence report delay dictionary rpt _ dit, the dictionary rpt _ dit comprises the delay of a starting clock, the delay of data and the delay of an end clock, the delay of data comprises logic delay and path delay, and the dictionary is as follows:
{ 'src _ clk', [ logic _ delay, net _ delay, total _ delay ], 'data', logic _ delay, net _ delay, total _ delay ], 'dest _ clk', logic _ delay, net _ delay, total _ delay }. 'src _ clk' represents a delay of a start clock, 'data' represents a data delay, 'dest _ clk' represents a delay of an end clock. logic _ delay represents the logical delay, net _ delay represents the path delay, and total _ delay represents the total delay.
Step 1.5: calculating logic delay: the method comprises the steps of obtaining a time sequence path list in a time sequence report, finding out path nodes which are of logic delay types in the time sequence path list, determining a module cell and a port of a first time sequence path node through which the time sequence path passes as startPort1 in a dictionary time _ mode _ dit, checking a port output by the module along the time sequence path as dstPort1, finding out delay of the module port from the module cell, the port dstPort1 and the startPort1 which correspond to the time sequence model dictionary time _ mode _ dit, and accumulating by the method of finding out all logic delays in the time sequence path.
Specifically, firstly, whether a path in a timing report is empty is judged, if the path is empty, it indicates that the project has no timing path, if the path is not empty, a calculation of a logic delay is performed, during the calculation, a path node with delay _ type of 0 representing a logic delay type is found by obtaining a path1 list, a module name (CELL, ram _ Block, IO, PLL) of the first path node and a start port startPort1 are determined by finding a CELL and a port through which the timing path passes, a port output by the module is found along the timing path as an end port dstPort1, a logic delay [ p _ delay ] corresponding to the module name (dstPort 1, startPort 1) is found through time _ mode _ dct, and delays of all logic delay types of the timing path are found by following paths in sequence and accumulated.
In this embodiment, when the end-point clock delay is calculated, the delay from the clock to the end-point register is calculated, ff _ Port in the dictionary needs to be found according to the time _ mode _ dit of the time sequence model dictionary, corresponding module names and corresponding delays of the ports are found according to the end-point module names and the Port names of the registers, and the start-point clock delay is obtained after summation.
In this embodiment, when calculating the logic delay of the sequential path, if the sequential path is a setup type path, the delay of t _ su needs to be subtracted from the time of all the logic delays, and if the sequential path is a hold type path, the delay of t _ h needs to be added to the time of all the logic delays.
Step 1.6, calculating path delay: finding out path nodes of path delay types in a time sequence path list, obtaining a module cell, a port and a module position location which a time sequence path passes through from a path node of a first path delay type, obtaining a signal name which the port passes through from a module port signal dictionary cell _ fact according to the module cell and the port, wherein the module cell and the port are signal initial points, then finding out a module name cell, a port and a position location of a next path node of the path delay types from the time sequence path list, wherein the path node is an end point sink, finding out all channel paths which the path passes through from a signal dictionary route _ fact according to the signal name, the initial point source and the end point sink, finding out all position locations which the path passes through according to the channel paths, finding out all position locations which the path passes through from a module position dictionary table _ MUX _ cause _ fact according to the position location, and finding out corresponding time delay module paths from a module _ cause _ time _ cause _ module _ cause _ time delay corresponding to the time sequence path.
Through the logic delay and the path delay, an actual calculation delay dictionary calc _ delay is generated, which includes all the logic delays and path delays calculated by the timing model and the chip structure, and the dictionary is as follows:
{‘src_clk’: [logic_delay, net_delay, total_delay], ‘data’: [logic_delay, net_delay, total_delay], ‘dest_clk’: [logic_delay, net_delay, total_delay]}。
and finally, performing time delay comparison and generating a result file: comparing the time sequence report time delay dictionary rpt _ dit with the actual calculation time delay dictionary calc _ delay, comparing the logic time delay logic _ delay, the path time delay net _ delay and the total time delay total _ delay of keys with the same time delay type, finally generating a comparison result file, printing the error path, the time delay type and the time delay in the time sequence report if the error occurs, and calculating the expected time delay, thereby being clear of the error.
If the results are inconsistent, the results are generated as shown in the following Table-1:
| path id | Starting cell | End point cell | Logical delays in reporting | Path delay in reporting | Total latency in reporting | Calculated logical delay | Calculated path delay | Calculated total delay |
| 1 | Cell1_1 | Cell1_2 | 200 | 300 | 500 | 200 | 400 | 600 |
| 2 | Cell2_1 | Cell2_2 | 523 | 400 | 923 | 325 | 923 | 1248 |
| 3 | Cell3_1 | Cell3_2 | 206 | 536 | 752 | 206 | 536 | 742 |
| 4 | Cell4_1 | Cell4_2 | 159 | 248 | 407 | 260 | 613 | 873 |
Fig. 2 shows a specific embodiment of a test apparatus diagram for path timing delay in FPGA EDA software according to the present invention, including:
and an actual calculation delay module: the system comprises a time sequence model file, a chip structure file, a netlist file and a wiring file, wherein the time sequence model file, the chip structure file, the netlist file and the wiring file are obtained and analyzed, and the logic delay and the path delay of each time sequence path in the time sequence model file are calculated according to the relation among modules in each file;
the time sequence report delay calculation module: the time sequence report file is used for acquiring and analyzing the time sequence report file, and the logic delay and the path delay of each time sequence path in the time sequence report file are found out;
a judging module: and the logic delay and the path delay calculated by each time sequence path in the actual calculation delay module are compared with the logic delay and the path delay of the corresponding time sequence path obtained from the time sequence report in the time sequence report delay calculation module to obtain a comparison result and output the comparison result.
According to the method and the device for testing the time sequence delay of each path in the FPGA EDA software, provided by the invention, the time sequence report delay in the time sequence report is compared with the actual calculation delay calculated through the nodes passed by each path, so that the position of the wrong time sequence path is determined. In addition, the invention can also carry out batch circuit verification, has strong expansibility, can be added into the automatic execution of the interface, and can call the verification script of the invention to carry out the batch verification of the time sequence after the interface is executed and the box layout and wiring are finished.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A method for testing path time sequence delay in FPGA EDA software is characterized by comprising the following steps:
step 1: acquiring and analyzing a time sequence model file, a chip structure file, a netlist file and a wiring file, and calculating the logic delay and the path delay of each time sequence path in the time sequence model file according to the relationship among modules in the files;
and 2, step: acquiring and analyzing a time sequence report file, and finding out the logic delay and the path delay of each time sequence path in the time sequence report file;
and 3, step 3: and (3) comparing the logic delay and the path delay calculated by each time sequence path in the step (1) with the logic delay and the path delay of the corresponding time sequence path obtained from the time sequence report in the step (2) to obtain a comparison result and output the comparison result.
2. The testing method according to claim 1, wherein the method for calculating the logic delay and the path delay of each timing path in the timing model file in step 1 is as follows:
step 1.1: analyzing the time sequence model file to obtain each module, channel delay corresponding to each module, delay, establishing time and holding time of each module port, and generating a time _ mode _ fact of a time sequence model dictionary;
step 1.2: analyzing the chip structure file to obtain coordinate positions of all chips and module names corresponding to each coordinate position, and generating a table _ mux _ dit for storing a module position dictionary;
step 1.3: analyzing the netlist file to obtain all module cells in the netlist, all ports under each module cell and signals passing through all the ports, and generating a module port signal dictionary cell _ fact;
step 1.4: analyzing the wiring file to obtain a source point, a path and a sink point which are passed by each signal, and generating a signal dictionary route _ dit, wherein each source point, path and sink point comprise a coordinate position and a port name;
step 1.5: calculating logic delay: obtaining a time sequence path list in a time sequence report, finding out a path node which is of a logic delay type in the time sequence path list, determining that a module cell and a port of a first time sequence path node which the time sequence path passes through are used as an input port dstPort1 in a dictionary time _ mode _ direct, then viewing an output port of the module along the time sequence path to be used as a startPort1, finding out the delay of the module port from the corresponding module cell and the ports dstPort1 and startPort1 in the time sequence model dictionary time _ mode _ direct, and repeating the steps of finding out all logic delays in the time sequence path and accumulating;
step 1.6: calculating path delay: finding out a path node which is a path delay type in the time sequence path list, obtaining a module cell, a port and a module position location which are passed by the time sequence path from the path node of the first path delay type, obtaining a signal name which is passed by the port from a module port signal dictionary cell _ dit according to the module cell and the port, wherein the module cell and the port are signal starting points source, and then finding out the module name cell, the port and the position location of the next path node of the path delay type from the time sequence path list, the path node is an end point sink, all channels chan passed by the path are found out from a signal dictionary route _ fact according to the signal name, the start point source and the end point sink, all position locations passed by the path are found out according to the channels chan, a module name module _ name is obtained from a module position dictionary table _ mux _ fact according to the position locations, the time delay corresponding to the corresponding module _ name is found out from a time sequence model dictionary time _ module _ fact according to the module name module _ name and is used as the path delay, and all path delays in the time sequence path are found out in sequence and accumulated.
3. The test method according to claim 2, wherein the method for finding out the logic delay and the path delay of each timing path in the timing report file in step 2 is:
acquiring a time sequence report file to obtain all time sequence paths, and storing all the time sequence paths in a time sequence path dictionary path _ dit; the time sequence path dictionary path _ dct includes all time sequence paths under various time sequence path types, all module cells, ports and delays passed by the time sequence path are listed in each time sequence path, delays of the same delay type in the time sequence path are added to obtain path delay and logic delay, and the path delay and the logic delay are added to obtain total delay.
4. The test method according to claim 3, wherein the time-series path dictionary path _ dit further includes a delay of a start clock, a data delay, and a delay of an end clock, the data delay including a logic delay and a path delay.
5. The test method of claim 3, wherein the timing path types include a simultaneous clock setup path, a simultaneous clock hold path, a cross-clock setup path, a cross-clock hold path, an asynchronous setup path, and an asynchronous hold path.
6. The test method of claim 4, wherein the step of calculating the end point clock delay is calculating the delay from the clock to the end point register, and finding out the corresponding setup time or hold time corresponding to the module name and port from the time _ mode _ dit of the timing model dictionary according to the end point module name and port name of the register, and summing the setup time or hold time to obtain the end point clock delay.
7. The test method of claim 4, wherein calculating the start clock delay is calculating the delay from the clock to the start register, finding out the corresponding module name and the corresponding delay of the port from the time model dictionary time _ mode _ fact according to the start module name and the port name of the register, and summing to obtain the start clock delay.
8. The test method as claimed in claim 6, wherein when calculating the sequential path logic delay, if the sequential path logic delay is a setup type path, the time of all logic delays needs to be subtracted by the delay of t _ su, and if the sequential path logic delay is a hold type path, the time of all logic delays needs to be added by the delay of t _ h.
9. The device for testing the path time sequence delay in the FPGA EDA software is characterized by comprising the following modules:
and an actual calculation delay module: the system comprises a time sequence model file, a chip structure file, a netlist file and a wiring file, wherein the time sequence model file, the chip structure file, the netlist file and the wiring file are obtained and analyzed, and the logic delay and the path delay of each time sequence path in the time sequence model file are calculated according to the relation among modules in each file;
the time sequence report delay calculation module: the time sequence report file is used for acquiring and analyzing the time sequence report file, and finding out the logic delay and the path delay of each time sequence path in the time sequence report file;
a judging module: and the logic delay and the path delay calculated by each time sequence path in the actual calculation delay module are compared with the logic delay and the path delay of the corresponding time sequence path obtained from the time sequence report in the time sequence report delay calculation module to obtain a comparison result and output the comparison result.
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