CN109710998B

CN109710998B - Memory optimization type static time sequence analysis method and system thereof

Info

Publication number: CN109710998B
Application number: CN201811495961.9A
Authority: CN
Inventors: 朱春; 谢丁
Original assignee: Shanghai Anlogic Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co.,Ltd.
Priority date: 2018-02-27
Filing date: 2018-12-07
Publication date: 2021-01-05
Anticipated expiration: 2038-12-07
Also published as: CN109710998A

Abstract

The application relates to a digital circuit and discloses a memory optimization type static time sequence analysis method and a system thereof. On the premise of not expanding subgraphs, the method instantly distinguishes and discards the false path in the traversal scanning process, reduces the influence of the false path on the downstream nodes, reduces redundant calculation, dynamically processes various timing constraints on each node in a differentiation mode in the traversal process, correspondingly covers two clusters, and reduces the number of labels on each node. The application of the method and the device can greatly reduce the occupation of the memory space of the system, improve the operation efficiency of the system and improve the performance of the system.

Description

Memory optimization type static time sequence analysis method and system thereof

Technical Field

The present invention relates to the field of digital circuits, and in particular, to a memory optimized static timing analysis method and system.

Background

In the process of realizing the physical design of the digital circuit, the static time sequence analysis plays a very important role, the feedback result of the static time sequence analysis provides a drive for a plurality of optimization programs in the process, and the kernel of the tool repeatedly calls the static time sequence analysis for iterative optimization for a plurality of times in different design stages, such as logic synthesis, layout, wiring and the like. Therefore, as a crucial underlying analysis engine, the performance of the static timing analysis tool has a very important impact on the performance of the entire software tool. The running efficiency of the bottom layer engine, including running time and space consumption, becomes a bottleneck of the efficiency of the whole set of tools, and the inventor of the application observes that the most advanced static timing analysis method in the prior art has the problem of excessive memory consumption in the aspects of eliminating false paths and cleaning multi-cycle paths.

Disclosure of Invention

The method and the system are used, so that redundancy preprocessing is reduced in the preparation stage of static time sequence analysis, and redundant information can be analyzed and abandoned in real time in the process; and on the premise of not degrading the software running time, the occupation of the memory space of the system is greatly reduced, the running efficiency of the system is improved, and the performance of the system is improved.

In order to solve the above problem, the present application discloses a memory optimization type static timing analysis method, including:

acquiring a circuit netlist to construct a timing diagram;

backward traversing and scanning the time sequence chart to obtain a subsequent path label set of each node;

forward traverse scanning the timing chart to obtain a preamble path label set of each node;

performing intersection operation on the pre-order path label set and the post-order path label set, and constructing a bipartite graph of each node according to the result of the intersection operation;

and according to the bipartite graph of each node, performing bipartite covering on each label of each node, and reducing the total amount of labels.

Calculating the delay margin corresponding to each label of each node and generating an analysis report;

and in the processes of the backward traversal scanning and the forward traversal scanning, identifying a false path in real time and discarding a label corresponding to the false path at the same time.

In a preferred embodiment, the method further comprises the following steps: the calculating the delay margin corresponding to each label on each node and generating the time sequence analysis report further comprises:

executing the following steps for many times until judging that no time sequence violation path exists in the time sequence chart, finally generating a time sequence analysis report,

calculating the delay allowance of each label of each node and recording the delay allowance on the corresponding label;

analyzing the time sequence violation path, judging whether the violation path exists in the time sequence chart, optimizing and modifying the path information on all the labels in all the nodes in the violation path if the violation path exists, and modifying the delay margin on the label corresponding to the path information.

In a preferred embodiment, the obtaining a circuit netlist construction timing diagram further includes: a circuit netlist is obtained to construct an overall timing diagram, and a partial timing diagram is constructed according to specified timing constraints.

In a preferred embodiment, in the process of the forward traversal scanning timing chart, the intersection operation is performed on the pre-order path label set and the post-order path label set while the forward traversal scanning passes through each node;

the constructing the bipartite graph of each node according to the result of the intersection operation further comprises: and obtaining all path information passing through each node according to the intersection operation, and constructing a bipartite graph of each node according to the path information.

In a preferred embodiment, each node has at least one tag, and each tag corresponds to a timing constraint;

and dynamically and differentially processing various timing constraints on each node when the two-cluster covering is carried out on each label of each node.

In a preferred embodiment, the backward traversing the scan timing graph to obtain the subsequent path label set of each node further includes: calculating a subsequent path label set of each node according to a first method; the first method further comprises: if node v is the primary output, a set is generated at node v

If node v is not the primary output, then for each back-driving edge (u, v) a set R' of v is computed, denoted as: r ' ═ R ═ t (u)), (v, u) and if R ' #f (v) is not dominated by spurious paths, add set R ' to the overall subsequent path label set of node v;

the step of obtaining the preamble path label set of each node by traversing the scan timing diagram further comprises: calculating a preamble path label set of each node according to a second method; the second method further comprises: if node v is the primary input, a set is generated on node v

If node v is not the primary input, then for each predecessor edge (u, v) a set R' of v is computed, denoted as: r ' ═ R ═ f (u)), (u, v), and if R ' _ t (v) is not dominated by the dummy path, then add R ' to the overall set of preamble path labels for node v;

the method for determining whether R '# T (v) and R' # F (v) are dominated by the dummy path is as follows: if the obtained intersection has false path constraint under the appointed time sequence constraint, judging that the preorder or postorder path is given to the leading part by the false path; where f (v) represents a set of all constraints starting from the node v, t (v) represents a set of all constraints ending from the node v, and I (u, v) represents a set of all constraints covering the edge (u, v).

The application also discloses a static time sequence analysis system of memory optimization type, includes:

the constructing module is used for acquiring the circuit netlist to construct an overall timing diagram and constructing a partial timing diagram according to the specified timing constraint;

the calculation module is used for calculating a subsequent path label set of each node, calculating a preamble path label set of each node, performing intersection operation on the preamble path label set and the subsequent path label set, solving bipartite graph representation corresponding to the intersection of the sets on each node, and performing bipartite covering on each label of each node to obtain a label on each node, wherein in the processes of backward traversal scanning and forward traversal scanning, a false path is immediately identified and the label corresponding to the false path is discarded;

and the processing module is used for calculating the delay margin corresponding to each label on the node and generating a time sequence analysis report.

the method for determining whether R '# T (v) and R' # F (v) are dominated by the dummy path is as follows: if false path constraint exists in the obtained intersection, judging that the preorder path or the postorder path is given to the leading path by the false path; where f (v) represents a set of all constraints starting from the node v, t (v) represents a set of all constraints ending from the node v, and I (u, v) represents a set of all constraints covering the edge (u, v).

The application also discloses a group cover system, includes:

a memory for storing computer executable instructions; and the number of the first and second groups,

a processor for implementing the steps in the method as described hereinbefore when executing the computer executable instructions.

The present application also discloses a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the steps in the method as described hereinbefore.

The method comprises the steps of optimizing the number of labels of each node of a reduced time sequence diagram, and enabling the reduced labels to be used for calculating the delay allowance in subsequent iteration; the process is divided into four stages, namely a data preparation stage, a preprocessing stage, a label generation stage, an analysis stage and a report stage, and the key points and the beneficial effects of the method are explained in detail according to the four stages.

In the embodiments of the present application, the key points are at least:

1. a data preparation stage: a) expressing the circuit netlist into a directed acyclic timing diagram; b) reading a delay information base file and marking a timing chart; c) extracting various complex time sequence constraints set by a user in a time sequence constraint file; d) and expressing specified timing constraints (such as false path constraints and multi-cycle path constraints) into a timing diagram subgraph.

2. A pretreatment stage: a) sub-graph expansion without false path constraint; b) and performing set representation on the timing subgraphs corresponding to the specified timing constraints.

3. And a label generation stage: a) backward traversal scanning to obtain a subsequent path label set label of each node, and instantly identifying a false path and discarding a corresponding label; b) forward traversal scanning is carried out to obtain a preamble path label set label of each node, a false path is identified immediately, and a corresponding label is discarded; c) while traversing through each node in the forward direction, solving the intersection of the pre-sequence path label and the post-sequence path label; d) constructing a bipartite graph according to the intersection obtained on the current node; e) covering a plurality of labels sharing the downstream path time sequence by two clusters to generate new labels, and reducing the total quantity of the labels on the whole; f) the multicycle constraint required by different cycles can be identified and processed in a two-cluster covering process.

4. Analysis phase and reporting phase: a) according to the main input delay appointed in the time sequence constraint, performing forward traversal scanning from the main input, and calculating the maximum arrival time and the minimum arrival time corresponding to each label on each node; b) backward traversal scanning is performed from the master output according to the clock period specified in the timing constraint. Calculating the maximum demand time and the minimum demand time corresponding to each label on each node c) calculating the establishment time allowance and the retention time allowance on each label; d) respectively collecting the establishment time constraint violation and the maintenance time constraint violation; e) extracting corresponding path information for the illegal label; f) and reporting the critical path information to an optimization tool for optimization.

In the prior art, in order to uniformly process a false path and a multi-cycle path, a subgraph corresponding to the false path is intentionally expanded in a preprocessing stage, and a new subgraph after expansion and extension contains a large number of upstream and downstream nodes of each node, resulting in very large memory overhead; in addition, in the prior art, decisions about identifying whether the paths are false paths and discarding the false paths, identifying whether the paths are multicycle paths and specially processing the multicycle paths are all postponed to be carried out at the last stage, a large amount of redundant calculation is introduced, space overhead is improved in a phase-changing manner, and analysis efficiency is reduced.

Compared with the prior art, the application has the advantages that: 1. the error path subgraph expansion is not carried out in the preprocessing stage, and the space requirement for expressing the redundant subgraph is greatly reduced; 2. and identifying false paths and discarding corresponding labels in the forward and backward traversal scanning process. The quantity of the labels in the timing diagram can be quickly reduced, the space requirement is obviously reduced, and the analysis efficiency is quickly improved; 3. various multi-period constraints required by different periods can be identified and distinguished in the process of two-cluster covering, and processing data is combed and simplified on the premise of not improving algorithm complexity; in conclusion, on the premise of not expanding the subgraph, the invention instantly judges whether the false path is discarded in the traversing process, reduces the influence of false path constraint on the downstream nodes, reduces redundant calculation, dynamically processes different types of time sequence constraints such as false path constraint, multi-cycle path constraint and the like in the traversing process in a differentiated mode, correspondingly performs two-block coverage, and further reduces the number of labels on each node.

Compared with the prior art, the embodiment of the invention has the following remarkable effects: on the premise of not degrading the software running time, the occupation of the memory space of the system is greatly reduced, the running efficiency of the system is improved, and the performance of the system is improved.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

FIG. 1 is a schematic flow chart of a static timing analysis method according to the present application

FIG. 2 is a schematic flow chart illustrating a memory-optimized static timing analysis method according to a first embodiment of the present application

FIG. 3 is a flow chart of a specific method for constructing a timing diagram according to the circuit netlist in the present application

FIG. 4 is a schematic diagram of an overall timing diagram according to a specific example in the present application

FIG. 5 is a schematic diagram of a portion of a timing diagram according to one specific example in the present application

FIG. 6 is an example of sub-step 202 according to the first embodiment of the present application

FIG. 7 is a schematic diagram of a bipartite graph of a node v according to a specific example in the present application

FIG. 8 is a schematic diagram of a two-blob overlay according to a specific example in this application

FIG. 9 is an example of a timing analysis method for a place and route process in a physical design according to a first embodiment of the present application

FIG. 10 is a schematic structural diagram of a static timing analysis system according to a second embodiment of the present application

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

Description of partial concepts:

1. static timing analysis: in electronic engineering, the timing sequence of a digital circuit is calculated and predicted to work, and the process does not need to be simulated by means of input excitation. Traditionally, one often has the operating clock frequency as one of the characteristics of a high performance integrated circuit. In order to test the ability of a circuit to operate at a specified rate, one needs to measure the delay of the circuit at different stages of operation during the design process. In addition, delay calculation is required to be performed on the internal paths of the circuit in different design stages (such as logic synthesis, placement, routing and some subsequent stages) so as to guide optimization, and static timing analysis plays an important role in rapid and accurate measurement of circuit timing.

2. A synchronous digital circuit: in a synchronous digital system, the flow of data should be in a consistent pace, i.e., the data can change once per change in the clock signal. This is accomplished by synchronous digital circuit devices, such as flip-flops or latches, that are clocked to copy data from their inputs to their outputs.

3. Establishing a time constraint: set-up time (T)_s) Meaning the minimum time that the signal remains stable until the clock sample level in order to be effectively sampled. To be provided withTo efficiently transfer and sample signals to the next sequential device (flip-flop), the delay of the combinational logic circuit must satisfy d_p<T_period-T_SWherein T is_periodRepresenting clock cycles, typically the setup time constraint is for a single clock cycle.

4. And (3) keeping time constraint: hold time (T)_h) Meaning the minimum time that the signal remains stable after the clock sample level in order to be effectively sampled. In order to keep the output sampling signal of the current time sequence device stable and not be covered by the same period sampling signal output by the previous time sequence device to cause data error, the holding time must satisfy d_p>T_h. Therefore, the combinational logic circuit delay between two stages of sequential devices must satisfy: t is_h<d_p<T_period-T_S。

5. Multi-cycle path: generally, the time required for a signal to pass through a combinational circuit between two stages of sequential devices is one clock cycle. In some particular designs, the time span for a signal to travel between two stages of sequential devices is a number of clock cycles. This flip-flop and the data path between flip-flops is referred to as a multi-cycle path. In the multi-cycle path, the setup time constraint and the hold time constraint are adjusted accordingly. For example, a time constraint of d is established_p<N×T_period-T_sAnd N is the number of clock cycles.

6. False path: during the actual operation of the circuit, due to logical mutual exclusion or a specific situation, there are certain paths in which signal conduction is unlikely to occur, these paths are called dummy paths, which are usually ignored by the analysis tool because they may give negative guidance to the actual optimization procedure, resulting in circuit timing being too conservative.

7. Timing diagram: a directed acyclic graph depicting a circuit structure. In the timing diagram, the nodes represent the input and output pins of a basic cell circuit, such as a register or a logic gate, and the edges represent the input-to-output connections of a combinational logic cell circuit, or connections specified by the circuit netlist. Each edge is labeled with the delay needed to pass through the cell circuit or routing resource. The register input pin is not connected to the output pin-the register output pin has no input edge, and the register input pin also has no output edge. Likewise, the primary input (input pin) has no input edge, while the primary output (output pin) has no output edge.

8. Timing constraint: the input of the static time sequence analysis tool comprises a series of specifications, such as working frequency requirements, clock deviation, main input delay, multiple clock domains, false paths, multiple periodic paths and other conditions, the static time sequence analysis tool comprehensively considers complex superposition conditions in time sequence constraints, calculates the arrival delay and the required delay of each actual path, further obtains the delay margin of the current path, and finally provides feedback for the optimization tool.

9. Arrival delay: the time that the signal needs to travel to reach the specified location of the circuit typically takes the time of arrival of the clock signal as the reference time, or zero time. To calculate the arrival time, a delay accumulation calculation of all combinational logic paths on the path needs to be performed. The time of arrival generally relates to a pair of data, namely the earliest possible time of arrival and the latest possible time of arrival after a signal change.

10. Delay of demand: the signal can arrive without violating the timing design requirements of the overall circuit. Typically the path end point is back-calculated in conjunction with this programmed position to end point delay.

11. And (3) delay allowance: the difference between the demand time and the arrival time. A positive margin at the node represents that the arrival time can be increased by the time represented by the margin, and the overall delay condition of the circuit is still not influenced; conversely, a negative margin indicates that the transmission is too slow on the path whose transmission rate must be increased, otherwise the overall circuit formed by it cannot operate at the expected rate.

12. A bipartite graph: the vertex set can be divided into two mutually disjoint subsets, and two vertices to which each edge is attached belong to the two mutually disjoint subsets, the vertices in the two subsets are not adjacent, and the vertex adjacency indicates that an edge connection exists between the two subsets.

13. Complete bipartite graph: the graph in which each pair of vertices belonging to two subsets in the bipartite graph is adjacent is referred to as a complete bipartite graph, herein simply referred to as a bipartite blob.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

A first embodiment of the present application relates to a memory-optimized static timing analysis method.

The static timing analysis method includes two major steps, step 101 and step 102, as shown in fig. 1:

to begin, step 101 is performed: and acquiring a circuit netlist to construct a timing diagram and optimizing and generating labels of all nodes according to the timing diagram. Optionally, each node of the timing graph finally has at least one label, each label corresponds to a timing constraint, and the constraint is a constraint subjected to combinatorial optimization rather than an original timing constraint; all of the arrival time, demand time, and delay margins we discuss hang up on this particular tag.

Then, step 102 is executed: and calculating the delay margin corresponding to each label of each node and generating a time sequence analysis report. Optionally, as shown in fig. 2, the step 102 further includes: repeatedly executing 'substep 204-substep 207' until the timing violation path does not exist in the timing diagram, and finally generating a timing analysis report; the method comprises the following specific steps: beginning, executing a substep 204, calculating the delay allowance of each label of each node and recording the delay allowance on the corresponding label; then, executing substep 205, analyzing the timing violation path, and determining whether the violation path exists in the timing chart; if yes, executing a substep 206, optimizing and modifying the path information on all labels in all nodes in the violation path, and modifying the delay margin on the corresponding labels, otherwise, executing a substep 207, and generating a timing analysis report. It should be noted that: the specific methods for optimizing and modifying the path information of the tag in the offending path and modifying the delay margin are prior art and will not be described in detail here.

This step 102 further comprises: the arrival time, the required time and the delay margin of each tag are calculated and recorded on the corresponding tag, and once the tag is generated in step 101, it remains unchanged in step 102, but the "arrival time, required time and delay margin" on the tag can be recalculated and overwritten.

Since the step 102 is repeatedly called by a multi-channel optimization program in the physical design flow to realize iterative optimization, the performance of the step 102 depends on the quality of the label generated in the step 101; therefore, the method according to the first embodiment of the present application mainly aims to: optimizing the label generation process and the quality of the generated label in step 101; as shown in fig. 2, the step 101 further includes "substeps 201 to 203", specifically:

to begin, substep 201 is performed: acquiring a circuit netlist to construct a timing diagram; specifically, an overall timing diagram is constructed for obtaining a circuit netlist, and a partial timing diagram is constructed according to specified timing constraints.

As shown in fig. 3, optionally, the sub-step 201 further comprises: beginning, step 301, a circuit netlist is formed into a directed acyclic timing diagram; then, step 302, reading the delay information base file and marking the timing diagram to obtain an integral timing diagram; then, step 303, extracting a plurality of timing constraints set by the user in the timing constraint file; then, in step 304, each constraint of the plurality of timing constraints is expressed as a partial timing diagram. Alternatively, the timing constraint may be set and changed by the user as the case may be, and the timing constraint may be, but is not limited to, a dummy path constraint and a multi-cycle path constraint.

The example of the application is based on two types of timing constraints of a false path and a multi-cycle path, and an obtained overall timing diagram is shown in FIG. 4; a partial timing diagram is constructed as shown in fig. 5, for example.

Then, the sub-step 202 is performed: and the backward traversal scanning sequence diagram obtains a backward path label set of each node, the forward traversal scanning sequence diagram obtains a preamble path label set of each node, the intersection operation is carried out on the preamble path label set and the backward path label set, and a bipartite graph of each node is constructed according to the result of the intersection operation, wherein in the processes of the backward traversal scanning and the forward traversal scanning, a false path is immediately identified and labels corresponding to the false path are abandoned at the same time.

In a preferred embodiment, in the process of the forward traversal scan timing chart, the intersection operation is performed on the preceding path label set and the following path label set while the forward traversal scan passes through each node.

Optionally, after the forward traversal scan timing chart, the intersection operation is performed on the pre-order path label set and the post-order path label set while the forward traversal scan passes through each node.

Fig. 6 shows an embodiment of the method of substep 202, which specifically comprises: starting, step 601, backward traversing the scanning timing chart to obtain a subsequent path label set of each node; then, step 602, traversing the scan timing chart forward, calculating and propagating the preamble path label set of each node; then, step 603, performing intersection operation on the pre-order path label set and the post-order path label set of the current node; then, step 604, generating a bipartite graph representing path information according to the intersection; thereafter, at step 605, two blobs are overlaid to reduce the number of labels.

Specifically, in the substep 202, the timing constraints of each node and edge in the timing diagram are expressed in a set, which is respectively embodied in a starting point set, an end point set and an edge set; this set of starting points is denoted f (v) { r | v ∈ B_rF (v) a set of all constraints starting from v, where B_rThe representation timing constraint r corresponds to the set of all starting points in the subgraph. Taking fig. 5 as an example, F (1) ═ 0}, F (2) ═ 1}, and so on. The endpoint set is expressed as: t (v) { r | v ∈ D_rWhere T (v) represents the set of all constraints ending with v, where D_rRepresenting the set of timing constraints r corresponding to all end points in the subgraph. Taking fig. 4 as an example, T (5) ═ 2}, T (6) ═ 3}, and so on. The set of edges is represented as I (u, v) — { r | (u, v) ∈ E_rDenotes the set of all constraints covering the edges (u, v), where E_rRepresenting the set of all edges in the sub-graph for the timing constraint r. Taking fig. 4 as an example, I (u, v) ═ {0,1,2,3}, I (u, 8) {0,1 }.

It should be noted that: because the starting point and the end point specified in the multi-cycle constraint must be the output end of the sequential device to the input end of the sequential device, the starting point and the end point of the sub-graph corresponding to the multi-cycle constraint must also be the starting point and the end point of the sequential graph, and for any other internal nodes v, f (v) and t (v) except the starting point and the end point in the sequential graph, the two sets do not contain the multi-cycle constraint.

Optionally, the step of backward traversing the scan timing graph to obtain a subsequent path label set of each node in the sub-step 202 further comprises: calculating a subsequent path label set of each node, wherein the method for calculating the subsequent path label set of each node comprises the following steps: if node v is the primary output, a set is generated at node v

If node v is not the primary output, then for each back-driving edge (u, v) a set R' of v is computed, denoted as: r ' ═ R ═ t (u)), (v, u) and if R ' #f (v) is not dominated by spurious paths, add set R ' to the overall subsequent path label set of node v; where f (v) represents a set of all constraints starting from the node v, t (v) represents a set of all constraints ending from the node v, and I (u, v) represents a set of all constraints covering the edge (u, v).

Optionally, the step of traversing the scan timing graph to obtain the preamble path label set of each node in the sub-step 202 further comprises: calculating a subsequent path label set of each node, wherein the method for calculating the subsequent path label set of each node comprises the following steps: if node v is the primary input, a set is generated on node v

If node v is not the primary input, then for each predecessor edge I (u, v) a set R' of v is computed, denoted as: r ═ f (u)), (u, v), and if R', (u), (v) is not subject to false path ownerIf yes, adding R' into the whole preorder path label set of the node v; where f (v) represents a set of all constraints starting from the node v, t (v) represents a set of all constraints ending from the node v, and I (u, v) represents a set of all constraints covering the edge I (u, v).

Optionally, the determining method of whether R '# t (v) and R' # f (v) are dominated by the dummy path is: if false path constraint exists in the obtained intersection, judging that the preorder path or the postorder path is dominated by the false path, and then discarding the label; where f (v) represents a set of all constraints starting from node v, t (v) represents a set of all constraints ending from node v, and I (u, v) represents a set of all constraints covering (u, v).

In sub-step 202, intersection operation is performed on the preceding path tag set and the following path tag set. Taking the timing diagram of fig. 4 and the timing constraint of fig. 5 as examples, the preceding path label set, the following path label set and their intersection on node v are shown in table 1:

intersection operation on node v of Table 1

Optionally, the constructing the bipartite graph of each node according to the result of the intersection operation further includes: and obtaining all path information passing through each node according to the intersection operation, and constructing a bipartite graph of each node according to the path information.

Taking the timing diagrams of fig. 4 and 5 and the false path constraint and the multi-cycle path constraint as examples of the specified constraints, constructing as a bipartite graph as shown in fig. 7, since the constraints #0 and #1 are false paths, any one of the two sets in the intersection is determined as a false path and discarded; in the bipartite graph of FIG. 7, we observe that there is no edge between the set of preamble path labels { {0} } and the set of subsequent path labels {0,1}, the set of preamble path labels { {1} } and the set of subsequent path labels {0,1}, which is an indication that a false path is identified and discarded.

Then, sub-step 203 is performed: and according to the constructed bipartite graph of each node, performing bipartite covering on each label of each node, reducing the total amount of labels, and finally obtaining the label of each optimized node.

Optionally, when performing two-clustering coverage on each label of each node, performing differentiation processing according to the type of the specified timing constraint. Alternatively, the specified timing constraint may be, but is not limited to, a multi-cycle path constraint. Taking the multi-cycle path constraint as an example: multicycle path constraints individually perform a two-cluster overlay, wherein if there are multiple multicycle path constraints, then differentiation is performed according to their respective cycle requirements; for example, if there are two multicycle constraints, both of which require 2 clock cycles, then the two constraints may be covered with the same bipartite clique; if the two constraints require a non-uniform number of cycles, then the same binary group cannot be used for coverage.

Taking the bipartite graph of FIG. 7 and the timing constraints specified by the dummy path constraint and the multi-cycle path constraint of FIG. 5 as examples, the two-blob overlay on node v is shown in FIG. 8; because the period requirements of the multicycle constraints #2 and #3 are different, they cannot be covered by the same bipartite group, one bipartite group corresponds to one label, so that the labels on the node v after being covered by the bipartite group are reduced from 4 to 3, and the original 4 labels are respectively: { {0} }, { {1} }, { {2} }, { {3} }, labels after binary coverage are: { {0}, {1} }, { {2} }, and { {3} }.

The label of each node generated after the time sequence diagram is optimized through the substep 201 to the substep 203 is the label after the redundant path is abandoned, and the label is used for providing a good basis for the iterative calculation of the delay margin in the substep 204 to the substep 205, thereby reducing the occupation of the system memory in the calculation process and improving the calculation efficiency; specifically, the essential purpose of the static timing analysis system is to analyze whether the delay in the netlist meets the requirement of the operating frequency, if not, provide a violation path report and modify a margin, and guide other application programs such as placement and routing to implement path delay optimization; the optimization process is not usually one-click, and is a process (specifically, "substep 204 to substep 207") of multiple iterations and gradual convergence, which characterizes that the cooperative work of the static timing analysis system and the optimization program is a compact and repeated process, and for a single optimization program, the netlist is not changed in the iteration process, so that only one netlist needs to be submitted to the static timing analysis system; in conclusion: the tight and repeated iterative time delay analysis process is implemented on the tags attached to the nodes of the time sequence diagram, and the tag generation process is optimized in detail through the substeps 201 to 203, so that the number of the tags on the nodes is reduced, and the redundancy of the system is reduced; the end result is: the memory optimization type static time sequence analysis method remarkably improves the performance and quality of a static time sequence analysis system and even the whole optimization program.

It should be noted that: the details listed in the specific examples referred to in the present application as "sub-step 201-207" are mainly for ease of understanding and are not intended to limit the scope of the present application.

Fig. 9 is an example of a timing analysis method of a layout and routing process in a physical design according to a first embodiment of the present application, and a timing diagram in the diagram is included in a partial timing diagram in the present application.

A second embodiment of the present application relates to a memory-optimized static timing analysis system, whose structure is shown in fig. 10, and the system includes a construction module, a calculation module and a processing module;

the constructing module is used for acquiring a circuit netlist to construct an overall timing diagram, and constructing a partial timing diagram according to specified timing constraints; the calculation module is used for calculating a subsequent path label set of each node, calculating a preamble path label set of each node, performing intersection operation on the preamble path label set and the subsequent path label set, solving bipartite graph representation corresponding to the intersection of the sets on each node, and performing bipartite covering on each label of each node to obtain a label on each node, wherein in the processes of backward traversal scanning and forward traversal scanning, a false path is immediately identified and the label corresponding to the false path is discarded; the processing module is used for calculating the delay margin corresponding to each label on the node and generating a time sequence analysis report.

Optionally, the method for calculating the subsequent path label set of each node is as follows: if node v is the primary output, a set is generated at node v

Optionally, the method for calculating the preamble path label set of each node is as follows: if node v is the primary input, a set is generated on node v

If node v is not the primary input, then for each predecessor edge (u, v) a set R' of v is computed, denoted as: r ' ═ R ═ f (u)), (u, v), and if R ' _ t (v) is not dominated by the dummy path, then add R ' to the overall set of preamble path labels for node v; where f (v) represents a set of all constraints starting from the node v, t (v) represents a set of all constraints ending from the node v, and I (u, v) represents a set of all constraints covering the edge (u, v).

The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment may be applied to the present embodiment, and the technical details in the present embodiment may also be applied to the first embodiment.

The following is a brief introduction to some of the related art involved in the embodiments of the present application:

static timing analysis is a key technology widely adopted in electronic design automation and used for verifying whether the pace of a data link signal and a clock signal in a synchronous timing circuit is consistent or not; it verifies that the method comprises: the time delay from the main input to the main output, from the output end of the time sequence device to the input end of the time sequence device, from the main input to the input end of the time sequence device (trigger), from the output end of the time sequence device to the main output, and the verification result is fed back to the optimization tool to ensure that the data paths are not too long and too short, and the time delay method ensures that the data signals in the four paths can be effectively sampled and accurately transmitted by clock signals. The length of the data path is usually indicated by the size of the delay. According to the maximum and minimum delays of the input end, the clock period, the establishment time constraint and the maintenance time constraint provided by the time sequence constraint, an algorithm firstly conducts forward scanning traversal on the time sequence diagram (such as the output of a trigger to a lower-level trigger) to obtain the arrival time of each node in the diagram, then conducts backward scanning traversal on the time sequence diagram (such as the input of the trigger to an upper-level trigger) to obtain the required time of each node, and finally subtracts the arrival time from the required time to obtain the delay margin of each node (from [ Robert B.Hitchcock. Timing Verification and the Timing Analysis program.19conference decision Automation,1982 ]), wherein for the establishment time constraint, if the delay margin is a negative value, the path through which a signal reaches the point is over long, optimization is needed, and the delay margin is enabled to be positive. For the hold time constraint, if the delay margin is positive, indicating that the path taken by the signal to reach this point is too short, it needs to be optimized and made negative. The process of traversing the timing graph for the delay margin for the forward and backward scans need not be concerned with the specific logical behavior represented by the timing graph. However, in actual circuits, some data paths may not be logically present at all and their delays should not be considered, possibly due to mutual exclusion of combinational logic or user specification without concern for delays in paths between particular nodes. We call these paths dummy paths. The unnecessary time delay is doped in the time sequence analysis, which may cause the circuit time sequence to be over conservative, the working frequency to be reduced, and the performance to be influenced. Therefore, spurious paths must be discarded. Belkhale, A.J.Suess.timing analysis with a knock down false sub-graph, IEEE/ACM International Conference on Computer-aid designed, 1995 ] proposes a method of generating labels to distinguish false paths based on set calculations. The method dynamically generates labels to separate out the false paths in the time sequence analysis process. Eventually, all spurious paths are cleared and all correct paths are covered. The labels and the special constraints have corresponding relations, and one label corresponds to one or more constraints. As the scale of the timing circuit increases and the complexity of the timing constraint increases, the number of tags attached to each node in the timing graph increases significantly. Meanwhile, the label on the current node is determined by the label on the predecessor node and the constraint quantity covering the current node. Thus, as the scan progresses further, the number of labels per node that the tool needs to process increases dramatically, and processing efficiency decreases. Through analysis, timing information of the tail of many paths (from the current node to the main output or the input end of the trigger) is shared for the current node traversed. Therefore, a plurality of labels representing different constraints on the current node can be combined and propagated, and the analysis efficiency is improved. [ Shuo Zhou. static Timing Analysis in VLSI design. university of California at San Diego, Electronic thesis and relationships, 2006 ] proposed a method of merging tags and dissemination. In addition, the method also proposes the processing of multi-cycle paths-the multi-cycle paths and dummy paths are represented indifferently by labels, but differentiated by priority and time offset. The dummy path has a higher priority than the multicycle path. And when the scanning traverses to the end point of the path, settlement is carried out and whether the current path is dominated by the false path or not is judged. If dominated by false paths, the current path is discarded. Otherwise, judging whether the multi-cycle path exists or not and correspondingly settling the delay allowance.

Timing constraints, such as dummy paths and multi-cycle paths, are ultimately mapped to a directed acyclic graph. The directed acyclic graph is a subgraph of the whole circuit timing diagram, and one constraint corresponds to one subgraph. In order to uniformly process the false path and the multi-cycle path in the prior art, a subgraph corresponding to the false path is intentionally expanded in a preprocessing stage. The main input node set of the expanded subgraph is a subset of the main input node set of the whole time sequence chart, and the main output node set is a subset of the main output node set of the whole time sequence chart. Because the original subgraph corresponding to the constraint is usually very small in size (if the false path constraint indicates that "the path through a certain pin of a certain logic device is a false path", the original subgraph corresponding to the false path constraint has only 1 node and a plurality of edges), the new subgraph after the extension comprises a large number of upstream and downstream nodes of the node, so that the size of the graph can be increased by multiple times or even by multiple times, and the very large memory overhead is caused by the following steps: a) the number of nodes and the number of edges of the subgraph can be increased by multiple times or even tens of times after expansion; the space requirement for expressing the expanded subgraph is increased in the same proportion; b) the total amount of labels in the whole program analysis process is positively correlated with the scale of all sub-graphs corresponding to the constraints. The size of the subgraph is increased significantly, which results in the increase of the number of labels on each node in the scanning traversal process, and the increase may be increased continuously with the depth of the traversal. The decisions are made when the forward scan traverses the entire timing diagram to the primary output node.

It should be noted that, as will be understood by those skilled in the art, the implementation functions of the modules shown in the above embodiments of the memory-optimized static timing analysis system can be understood by referring to the related description of the memory-optimized static timing analysis system. The functions of the modules shown in the embodiment of the memory-optimized static timing analysis system may be implemented by a program (executable instructions) running on a processor, or may be implemented by specific logic circuits. The memory optimization type static timing analysis system in the embodiment of the present application, if implemented in the form of a software function module and sold or used as an independent product, may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

Accordingly, the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the computer-executable instructions implement the method embodiments of the present application. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable storage medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

In addition, the embodiment of the present application further provides a memory-optimized static timing analysis system, which includes a memory for storing computer-executable instructions, and a processor; the processor is configured to implement the steps of the method embodiments described above when executing the computer-executable instructions in the memory. The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or the like. The aforementioned memory may be a read-only memory (ROM), a Random Access Memory (RAM), a Flash memory (Flash), a hard disk, or a solid state disk. The steps of the method disclosed in the embodiments of the present invention may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

All documents mentioned in this application are to be considered as being incorporated in their entirety into the disclosure of this application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

Claims

1. A memory optimization type static time sequence analysis method is characterized by comprising the following steps:

acquiring a circuit netlist to construct a timing diagram;

according to the bipartite graph of each node, performing bipartite group covering on each label of each node to reduce the total quantity of labels, wherein during the bipartite group covering, various multi-cycle path constraints required by different cycles are identified, and if a plurality of multi-cycle path constraints exist, the multi-cycle path constraints with the same cycle number are covered by the same bipartite group;

2. The memory-optimized static timing analysis method according to claim 1, wherein the calculating a delay margin corresponding to each tag on each node and generating a timing analysis report further comprises:

3. The memory-optimized static timing analysis method of claim 1, wherein obtaining the circuit netlist to construct the timing diagram further comprises: a circuit netlist is obtained to construct an overall timing diagram, and a partial timing diagram is constructed according to specified timing constraints.

4. The memory-optimized static timing analysis method according to claim 1, wherein in the process of the forward traversal scan timing chart, the intersection operation is performed on the preceding path label set and the following path label set while the forward traversal scan passes through each node;

the constructing the bipartite graph of each node according to the intersection operation result further comprises: and obtaining all path information passing through each node according to the intersection operation, and constructing a bipartite graph of each node according to the path information.

5. The memory-optimized static timing analysis method according to claim 1, wherein each node has at least one tag, and each tag corresponds to a timing constraint;

and dynamically and differentially processing various time sequence constraints on each node when the two-cluster covering is carried out on each label of each node.

6. The memory-optimized static timing analysis method of claim 1, wherein the backward traversal scan timing graph to obtain a subsequent path label set for each node further comprises: calculating a subsequent path label set of each node according to a first method; the first method further comprises: if node v is the primary output, a set is generated at node v

the method for determining whether the R '# T (v) and the R' # F (v) are dominated by the dummy path is as follows: if false path constraint exists in the obtained intersection, judging that the preorder path or the postorder path is given to the leading path by the false path; where f (v) represents a set of all constraints starting from the node v, t (v) represents a set of all constraints ending from the node v, and I (u, v) represents a set of all constraints covering the edge (u, v).

7. A memory-optimized static timing analysis system, comprising:

the calculation module is used for backward traversing and scanning the time sequence diagram to obtain a subsequent path label set of each node, forward traversing and scanning the time sequence diagram to obtain a preamble path label set of each node, performing intersection operation on the preamble path label set and the subsequent path label set to obtain bipartite graph representation corresponding to the intersection of the sets on each node, and performing bipartite group covering on each label of each node to obtain a label on each node, wherein in the backward traversing and forward traversing scanning processes, a false path is immediately identified and the label corresponding to the false path is discarded, and when the bipartite group is covered, various multi-cycle path constraints required by different cycles are identified, and if a plurality of multi-cycle path constraints exist, the multi-cycle path constraints with the same cycle number are covered by the same bipartite group;

8. The memory-optimized static timing analysis system of claim 7, wherein the calculating the set of next path labels for each node is performed by a first method; the first method further comprises: if node v is the primary output, a set is generated at node v

the calculation of the preamble path label set of each node is performed according to a second method; the secondThe method further comprises the following steps: if node v is the primary input, a set is generated on node v

9. A bolus covering system, comprising:

a processor for implementing the steps in the method of any one of claims 1 to 6 when executing the computer-executable instructions.

10. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the steps in the method of any one of claims 1 to 6.