CN113392608B - Circuit generation method, circuit generation device, electronic equipment and storage medium - Google Patents
Circuit generation method, circuit generation device, electronic equipment and storage medium Download PDFInfo
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- CN113392608B CN113392608B CN202110714002.7A CN202110714002A CN113392608B CN 113392608 B CN113392608 B CN 113392608B CN 202110714002 A CN202110714002 A CN 202110714002A CN 113392608 B CN113392608 B CN 113392608B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
Abstract
One or more embodiments of the application disclose a circuit generation method, a circuit generation device, electronic equipment and a storage medium, which relate to the technical field of integrated circuits and are invented for improving the reliability of products. The circuit generation method comprises the following steps: obtaining a standard unit time sequence library, a circuit constraint file of a target circuit and circuit description, wherein the standard unit time sequence library comprises the time delay of a standard unit and the aging time delay parameter of the standard unit, and the aging time delay parameter is used for representing the influence of aging on the time delay of the standard unit; selecting a target standard unit in the standard unit time sequence library according to the circuit constraint file, the circuit description, the delay of the standard unit and the ageing delay parameter; and synthesizing a logic circuit according to the target standard unit and the circuit description to obtain a circuit netlist. The embodiment of the application is suitable for the design of integrated circuits.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a circuit generating method, a circuit generating device, an electronic device, and a storage medium.
Background
Currently, with the progressive development of CMOS (Complementary Metal Oxide Semiconductor ) technology, CMOS devices are also gradually reduced in size. Although the operating voltage of the device is also decreasing, the device size is even more reduced than the operating voltage, and as a result, the device ages, new dominant mechanisms are also gradually emerging. NBTI (Negative Bias Temperature Instability ) and HCI (Hot Carriers Injection, hot electron injection) occur from abrupt, permanent dielectric breakdown and electromigration.
At present, a certain measure can be adopted to compensate the influence of device aging on a circuit, for example, a certain time redundancy (timing margin) is increased to ensure that the time sequence can still meet the requirement after the device aging. However, the increased amount of time redundancy may occur in a smaller (under-estimate) or larger (over-estimate) situation. The circuit can fail after the device is aged due to small time redundancy; the larger time redundancy is to predict the timing advance after the aging of the device, so that on one hand, a larger cost is required to meet the timing, and on the other hand, a part of PPA (Power, performance, area, power consumption, performance and area of the design) of the circuit is also sacrificed. It can be seen that the problem of influence of device aging on the circuit is solved by increasing the time redundancy, and the problem that the increased time redundancy is smaller or larger can occur.
Disclosure of Invention
In view of this, one or more embodiments of the present application provide a circuit generating method, apparatus, electronic device, and storage medium, which can improve product reliability.
One or more embodiments of the present application provide a circuit generating method including: obtaining a standard unit time sequence library, a circuit constraint file of a target circuit and circuit description, wherein the standard unit time sequence library comprises the time delay of a standard unit and the aging time delay parameter of the standard unit, and the aging time delay parameter is used for representing the influence of aging on the time delay of the standard unit; selecting a target standard unit in the standard unit time sequence library according to the circuit constraint file, the circuit description, the delay of the standard unit and the ageing delay parameter; and synthesizing a logic circuit according to the target standard unit and the circuit description to obtain a circuit netlist.
Optionally, the method further comprises: before a standard unit time sequence library, a circuit constraint file of a target circuit and a circuit description are acquired, performing aging simulation of a preset aging mechanism on each standard unit in the standard unit time sequence library according to preset simulation conditions, preset transition time and preset load capacitance to obtain aging delay parameters of each standard unit.
Optionally, the method further comprises: and after logic circuit synthesis is carried out according to the target standard unit and the circuit description to obtain a circuit netlist, carrying out circuit layout planning according to the standard unit time sequence library, the circuit constraint file and the circuit netlist to obtain a circuit layout, wherein in the layout planning process, the size and the position of each circuit module in the circuit layout are determined according to the delay of the standard unit and the ageing delay parameter.
Optionally, the method further comprises: and performing layout winding of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit layout after performing layout planning of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit netlist, wherein in the layout winding process, the winding of the target circuit is determined according to the time delay of the standard unit, the ageing time delay parameter and the time sequence requirement of the target circuit.
Optionally, the method further comprises: after the layout of the circuit is wound according to the circuit constraint file, the standard unit time sequence library and the circuit layout, signing the circuit layout after the layout is wound according to the circuit constraint file and the aging delay parameter, wherein in the signing process of the circuit layout after the layout is wound, whether the time sequence requirement of the target circuit is met after the key path in the target circuit is aged or not is determined according to the aging delay parameter.
Optionally, the method further comprises: and in response to detecting that a first standard cell which does not meet the time sequence requirement after the critical path is aged exists in the circuit layout subjected to the signing, preferentially selecting a second standard cell which is insensitive to aging and meets the same function as the first standard cell from the standard cell time sequence library to replace the first standard cell.
Optionally, selecting a target standard cell according to the circuit constraint file, the circuit description and the standard cell timing library includes: according to the circuit constraint file, the circuit description and the standard cell timing sequence library, a standard cell which is not aged and has delay meeting the timing sequence requirement of a critical path in the target circuit and is insensitive to aging is preferentially selected to be used as the target standard cell at a critical node in the critical path; or according to the circuit constraint file, the circuit description and the standard cell timing library, preferentially selecting the standard cell with time delay meeting the timing requirement of the target circuit and small area and/or power consumption after aging as the target standard cell at the key node in the key path.
Optionally, the preset simulation conditions at least include one of the following: process conditions, voltage conditions and temperature conditions PVT, input excitation signals, and aging time.
Optionally, the aging delay parameter includes at least one of: the method comprises the steps of delaying after standard unit aging, delaying the difference between the delaying after standard unit aging and delaying before standard unit aging, and delaying the aging ratio factor of the standard unit, wherein the aging ratio factor is equal to the ratio of the delaying before standard unit aging to the delaying after standard unit aging, or the aging ratio factor is equal to the ratio of the delaying after standard unit aging to the delaying before standard unit aging.
Optionally, the preset aging mechanism includes: hot electron injection HCI or negative bias temperature instability NBTI.
One or more embodiments of the present application also provide a circuit generating apparatus including: the acquisition module is configured to acquire a standard unit time sequence library, a circuit constraint file of a target circuit and a circuit description, wherein the standard unit time sequence library comprises standard unit time delay and standard unit aging time delay parameters, and the aging time delay parameters are used for representing the influence of aging on the standard unit time delay; a selection module configured to select a target standard cell in the standard cell timing library based on the circuit constraint file, the circuit description, the delay of the standard cell, and the aging delay parameter; and the synthesis module is configured to perform logic circuit synthesis according to the target standard unit and the circuit description to obtain a circuit netlist.
Optionally, the apparatus further includes: the simulation module is configured to perform aging simulation of a preset aging mechanism on each standard unit in the standard unit time sequence library according to preset simulation conditions, preset transition time and preset load capacitance before acquiring the standard unit time sequence library, a circuit constraint file of a target circuit and circuit description, so as to obtain aging delay parameters of each standard unit.
Optionally, the apparatus further includes: and the synthesis module is configured to synthesize a logic circuit according to the target standard unit and the circuit description, and then, perform layout planning of a circuit according to the standard unit time sequence library, the circuit constraint file and the circuit netlist to obtain a circuit layout, wherein in the layout planning process, the size and the position of each circuit module in the circuit layout are determined according to the delay of the standard unit and the ageing delay parameter.
Optionally, the apparatus further includes: and the layout module is configured to perform layout winding of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit layout after performing layout planning of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit netlist, wherein in the layout winding process, the winding of the target circuit is determined according to the time delay of the standard unit, the ageing time delay parameter and the time sequence requirement of the target circuit.
Optionally, the apparatus further includes: and the signing and checking module is configured to sign and check the circuit layout after the circuit layout is wound according to the circuit constraint file, the standard unit time sequence library and the circuit layout, and to determine whether the time sequence requirement of the target circuit is met after the key path in the target circuit is aged according to the aging delay parameter in the process of signing and checking the circuit layout after the circuit layout is wound according to the circuit constraint file and the aging delay parameter.
Optionally, the apparatus further includes: and the modification module is configured to respond to the detection that a first standard cell which does not meet the time sequence requirement after the key path is aged exists in the circuit layout subjected to signing, and preferentially select a second standard cell which is insensitive to aging and meets the same function as the first standard cell to replace the first standard cell in the standard cell time sequence library.
Optionally, the selection module is specifically configured to: and according to the circuit constraint file, the circuit description and the standard cell timing library, preferentially selecting standard cells which meet the timing requirement of a critical path in the target circuit and are insensitive to aging, or preferentially selecting standard cells which meet the timing requirement of the critical path in the target circuit and have small area and/or power consumption, according to the circuit constraint file, the circuit description and the standard cell timing library, and preferentially selecting standard cells which meet the timing requirement of the critical path in the target circuit and have small area and/or power consumption.
Optionally, the preset simulation conditions at least include one of the following: process conditions, voltage conditions and temperature conditions PVT, input excitation signals, and aging time.
Optionally, the aging delay parameter includes at least one of: the method comprises the steps of delaying after standard unit aging, delaying the difference between the delaying after standard unit aging and delaying before standard unit aging, and delaying the aging ratio factor of the standard unit, wherein the aging ratio factor is equal to the ratio of the delaying before standard unit aging to the delaying after standard unit aging, or the aging ratio factor is equal to the ratio of the delaying after standard unit aging to the delaying before standard unit aging.
Optionally, the preset aging mechanism includes: hot electron injection HCI or negative bias temperature instability NBTI.
One or more embodiments of the present application also provide an electronic device including: a processor; and a memory having stored thereon computer executable instructions which when executed by the processor are for implementing any of the circuit generation methods described above.
One or more embodiments of the present application also provide a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, are configured to implement any of the above-described circuit generation methods.
In the circuit generating method of one or more embodiments of the present application, when logic circuit synthesis is performed, a target standard cell can be selected according to a standard cell timing sequence library including an aging delay parameter of a standard cell to perform logic circuit synthesis, so as to obtain a circuit netlist, thereby realizing that in a design stage of a circuit, that is, considering the aging condition of the standard cell in the circuit, PPA of the circuit can be improved, reliability of the circuit can be improved, and design cost of the circuit can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow diagram illustrating a circuit generation method in accordance with one or more embodiments of the application;
FIG. 2 is a flow diagram illustrating a circuit generation method in accordance with one or more embodiments of the application;
FIG. 3 is a circuit design flow diagram illustrating one or more embodiments in accordance with the present application;
FIG. 4 is a circuit design flow diagram illustrating one or more embodiments in accordance with the present application;
FIG. 5 is a schematic diagram illustrating a logic circuit synthesis process in accordance with one or more embodiments of the present application;
FIG. 6A is a schematic diagram illustrating circuit paths that do not meet timing after aging in accordance with one or more embodiments of the present application;
FIG. 6B is a schematic diagram illustrating circuit paths that meet timing after aging in accordance with one or more embodiments of the present application;
FIG. 7 is a schematic diagram of a circuit generation device shown in accordance with one or more embodiments of the application;
FIG. 8 is a schematic diagram of another circuit generation device shown in accordance with one or more embodiments of the application;
fig. 9 is a schematic structural view of an electronic device according to one or more embodiments of the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
FIG. 1 is a flow diagram illustrating a method of circuit generation, as shown in FIG. 1, according to one or more embodiments of the application, the method comprising:
step 101: obtaining a standard unit time sequence library, a circuit constraint file of a target circuit and circuit description, wherein the standard unit time sequence library comprises the time delay of a standard unit and the aging time delay parameter of the standard unit, and the aging time delay parameter is used for representing the influence of aging on the time delay of the standard unit;
the standard units may include inverters, buffers, and gates, or gates, registers, selectors, and full adders. The standard cell timing library may include basic information of the standard cell, for example, may include timing information, area, power consumption, etc. of the standard cell, where the timing information includes timing and aging delay parameters of the standard cell, and the delay of the standard cell refers to an unaged delay of the standard cell, and the aging delay parameter may be a parameter that reflects an influence of aging on the delay of the standard cell. The circuit constraint file may be, for example, an SDC (Synopsys Design Constraint, logic integrated design constraint) file that constrains the timing, area, and power consumption of the circuit. The circuit description may be, for example, a circuit description of RTL (Register-Transfer Level). The target circuit may be, for example, an integrated circuit that is applied to a certain occasion to realize a specified function. Before the target circuit is generated, specifications such as functions, operation speed, interface specification, ambient temperature, power consumption and the like of the target circuit can be set according to the application occasion of the target circuit and the functions to be realized, so as to be used as design basis of the target circuit.
Step 102: selecting a target standard unit in the standard unit time sequence library according to the circuit constraint file, the circuit description, the delay of the standard unit and the ageing delay parameter;
the target standard cell may be, for example, a standard cell at a critical node in each critical path of the target circuit.
Step 103: and synthesizing a logic circuit according to the target standard unit and the circuit description to obtain a circuit netlist.
For example, logic synthesis (Logic synthesis) may be performed by a hardware description language synthesizer (synthesizer) according to the circuit constraint file and the circuit description, and the synthesis may be abbreviated as "synthesis" hereinafter, to generate a net list (net list) of Logic circuits, and the circuit netlist may be abbreviated as "circuit netlist" hereinafter.
In the circuit generating method of one or more embodiments of the present application, when logic circuit synthesis is performed, a target standard cell can be selected to perform logic circuit synthesis according to a standard cell timing sequence library including an aging delay parameter of a standard cell and a standard cell delay, so as to obtain a circuit netlist, thereby realizing that in a design stage of a circuit, that is, considering an aging condition of a standard cell in the circuit, PPA of the circuit can be improved, reliability of the circuit can be improved, and design cost of the circuit can be reduced.
FIG. 2 is a flow diagram of a circuit generation method according to one or more embodiments of the present application, as shown in FIG. 2, which may further include, based on the circuit generation method shown in FIG. 1:
step 201: before a standard unit time sequence library, a circuit constraint file of a target circuit and a circuit description are acquired, performing aging simulation of a preset aging mechanism on each standard unit in the standard unit time sequence library according to preset simulation conditions, preset transition time and preset load capacitance to obtain aging delay parameters of each standard unit. For example, a plurality of sets of combinations of different transition times and load capacitances are preset, and a plurality of sets of simulation conditions (which is an example of the preset simulation conditions) are preset, wherein one transition time value and one load capacitance value are included in one transition time and load capacitance combination; parameters corresponding to a plurality of different simulation conditions can be included in a set of simulation conditions, for example, the types of the simulation conditions in the set of simulation conditions include: at least one of PVT (Process, voltage, temperature, process, voltage and temperature conditions), stimulus signal (stimulus) and aging time, where the set of simulation conditions includes the three simulation conditions, the set of simulation conditions may include PVT parameters, parameters of stimulus signal and aging time parameters. Preset aging mechanisms include, but are not limited to, NBTI and HCI.
The process of obtaining the aging delay parameter of the standard cell is exemplarily described below with reference to fig. 3. As shown in fig. 3, under the simulation conditions of PVT (process, voltage, temperature conditions) 301, input excitation signal 302, and aging time 303, for example, considering aging mechanisms NBTI and HCI, performing SPICE (Simulation Program with Integrated Circuit Emphasis, simulation circuit simulator) 307 simulation on standard cells under the combination of different transition times 305 and load capacitors 306 by using an aging model 304 to obtain aging delay parameters of the standard cells, after obtaining the aging delay parameters of each standard cell in the standard cell timing library in this way, adding the aging delay parameters of each standard cell to the standard cell timing library to obtain a standard cell timing library 308 containing the aging delay parameters of the standard cells, where the standard cell timing library includes the aging delay parameters reflecting the effect of aging on the standard cell delay and the aging delay of the standard cells, for example, the aging delay of each standard cell is reflected in the aging effect of the standard cell timing library; the time delay condition of each standard cell after aging under the conditions of a certain transition time and a load capacitance can be included, and the time delay condition of each standard cell under a certain input logic level (which is an example of the input excitation signal) can be included, for example, the time delay of some standard cells is even reduced or even negative under a certain input logic level, and even the aging ratio factor of the standard cells is negative.
Based on a standard unit time sequence library containing the standard unit aging delay parameters, the aging delay parameters of the standard unit can be searched and determined under the conditions of a certain PVT, an input excitation signal, transition time and a load capacitor. For example, a NAND gate NAND1 (which is an example of the standard cell) has an input transition time t under a certain PVT and input excitation signal condition r When the load capacitance is C, according to t r C, inquiring a standard unit time sequence base to obtain time delay t d . And after five years of aging of the standard cell, at the same t r And C, under the condition of carrying out standard unit aging simulation, obtaining the time delay t of the standard unit after aging age . In general, t age ＞t d I.e. the delay of the standard cell is deteriorated.
It should be noted that the simulation conditions described above may not be limited to PVT, input stimulus signal, aging time, and aging model, but may include other factors 309 related to standard cell aging.
After obtaining the standard cell timing library containing the standard cell aging delay parameters, the timing library can be applied to the entire process of the circuit design shown in fig. 4, and the process includes step 401: inputting circuit description, circuit constraint files and standard unit time sequence library; step 402: synthesizing a logic circuit; step 403: layout planning (floor plan) of the circuit; step 404: layout routing (placement & route) of the circuit; step 405: sign-off (sign-on) of the circuit, if the sign-off is passed, executing step 407, otherwise executing step 406; step 406: modification in the design process of the circuit (ECO); step 407: a tape out).
The above-described circuit generating method is exemplified below with reference to fig. 5 by taking the logic circuit synthesis based on the above-described aging delay parameter (the logic circuit synthesis can be realized by the synthesis tool in EDA according to the embodiment of the present application, so in this example, the logic circuit synthesis is referred to as synthesis).
In this example, the circuit design flow shown in fig. 4 may be implemented by an EDA (Electronics Design Automation, electronic design automation) tool. As shown in fig. 5, at the synthesis stage of circuit design based on EDA tools, an input file 501 of a synthesis tool 502 (for logic circuit synthesis) includes: circuit constraint file, circuit description. Wherein the aging delay parameter exists in the standard cell timing library 503. In the synthesis stage, an optimization engine 505 for considering aging of standard units is added on the basis of a PPA optimization engine 504, the optimization engine 505 can optimally select standard units of certain nodes in a critical path of a target circuit according to aging delay parameters of the standard units through a preset algorithm, for example, standard units which still can meet the requirement of circuit time sequence after aging can be selected according to the delay of the standard units after aging. After the standard cells of the circuit are selected, the standard cells are synthesized based on the selected standard cells to obtain a circuit netlist 506, and the circuit netlist, a standard cell timing library and a circuit constraint file can be used as inputs of a layout winding stage, and a PR (layout winding) tool performs layout winding of the circuit according to the inputs. It is contemplated that circuit netlist 506 synthesized based on aging delay parameters of standard cells may be structurally different from a circuit netlist synthesized without considering aging delay parameters of standard cells. The circuit netlist 506 satisfies the timing requirements of the target circuit before standard cell burn-in, satisfies the timing requirements of the target circuit after standard cell burn-in, and satisfies the PPA requirements of the target circuit.
The application of the above-described timing library at each stage of circuit design will be described one by one.
In one or more embodiments of the present application, the circuit generating method may further include: and after logic circuit synthesis is carried out according to the target standard unit and the circuit description to obtain a circuit netlist, carrying out circuit layout planning according to the standard unit time sequence library, the circuit constraint file and the circuit netlist to obtain a circuit layout, wherein in the layout planning process, the size and the position of each circuit module in the circuit layout are determined according to the delay of the standard unit and the ageing delay parameter. In the layout planning process of the circuit, the logic circuit obtained by synthesizing the logic circuit is divided into a plurality of circuit modules, and the size of each circuit module and/or the placement position of each circuit module in the circuit layout are/is influenced by the time delay of the target standard unit in each circuit module after aging, so that the size and the position of each circuit module are determined according to the aging time delay parameters of the standard unit in the layout planning process of the circuit, the layout planning of the circuit is realized under the guidance of the aging time delay parameters of the standard unit, the circuit still meets the time sequence requirement even after the standard unit is aged, and the reliability of the circuit is improved.
In one or more embodiments of the present application, the circuit generating method may further include: and performing layout winding of the circuit according to the circuit constraint file, the circuit description, the standard unit time sequence library and the circuit layout after performing layout planning of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit netlist, wherein in the layout winding process, the winding of the target circuit is determined according to the delay of the standard unit, the ageing delay parameter and the time sequence requirement of the target circuit. The layout routing of the circuit may include, for example, interconnections between circuit modules and interconnections within the modules. Because the wiring among the circuit modules can influence the delay of the paths, when the layout wiring of the circuit is carried out, the wiring among the circuit modules can be determined according to the delay after the aging of the standard unit and the criterion that the time sequence after the aging of the standard unit still can meet the time sequence requirement of the circuit.
In one or more embodiments of the present application, the circuit generating method may further include: after the layout of the circuit is wound according to the circuit constraint file, the standard unit time sequence library and the circuit layout, the circuit layout after the layout is wound is checked according to the circuit constraint file and the aging delay parameter, wherein in the process of checking the circuit layout after the layout is wound, whether the time sequence requirement of the target circuit is met after the key path in the target circuit is aged or not can be determined according to the aging delay of the standard unit. For example, according to the requirement on the service life of the target circuit, whether the standard unit of the key node in the key path of the target circuit can still meet the time sequence requirement of the target circuit after corresponding aging life is judged, if not, the sign-on is determined to be not passed, and if so, the sign-on is determined to be passed. Based on the method, the target circuit can meet the requirement of the product on the practical service life.
In one or more embodiments of the present application, the circuit generating method may further include: and in response to detecting that a first standard cell which does not meet the time sequence requirement after the critical path is aged exists in the circuit layout subjected to the signing, preferentially selecting a second standard cell which is insensitive to aging and has the same function as the first standard cell from the standard cell time sequence library to replace the first standard cell. For example, after signing the circuit layout, a stage of ECO (Engineering Change Order, modification in the design process) of the circuit design may be entered, in the ECO stage, whether a standard cell which does not meet the circuit timing requirement after ageing exists in a critical path of the target circuit may be detected, if it is determined that a first standard cell which does not meet the circuit timing requirement after ageing exists in the path is determined, based on a transition time and a load capacitance given by a node where the first standard cell is located, a second standard cell which achieves the same function as the first standard cell and is insensitive to ageing may be selected from the standard cell timing library to replace the first standard cell in the circuit layout, so that the path meets the circuit timing requirement before and after ageing of the standard cell, and the circuit layout may be signed. The standard cell insensitive to aging may be, for example, a standard cell whose delay time after aging and before aging does not change much, the degree of sensitivity to aging may be represented by, for example, a difference between a delay time after aging and a delay time before aging of the standard cell, or may be represented by a ratio of the difference to the delay time before aging, or a ratio of the delay time after aging of the standard cell to the delay time before aging of the standard cell, and the degree of sensitivity to aging of the standard cell may be, for example, referred to as an aging ratio factor. In one example, in the path shown in fig. 6A, the delay time of the NAND gate NAND1 after aging is 6ps, and the delay time after aging becomes 20ps, resulting in that the path does not satisfy the timing requirement. As shown in the path of fig. 6B, NAND gate NAND2 with the same function as NAND1 can be selected, and the delay of NAND2 after aging is 7ps, and the delay after aging is 12ps, so that the path meets the timing requirement before and after aging of the device.
In one or more embodiments of the present application, selecting a target standard cell in the standard cell timing library according to the circuit constraint file, the circuit description, and the aging delay parameter may include:
and preferentially selecting the standard units which have delay meeting the time sequence requirement of the critical path in the target circuit and are insensitive to aging as target standard units at the critical nodes in the critical path according to the circuit constraint file, the circuit description and the standard unit time sequence library. For example, if there are a plurality of standard cells whose delay time satisfies the timing requirement of a critical path when no aging occurs, the standard cell with the smallest aging ratio factor among the plurality of standard cells may be selected as the target standard cell disposed at the critical node in the critical path. On the basis that the time delay when aging does not occur meets the time sequence requirement, the standard units insensitive to aging are preferably selected to synthesize the logic circuits, so that the whole circuit is less influenced by the aging of the individual standard units.
In one or more embodiments of the present application, selecting a target standard cell based on the circuit constraint file, the circuit description, and the standard cell timing library may include:
And preferentially selecting the standard cells with time delays meeting the time sequence requirements of the critical paths in the target circuit and small area and/or power consumption as the target standard cells at the critical nodes in the critical paths according to the circuit constraint file, the circuit description and the standard cell time sequence library. For example, a standard cell whose aged delay satisfies the timing requirement of the critical path and whose area and power consumption are both small may be preferentially selected in the standard cell timing library as the target standard cell at the critical node in the critical path, or a standard cell whose aged delay satisfies the timing requirement of the critical path and whose area or power consumption is small may be preferentially selected in the timing of the standard cell as the target standard cell at the node. Based on the method, the circuit can reach the optimal PPA while the service life of the circuit is ensured, and the reliability of the circuit is improved.
The standard cell timing library may include parameters such as timing before aging, timing after aging, aging ratio factor, area, and power consumption of each standard cell.
In one or more embodiments of the application, the aging delay parameter may include at least one of:
Delay after standard cell aging, difference between delay after standard cell aging and delay before standard cell aging, and standard cellWherein the burn-in ratio factor is equal to the ratio of the difference to the delay before aging of the standard cell. Let the delay before aging of a standard cell be denoted as t d The time delay after aging is denoted as t age The above difference is denoted t age -t d The above aging scale factor is expressed as η= (t age -t d )/t d Or as η=t age /t d . The standard cell timing library may include t d 、t age -t d Or η.
Fig. 7 is a schematic diagram of a circuit generating apparatus according to one or more embodiments of the present application, and as shown in fig. 7, the apparatus 70 includes:
an obtaining module 71, configured to obtain a standard cell timing library, a circuit constraint file of a target circuit, and a circuit description, where the standard cell timing library includes a delay of a standard cell and an aging delay parameter of the standard cell, where the aging delay parameter is used to represent an effect of aging on the delay of the standard cell;
a selection module 72 configured to select a target standard cell in the standard cell timing library based on the circuit constraint file, the circuit description, the delay of the standard cell, and the aging delay parameter;
And a synthesis module 73 configured to perform logic circuit synthesis according to the target standard cell and the circuit description to obtain a circuit netlist.
Fig. 8 is a schematic structural diagram of another circuit generating device according to one or more embodiments of the present application, and as shown in fig. 8, the device may further include, on the basis of the device shown in fig. 7:
the simulation module 81 is configured to perform an aging simulation of a preset aging mechanism on each standard cell in the standard cell timing library according to a preset simulation condition, a preset transition time and a preset load capacitance before acquiring the standard cell timing library, a circuit constraint file of a target circuit and a circuit description, so as to obtain an aging delay parameter of each standard cell.
In one or more embodiments of the present application, the circuit generating apparatus may further include: and the synthesis module is configured to synthesize a logic circuit according to the target standard unit and the circuit description, and then, perform layout planning of a circuit according to the standard unit time sequence library, the circuit constraint file and the circuit netlist to obtain a circuit layout, wherein in the layout planning process, the size and the position of each circuit module in the circuit layout are determined according to the delay of the standard unit and the ageing delay parameter.
In one or more embodiments of the present application, the circuit generating apparatus may further include: and the layout module is configured to perform layout winding of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit layout after performing layout planning of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit netlist, wherein in the layout winding process, the winding of the target circuit is determined according to the time delay of the standard unit, the ageing time delay parameter and the time sequence requirement of the target circuit.
In one or more embodiments of the present application, the circuit generating apparatus may further include: and the signing and checking module is configured to sign and check the circuit layout after the circuit layout is wound according to the circuit constraint file, the standard unit time sequence library and the circuit layout, and to determine whether the time sequence requirement of the target circuit is met after the key path in the target circuit is aged according to the aging delay parameter in the process of signing and checking the circuit layout after the circuit layout is wound according to the circuit constraint file and the aging delay parameter.
In one or more embodiments of the present application, the circuit generating apparatus may further include: and the modification module is configured to respond to the detection that a first standard cell which does not meet the time sequence requirement after the key path is aged exists in the circuit layout subjected to signing, and preferentially select a second standard cell which is insensitive to aging and meets the same function as the first standard cell to replace the first standard cell in the standard cell time sequence library.
In one or more embodiments of the present application, the selection module may be specifically configured to: and preferentially selecting the standard units which have delay meeting the time sequence requirement of the critical path in the target circuit and are insensitive to aging according to the circuit constraint file, the circuit description and the standard unit time sequence library when aging does not occur, and taking the standard units as target standard units at critical nodes in the critical path.
In one or more embodiments of the present application, the selection module may be specifically configured to: and preferentially selecting the standard cells with time delays meeting the time sequence requirements of the critical paths in the target circuit and small area and/or power consumption as the target standard cells at the critical nodes in the critical paths according to the circuit constraint file, the circuit description and the standard cell time sequence library.
In one or more embodiments of the present application, the preset simulation conditions may include at least one of: process conditions, voltage conditions and temperature conditions PVT, input excitation signals, and aging time.
In one or more embodiments of the application, the aging delay parameter may include at least one of: the method comprises the steps of delaying after standard unit aging, delaying the difference between the delaying after standard unit aging and delaying before standard unit aging, and delaying the aging ratio factor of the standard unit, wherein the aging ratio factor is equal to the ratio of the delaying before standard unit aging to the delaying after standard unit aging, or the aging ratio factor is equal to the ratio of the delaying after standard unit aging to the delaying before standard unit aging.
In one or more embodiments of the application, the pre-set aging mechanism includes, but is not limited to: hot electron injection HCI or negative bias temperature instability NBTI.
One or more embodiments of the present application provide an electronic device including: a processor; and a memory having stored thereon computer executable instructions which when executed by the processor are for implementing any of the circuit generation methods described above.
One or more embodiments of the present application provide a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, are for implementing a circuit generation method as any one of the above.
Fig. 9 shows a schematic structural diagram of an electronic device according to one or more embodiments of the present application, which may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 implement communication connections therebetween within the device via a bus 1050.
The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.
The Memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 1020 may store an operating system and other application programs, and when the embodiments of the present specification are implemented in software or firmware, the associated program code is stored in memory 1020 and executed by processor 1010.
The input/output interface 1030 is used to connect with an input/output module for inputting and outputting information. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
Communication interface 1040 is used to connect communication modules (not shown) to enable communication interactions of the present device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
Bus 1050 includes a path for transferring information between components of the device (e.g., processor 1010, memory 1020, input/output interface 1030, and communication interface 1040).
It should be noted that although the above-described device only shows processor 1010, memory 1020, input/output interface 1030, communication interface 1040, and bus 1050, in an implementation, the device may include other components necessary to achieve proper operation.
Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
For convenience of description, the above apparatus is described as being functionally divided into various units/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present application.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (18)
1. A circuit generation method, comprising:
obtaining a standard unit time sequence library, a circuit constraint file of a target circuit and a circuit description, wherein the standard unit time sequence library comprises the delay of a standard unit and the ageing delay parameter of the standard unit, the delay of the standard unit represents the unaged delay of the standard unit, and the ageing delay parameter is used for representing the influence of ageing on the delay of the standard unit;
Selecting a target standard unit in the standard unit time sequence library according to the circuit constraint file, the circuit description, the delay of the standard unit and the ageing delay parameter;
performing logic circuit synthesis according to the target standard unit and the circuit description to obtain a circuit netlist;
wherein the selecting a target standard cell in the standard cell timing library according to the circuit constraint file, the circuit description, the delay of the standard cell, and the aging delay parameter comprises:
and selecting a standard unit which is insensitive to aging and is determined by aging delay parameters and has time delay meeting the time sequence requirement of a critical path in the target circuit when the standard unit is not aged according to the circuit constraint file, the circuit description and the standard unit time sequence library as the target standard unit.
2. The method according to claim 1, wherein the method further comprises:
before a standard unit time sequence library, a circuit constraint file of a target circuit and a circuit description are acquired, performing aging simulation of a preset aging mechanism on each standard unit in the standard unit time sequence library according to preset simulation conditions, preset transition time and preset load capacitance to obtain aging delay parameters of each standard unit.
3. The method according to claim 1, wherein the method further comprises:
and after logic circuit synthesis is carried out according to the target standard unit and the circuit description to obtain a circuit netlist, carrying out circuit layout planning according to the standard unit time sequence library, the circuit constraint file and the circuit netlist to obtain a circuit layout, wherein in the layout planning process, the size and the position of each circuit module in the circuit layout are determined according to the delay of the standard unit and the ageing delay parameter.
4. A method according to claim 3, characterized in that the method further comprises:
and performing layout winding of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit layout after performing layout planning of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit netlist, wherein in the layout winding process, the winding of the target circuit is determined according to the time delay of the standard unit, the ageing time delay parameter and the time sequence requirement of the target circuit.
5. The method according to claim 4, wherein the method further comprises:
After the layout of the circuit is wound according to the circuit constraint file, the standard unit time sequence library and the circuit layout, signing the circuit layout after the layout is wound according to the circuit constraint file and the aging delay parameter, wherein in the signing process of the circuit layout after the layout is wound, whether the time sequence requirement of the target circuit is met after the key path in the target circuit is aged or not is determined according to the aging delay parameter.
6. The method of claim 5, wherein the method further comprises:
and in response to detecting that a first standard cell which does not meet the time sequence requirement after the critical path is aged exists in the circuit layout subjected to the signing, selecting a second standard cell which is insensitive to aging and meets the same function as the first standard cell from the time sequence library of the standard cell to replace the first standard cell.
7. The method of claim 2, wherein the predetermined simulation conditions include at least one of:
process conditions, voltage conditions and temperature conditions PVT, input excitation signals, and aging time.
8. The method according to any one of claims 1 to 6, wherein the aging delay parameter comprises at least one of:
The method comprises the steps of delaying after standard unit aging, delaying the difference between the delaying after standard unit aging and delaying before standard unit aging, and delaying the aging ratio factor of the standard unit, wherein the aging ratio factor is equal to the ratio of the delaying before standard unit aging to the delaying after standard unit aging, or the aging ratio factor is equal to the ratio of the delaying after standard unit aging to the delaying before standard unit aging.
9. The method of claim 2, wherein the pre-set aging mechanism comprises:
hot electron injection HCI or negative bias temperature instability NBTI.
10. A circuit generating apparatus, comprising:
the system comprises an acquisition module, a reference unit timing sequence library, a circuit constraint file of a target circuit and a circuit description, wherein the reference unit timing sequence library comprises the delay of a reference unit and the ageing delay parameter of the reference unit, the delay of the reference unit represents the unaged delay of the reference unit, and the ageing delay parameter is used for representing the influence of ageing on the delay of the reference unit;
a selection module configured to select a target standard cell in the standard cell timing library based on the circuit constraint file, the circuit description, the delay of the standard cell, and the aging delay parameter; the selection module is specifically configured to: according to the circuit constraint file, the circuit description and the standard unit time sequence library, selecting a standard unit which is insensitive to aging and is determined by aging time delay parameters and the time delay of which is not aged meets the time sequence requirement of a critical path in the target circuit as the target standard unit;
And the synthesis module is configured to perform logic circuit synthesis according to the target standard unit and the circuit description to obtain a circuit netlist.
11. The apparatus of claim 10, wherein the apparatus further comprises:
the simulation module is configured to perform aging simulation of a preset aging mechanism on each standard unit in the standard unit time sequence library according to preset simulation conditions, preset transition time and preset load capacitance before acquiring a standard unit time sequence library, a circuit constraint file of a target circuit and a circuit description of the target circuit, so as to obtain aging delay parameters of each standard unit.
12. The apparatus of claim 10, wherein the apparatus further comprises:
and the synthesis module is configured to synthesize a logic circuit according to the target standard unit and the circuit description, and then, perform layout planning of a circuit according to the standard unit time sequence library, the circuit constraint file and the circuit netlist to obtain a circuit layout, wherein in the layout planning process, the size and the position of each circuit module in the circuit layout are determined according to the delay of the standard unit and the ageing delay parameter.
13. The apparatus of claim 12, wherein the apparatus further comprises:
and the layout module is configured to perform layout winding of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit layout after performing layout planning of the circuit according to the circuit constraint file, the standard unit time sequence library and the circuit netlist, wherein in the layout winding process, the winding of the target circuit is determined according to the time delay of the standard unit, the ageing time delay parameter and the time sequence requirement of the target circuit.
14. The apparatus of claim 13, wherein the apparatus further comprises:
and the signing and checking module is configured to sign and check the circuit layout after the circuit layout is wound according to the circuit constraint file, the standard unit time sequence library and the circuit layout, and to determine whether the time sequence requirement of the target circuit is met after the key path in the target circuit is aged according to the aging delay parameter in the process of signing and checking the circuit layout after the circuit layout is wound according to the circuit constraint file and the aging delay parameter.
15. The apparatus of claim 14, wherein the apparatus further comprises:
and the modification module is configured to respond to the detection that a first standard cell which does not meet the time sequence requirement after the key path is aged exists in the circuit layout subjected to signing, and select a second standard cell which is insensitive to aging and meets the same function as the first standard cell to replace the first standard cell in the standard cell time sequence library.
16. The apparatus according to any one of claims 10 to 15, wherein the aging delay parameter comprises at least one of:
the method comprises the steps of delaying after standard unit aging, delaying the difference between the delaying after standard unit aging and delaying before standard unit aging, and delaying the aging ratio factor of the standard unit, wherein the aging ratio factor is equal to the ratio of the delaying before standard unit aging to the delaying after standard unit aging, or the aging ratio factor is equal to the ratio of the delaying after standard unit aging to the delaying before standard unit aging.
17. An electronic device, comprising:
a processor; and
memory having stored thereon computer executable instructions for implementing the circuit generating method according to any of claims 1-9 when executed by a processor.
18. A computer-readable storage medium, having stored thereon computer-executable instructions, which when executed by a processor are for implementing the circuit generation method of any of claims 1-9.
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| CN115392166B (en) * | 2022-10-24 | 2023-01-20 | 北京智芯微电子科技有限公司 | Transistor width determination method and device, electronic equipment and medium |
| CN116467980B (en) * | 2023-06-19 | 2023-09-05 | 杭州行芯科技有限公司 | Parameter solving method of standard unit circuit, electronic equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105138769A (en) * | 2015-08-24 | 2015-12-09 | 深圳市同创国芯电子有限公司 | Timing sequence model generation method and device for programmable circuit |
| CN109710998A (en) * | 2018-02-27 | 2019-05-03 | 上海安路信息科技有限公司 | Internal memory optimization type Static Timing Analysis Methodology and its system |
| CN110915173A (en) * | 2017-07-10 | 2020-03-24 | 芬基波尔有限责任公司 | Data processing unit for computing nodes and storage nodes |
| CN111651946A (en) * | 2020-05-12 | 2020-09-11 | 江南大学 | Method for hierarchically identifying circuit gate based on workload |
| CN111898335A (en) * | 2020-06-23 | 2020-11-06 | 北京大学 | Circuit reliability analysis method |
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| CN112949233A (en) * | 2021-03-08 | 2021-06-11 | 北京士昌鼎科技有限公司 | Automatic development method and device of FPGA chip and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10073939B2 (en) * | 2015-11-04 | 2018-09-11 | Chronos Tech Llc | System and method for application specific integrated circuit design |
-
2021
- 2021-06-25 CN CN202110714002.7A patent/CN113392608B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105138769A (en) * | 2015-08-24 | 2015-12-09 | 深圳市同创国芯电子有限公司 | Timing sequence model generation method and device for programmable circuit |
| CN110915173A (en) * | 2017-07-10 | 2020-03-24 | 芬基波尔有限责任公司 | Data processing unit for computing nodes and storage nodes |
| CN109710998A (en) * | 2018-02-27 | 2019-05-03 | 上海安路信息科技有限公司 | Internal memory optimization type Static Timing Analysis Methodology and its system |
| CN111651946A (en) * | 2020-05-12 | 2020-09-11 | 江南大学 | Method for hierarchically identifying circuit gate based on workload |
| CN111898335A (en) * | 2020-06-23 | 2020-11-06 | 北京大学 | Circuit reliability analysis method |
| CN112100158A (en) * | 2020-09-21 | 2020-12-18 | 海光信息技术有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| CN112949233A (en) * | 2021-03-08 | 2021-06-11 | 北京士昌鼎科技有限公司 | Automatic development method and device of FPGA chip and electronic equipment |
Non-Patent Citations (1)
| Title |
|---|
| 徐辉.集成电路老化预测与容忍.《中国博士学位论文全文数据库（电子期刊）》.2014,I135-24. * |
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