CN112560401B - Verilog file conversion method, device, storage medium and equipment - Google Patents
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Abstract
One or more embodiments of the present invention disclose a Verilog file conversion method, device, storage medium and apparatus, the method comprising: acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to a target electronic design automation EDA tool; obtaining target codes describing logic functions from the original Verilog file; converting the target code into a target expression mode to be expressed, and obtaining a converted file; generating a first test excitation file according to the target code; according to the first test excitation file, performing simulation test on the original Verilog file and the converted file respectively to obtain a first test result; and judging whether the functions of the converted file and the original Verilog file are consistent according to the first test result, wherein the method can improve the universality of the Verilog file.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a Verilog file conversion method, device, storage medium, and apparatus.
Background
Currently, in integrated circuit design, the design process can be mainly divided into a semi-custom circuit design process and a fully custom circuit design process. The semi-custom circuit design refers to performing behavior level description of a chip by using a hardware description language (Verilog or VHDL (Very-High-Speed Integrated Circuit Hardware Description Language, very High-speed integrated circuit hardware description language)) according to a chip design specification, wherein Verilog is a hardware description language, and the structure and behavior of digital system hardware are described in a text form. And then converting the hardware description language into a gate-level netlist by using a synthesis tool, and finally carrying out a process of automatic physical design by using an automatic layout and wiring tool. In this flow, most of the steps can be automated by EDA (Electronic design automation ) tools, which can facilitate large-scale chip circuit design. In the full-custom circuit design, a circuit meeting the function is designed according to the function and performance requirements of a user, and then layout design and optimization are performed manually. In the semi-custom circuit design flow, verilog or VHDL design files are converted into a gate-level netlist through a synthesis tool, and then a final layout design is obtained through an automatic layout and wiring tool. In this flow, the Verilog design file is EDA tool compatible and correctly identifiable by the EDA tool. However, in the full custom design flow, the circuit design is directly performed without converting Verilog into a gate level netlist through a synthesis tool. In this case, verilog files are typically only used for early functional verification, and there is a high probability that it is not compatible with other EDA tools. At present, in large chip design, semi-custom circuit design and full-custom routing design are often used comprehensively, part of special IP (Intellectual Property, intellectual property module) can adopt custom circuit design flow to complete internal circuit and layout design of IP, then layout files and other design files of IP can be called for top-level design when top-level design of the chip is performed, and simultaneously Verilog files of IP can be called for top-level Verilog simulation verification and DFT (Design For Testability, testability design) when top-level design is performed. Thus, verilog of fully custom circuit design modules often fails to accommodate the subsequent process EDA tools. Even the Verilog files in a semi-custom design flow may be compatible with some EDA tools in subsequent flows, but not with other EDA tools, resulting in poor portability of the Verilog files.
Disclosure of Invention
In view of this, one or more embodiments of the present invention provide a Verilog file conversion method, apparatus, storage medium, and device that can improve the compatibility of Verilog files with EDA tools.
One or more embodiments of the present invention provide a Verilog file conversion method, including: acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to a target electronic design automation EDA tool; obtaining target codes describing logic functions from the original Verilog file; converting the target code into a target expression mode to be expressed, and obtaining a converted file;
generating a first test excitation file according to the target code; according to the first test excitation file, performing simulation test on the original Verilog file and the converted file respectively to obtain a first test result; and judging whether the functions of the converted file and the original Verilog file are consistent according to the first test result.
Optionally, the first test result includes a first signal output by a simulation tool when the original Verilog file is used for performing a simulation test, and a second signal output by the simulation tool when the converted file is used for performing the simulation test, and according to the first test result, judging whether the functions of the converted file and the original Verilog file are consistent, including: comparing the first signal with the second signal; determining that the converted file is consistent with the function of the original Verilog file in response to the first signal being consistent with the second signal; and in response to the first signal being inconsistent with the second signal, determining that the converted file is inconsistent with the original Verilog file.
Optionally, the method further comprises: modifying the configuration file in response to determining that the converted file is inconsistent with the original Verilog file in function according to the first test result; and re-acquiring target codes describing logic functions from the original Verilog file according to the modified configuration file, and converting the re-acquired target codes into the target expression mode for representation to obtain a re-converted file.
Optionally, obtaining object code describing a logic function from the original Verilog file includes: identifying codes describing logic functions from the original Verilog file; extracting the target code describing the target logic function from the identified code.
Optionally, the configuration file further includes: correspondence of logic functions to Verilog code representing the logic functions.
Optionally, identifying code describing logic functions from the original Verilog file includes: and identifying codes describing the logic function from the Verilog file according to the correspondence between the logic function and the Verilog codes used for representing the logic function.
Optionally, the method further comprises: after obtaining the target code describing the logic function from the original Verilog file, testing the original Verilog file by using a second test excitation file to obtain a second test result; determining a target logic function included in the original Verilog file according to the second test result; and determining whether the target code is correct according to the target logic function.
One or more embodiments of the present invention further provide a Verilog file conversion apparatus, including: the electronic design automation EDA tool comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is configured to acquire an original Verilog file and a configuration file, and the configuration file comprises information of a target expression mode corresponding to the target electronic design automation EDA tool; a second acquisition module configured to acquire object code describing a logic function from the original Verilog file; the first conversion module is configured to convert the target code into a representation in the target expression mode to obtain a converted file; a generation module configured to generate a first test stimulus file from the object code; the first test module is configured to perform simulation test on the original Verilog file and the converted file according to the first test excitation file to obtain a first test result; and the verification module is configured to judge whether the functions of the converted file and the original Verilog file are consistent according to the first test result.
Optionally, the first test result includes a first signal output by a simulation tool when the original Verilog file is used for performing a simulation test, and a second signal output by the simulation tool when the converted file is used for performing the simulation test, and the verification module is specifically configured to: comparing the first signal with the second signal; responding to the first signal and the second signal to determine that the converted file is consistent with the original Verilog file in function; and in response to the first signal being inconsistent with the second signal, determining that the converted file is inconsistent with the original Verilog file.
Optionally, the apparatus further includes: a modification module configured to modify the configuration file in response to determining that the converted file is inconsistent with the original Verilog file according to the first test result; and the second conversion module is configured to re-acquire the target codes describing the logic functions from the original Verilog file according to the modified configuration file, and convert the re-acquired target codes into the target expression to be expressed, so as to obtain a re-converted file.
Optionally, the second obtaining module is specifically configured to: identifying codes describing logic functions from the original Verilog file; extracting the target code describing the target logic function from the identified code.
Optionally, the configuration file further includes: correspondence of logic functions to Verilog code representing the logic functions.
Optionally, the second obtaining module is specifically configured to: and identifying codes describing the logic function from the Verilog file according to the correspondence between the logic function and the Verilog codes used for representing the logic function.
Optionally, the apparatus further includes: the second testing module is configured to test the original Verilog file by a second testing stimulus file after obtaining the target code describing the logic function from the original Verilog file, so as to obtain a second testing result; the first determining module is configured to determine a target logic function included in the original Verilog file according to the second test result; a second determination module configured to determine whether the target code is correct based on the target logic function.
One or more embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements any of the Verilog file conversion methods described above when the program is executed by the processor.
One or more embodiments of the present invention also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform any one of the Verilog file conversion methods described above.
According to the Verilog file conversion method provided by one or more embodiments of the invention, the target code describing the logic function is obtained from the Verilog file, the target code is expressed in the target expression mode corresponding to the target EDA tool in the configuration file, and whether the converted file is equivalent to the original Verilog file or not is verified through the test excitation file, so that the purpose of converting the Verilog file into the file compatible with the target EDA tool is realized, the Verilog file can be applied to various EDA tools, and the universality of the Verilog file is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow diagram illustrating a Verilog file conversion method in accordance with one or more embodiments of the present invention;
FIG. 2 is a flow diagram illustrating a Verilog file conversion method in accordance with one or more embodiments of the present invention;
FIG. 3 is a flow diagram illustrating a Verilog file conversion method in accordance with one or more embodiments of the present invention;
FIG. 4 is a schematic diagram of a Verilog file conversion apparatus shown in accordance with one or more embodiments of the present invention;
fig. 5 is a schematic structural diagram of an electronic device, shown in accordance with one or more embodiments of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
FIG. 1 is a flow diagram of a Verilog file conversion method, as shown in FIG. 1, in accordance with one or more embodiments of the present invention, the method comprising:
step 101: acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to an EDA tool;
the configuration file defines, for example, a target EDA tool required to be compatible by the Verilog file and a Verilog expression mode corresponding to the target EDA tool. For example, if the logic and function is implemented, there may be several expressions as follows:
behavior level: out=a & B;
gate level: and I1 (OUT, A, B);
or the form of primitives may be used to represent the function of the logical AND.
For another example, only a general Verilog expression may be defined in the configuration file, and then, in step 101, the Verilog file may be converted into a representation in the general Verilog expression according to the configuration file.
Step 102: obtaining target codes describing logic functions from the original Verilog file;
the logic function in one or more embodiments of the present invention may be, for example, a logic function that can be implemented by a single logic device, or may be a logic function that can be implemented by a functional unit/module formed by connecting at least two logic devices through a certain connection relationship. On the basis, an algorithm for identifying codes describing logic functions in the Verilog files can be constructed in advance, the Verilog codes corresponding to various logic devices can be predefined in the algorithm, or Verilog code segments corresponding to functional modules formed by at least two logic devices can be defined, the Verilog files are used as inputs of the algorithm, the algorithm is operated, codes describing the logic functions in the Verilog files and the logic functions described by the codes can be output, and then target codes are extracted from the output codes according to the purposes of the codes. For example, for a more complex IP module, such as a memory, when the original Verilog file is only used for the DFT design of the top layer (e.g., scan chain design), if the completed original Verilog file is used for the DFT design of the top layer, the design period will be longer, so that the Verilog logic related to the test can be extracted according to the identified code usage describing the logic function, so as to remove redundant logic (i.e., logic unrelated to the test, such as storage array logic, etc.) to obtain the target code, thereby accelerating the subsequent design process and simplifying the design flow.
Step 103: converting the target code into a target expression mode to be expressed, and obtaining a converted file;
for example, for various EDA tools, verilog expressions that are compatible with the various EDA tools may be preset, and the Verilog expressions that are compatible with the various EDA tools may be set as target expressions corresponding to the EDA tools. Assuming that a target expression compatible with a certain EDA tool a includes expression 1, expression 2, and expression 3, taking the case assumed here as an example, in the above step 103, the target code may be converted to be expressed in any one of expression 1, expression 2, and expression 3.
Step 104: generating a first test excitation file according to the target code;
for example, a set of simulation stimulus files may be generated from the logical functions described by the object code for simulation testing of those logical functions.
Step 105: according to the first test excitation file, performing simulation test on the original Verilog file and the converted file respectively to obtain a first test result;
in one example, a simulation test is performed by a simulation tool according to a first test excitation file and an original Verilog file to obtain a first signal output by the simulation tool, and a simulation test is performed by the simulation tool according to the first test excitation file and a converted file to obtain a second signal output by the simulation tool. Because the test excitation files used for the simulation test based on the original Verilog file and the converted file are the same, whether the converted file is equivalent to the original Verilog file can be determined by judging the consistency of the first signal and the second signal.
Step 106: and judging whether the functions of the converted file and the original Verilog file are consistent according to the first test result.
Along the above example, if the first signal and the second signal are confirmed to be consistent by comparison, it can be determined that the converted file is equivalent to the original Verilog file, or else, it can be determined that the converted file is not equivalent to the original Verilog file, at this time, the Verilog file can be reconverted.
According to the Verilog file conversion method provided by one or more embodiments of the invention, the target code describing the logic function is obtained from the Verilog file, the target code is expressed in the target expression mode corresponding to the target EDA tool in the configuration file, and whether the converted file is equivalent to the original Verilog file or not is verified through the test excitation file, so that the purpose of converting the Verilog file into the file compatible with the target EDA tool is realized, the Verilog file can be applied to various EDA tools, and the universality of the Verilog file is improved. In addition, because the method can convert the Verilog incompatible with EDA tools into the Verilog compatible with the mainstream EDA tools in a relatively simple way, the Verilog file does not need to be redesigned, and the design time is saved.
In one or more embodiments of the present invention, the designer of the Verilog file also customizes some of the functional modules, in which case the configuration file may further include: correspondence of logic functions to Verilog code representing the logic functions. Based on the above, when the object code describing the logic function is obtained from the Verilog file, some custom function modules in the Verilog file can be effectively identified based on the corresponding relation, and the code describing the logic function is obtained. The logic function may be implemented, for example, by one logic device or by at least two connected logic devices.
In one or more embodiments of the present invention, the Verilog file conversion method may further include: modifying the configuration file in response to determining that the converted file is inconsistent with the original Verilog file in function according to the first test result; and re-acquiring target codes describing logic functions from the original Verilog file according to the modified configuration file, and converting the re-acquired target codes into the target expression mode for representation to obtain a re-converted file. Along the above example, if the first signal and the second signal are inconsistent, it may be determined that the converted file is inconsistent with the function of the original Verilog file, where there may be some special function modules in the original Verilog file that are not effectively identified when the original Verilog file is converted, for example, when the original Verilog file includes some user-defined function modules, the function modules may not be correctly identified when codes describing logical functions are identified from the original Verilog file. Therefore, after the converted file is determined to be inconsistent with the original Verilog file according to the first test result, the expression of the custom function modules can be added/modified in the configuration file, so that the logic function in the Verilog file can be correctly identified when the original Verilog file is identified again after the configuration file is modified.
In one or more embodiments of the present invention, the first test result includes a first signal output by a simulation tool when performing a simulation test with the original Verilog file, and a second signal output by the simulation tool when performing a simulation test with the converted file, and determining, according to the first test result, whether the functions of the converted file and the original Verilog file are consistent may include: comparing the first signal with the second signal; determining that the converted file is consistent with the function of the original Verilog file in response to the first signal being consistent with the second signal; and in response to the first signal being inconsistent with the second signal, determining that the converted file is inconsistent with the original Verilog file.
FIG. 2 is a flow chart of a method for converting Verilog files according to one or more embodiments of the present invention, taking the example shown in FIG. 2, in performing equivalence verification on an original Verilog file and a converted file, using the test stimulus file, a test stimulus signal is added to input signals of the original Verilog file and the converted Verilog file, respectively, as shown in steps 203, 204 and 205 in FIG. 2, and then simulation is performed based on the two Verilog files, respectively, by a Verilog simulation tool, and then changes in output signals of the two Verilog files are compared. If the changes of the two Verilog output signals are completely consistent, it can be determined that the converted Verilog file is equivalent to the original Verilog file, i.e., the two functions are consistent.
In one or more embodiments of the present invention, complex Verilog may be simplified according to requirements, for example, when the step of "obtaining object code describing a logic function from the Verilog file" is performed, a part of important logic functions in the Verilog file may be extracted according to requirements, and redundant logic may be removed, so as to simplify the design flow and shorten the design cycle. Based on this, obtaining object code describing logic functions from the original Verilog file may include: identifying codes describing logic functions from the original Verilog file; extracting the target code describing the target logic function from the identified code.
In one or more embodiments of the invention, identifying code describing logical functions from the raw Verilog file may include: and identifying codes describing the logic function from the original Verilog file according to the correspondence between the logic function and the Verilog codes used for representing the logic function. For example, when some user-defined function modules are included in the original Verilog file, codes describing these user-defined function modules can be correctly identified from the original Verilog file according to Verilog codes corresponding to the logic functions defined in the configuration file.
In one or more embodiments of the present invention, the Verilog file conversion method may further include: after obtaining the target code describing the logic function from the original Verilog file, testing the original Verilog file by using a second test excitation file to obtain a second test result; determining a target logic function included in the original Verilog file according to the second test result; and determining whether the target code is correct according to the target logic function. The logic functions contained in the Verilog file can be determined by adding the corresponding test stimulus signals to the original Verilog file and then by the output signals. For example, the information of the scan chain in Verilog file may be determined by injecting a specific stimulus into the scan chain input signal and then observing the output signal of the scan chain.
FIG. 3 is a flow diagram of a Verilog file conversion method, shown in FIG. 3, in accordance with one or more embodiments of the present invention, which may include the following processes:
step 301: preparing an original Verilog file;
step 302: recognizing the logic function description in the original Verilog file, converting the logic function description into a Verilog description mode which can be recognized by a mainstream EDA tool (which is an example of the target EDA tool), namely a universal Verilog file, and generating a set of test stimulus according to the recognized logic structure;
step 303: using the test excitation file generated in the step 302 to respectively carry out simulation test on the original Verilog and the universal Verilog, comparing whether the output signals of the two Verilog files are consistent, if the output signals of the two Verilog files in the simulation test result are completely consistent, determining that the generated universal Verilog file is equivalent to the original Verilog file, otherwise, the generated universal Verilog file and the original Verilog file are not equivalent, and if the generated universal Verilog file and the original Verilog file are not equivalent, returning to the step 302 to convert the original Verilog file again;
step 304: after the commonality Verilog file generated in step 303 passes the equivalent verification, the generated commonality Verilog file can be applied to the design links of the subsequent mainstream EDA tools.
FIG. 4 is a schematic diagram of a Verilog file conversion apparatus according to one or more embodiments of the present invention, as shown in FIG. 4, apparatus 40 may comprise:
a first obtaining module 41, configured to obtain an original Verilog file and a configuration file, where the configuration file includes information of a target expression corresponding to a target EDA tool;
a second obtaining module 42 configured to obtain object codes describing logic functions from the original Verilog file;
a first conversion module 43 configured to convert the target code into a representation in the target expression, resulting in a converted file;
a generation module 44 configured to generate a first test stimulus file from the object code;
the first test module 45 is configured to perform a simulation test on the Verilog file and the converted file according to the first test excitation file, so as to obtain a first test result;
verification module 46 is configured to determine, according to the first test result, whether the converted file is consistent with the function of the original Verilog file.
In one or more embodiments of the present invention, the first test result includes a first signal output by a simulation tool when performing a simulation test with the original Verilog file, and a second signal output by the simulation tool when performing a simulation test with the converted file, and the verification module may specifically be configured to: comparing the first signal with the second signal; determining that the converted file is consistent with the function of the original Verilog file in response to the first signal being consistent with the second signal; and in response to the first signal being inconsistent with the second signal, determining that the converted file is inconsistent with the original Verilog file.
In one or more embodiments of the present invention, the Verilog file conversion apparatus may further include: a modification module configured to modify the configuration file in response to determining that the converted file is inconsistent with the original Verilog file according to the first test result; and the second conversion module is configured to re-acquire the target codes describing the logic functions from the original Verilog file according to the modified configuration file, and convert the re-acquired target codes into the target expression to be expressed, so as to obtain a re-converted file.
In one or more embodiments of the present invention, the second acquisition module is specifically configured to: identifying codes describing logic functions from the original Verilog file; extracting the target code describing the target logic function from the identified code.
In one or more embodiments of the present invention, the configuration file may further include: correspondence of logic functions to Verilog code representing the logic functions.
In one or more embodiments of the present invention, the second acquisition module may be specifically configured to: and identifying codes describing the logic function from the Verilog file according to the correspondence between the logic function and the Verilog codes used for representing the logic function.
In one or more embodiments of the present invention, the Verilog file conversion apparatus may further include: the second testing module is configured to test the original Verilog file by a second testing stimulus file after obtaining the target code describing the logic function from the original Verilog file, so as to obtain a second testing result; the first determining module is configured to determine a target logic function included in the original Verilog file according to the second test result; a second determination module configured to determine whether the target code is correct based on the target logic function.
One or more embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements any of the Verilog file conversion methods described above when the program is executed by the processor.
One or more embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the Verilog file conversion methods described above.
FIG. 5 illustrates a more specific hardware architecture of an electronic device that may include: processor 510, memory 520, input/output interface 530, communication interface 540, and bus 550. Wherein processor 510, memory 520, input/output interface 530, and communication interface 540 enable a communication connection within the device between each other via bus 550.
The processor 510 may be implemented by a general-purpose CPU (Central Processing Unit ), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.
The Memory 520 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 520 may store an operating system and other application programs, and when the embodiments of the present disclosure are implemented in software or firmware, the associated program code is stored in memory 520 and executed by processor 510.
The input/output interface 530 is used for connecting with an input/output module to realize information input and output. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
The communication interface 540 is used to connect with a communication module (not shown in the figure) to enable communication interaction between the present device and other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
Bus 550 includes a path to transfer information between elements of the device (e.g., processor 510, memory 520, input/output interface 530, and communication interface 440).
It should be noted that although the above device only shows the processor 510, the memory 520, the input/output interface 530, the communication interface 540, and the bus 550, in the implementation, the device may further include other components necessary for achieving normal operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
For convenience of description, the above apparatus is described as being functionally divided into various units/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (RandomAccess Memory, RAM), or the like.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (16)
1. The Verilog file conversion method is characterized by comprising the following steps of:
acquiring an original Verilog file and a configuration file, wherein the configuration file comprises information of a target expression mode corresponding to a target electronic design automation EDA tool;
obtaining target codes describing logic functions from the original Verilog file;
converting the target code into a target expression mode to be expressed, and obtaining a converted file;
generating a first test excitation file according to the target code;
according to the first test excitation file, performing simulation test on the original Verilog file and the converted file respectively to obtain a first test result;
and judging whether the functions of the converted file and the original Verilog file are consistent according to the first test result.
2. The method according to claim 1, wherein the first test result includes a first signal output by a simulation tool when the original Verilog file is used for performing a simulation test, and a second signal output by a simulation tool when the converted file is used for performing a simulation test, and determining whether the converted file is consistent with the original Verilog file according to the first test result includes:
comparing the first signal with the second signal;
determining that the converted file is consistent with the function of the original Verilog file in response to the first signal being consistent with the second signal;
and in response to the first signal being inconsistent with the second signal, determining that the converted file is inconsistent with the original Verilog file.
3. The method according to claim 1, wherein the method further comprises:
modifying the configuration file in response to determining that the converted file is inconsistent with the original Verilog file in function according to the first test result;
and re-acquiring target codes describing logic functions from the original Verilog file according to the modified configuration file, and converting the re-acquired target codes into the target expression mode for representation to obtain a re-converted file.
4. The method of claim 1, wherein obtaining object code describing logic functions from the original Verilog file comprises:
identifying codes describing logic functions from the original Verilog file;
extracting the target code describing the target logic function from the identified code.
5. The method of claim 4, wherein the configuration file further comprises:
correspondence of logic functions to Verilog code representing the logic functions.
6. The method of claim 5, wherein identifying code describing logic functions from the original Verilog file comprises:
and identifying codes describing the logic function from the original Verilog file according to the correspondence between the logic function and the Verilog codes used for representing the logic function.
7. The method according to any one of claims 1 to 6, further comprising:
after obtaining the target code describing the logic function from the original Verilog file, testing the original Verilog file by using a second test excitation file to obtain a second test result;
determining a target logic function included in the original Verilog file according to the second test result;
and determining whether the target code is correct according to the target logic function.
8. A Verilog file conversion device, comprising:
the electronic design automation EDA tool comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is configured to acquire an original Verilog file and a configuration file, and the configuration file comprises information of a target expression mode corresponding to the target electronic design automation EDA tool;
a second acquisition module configured to acquire object code describing a logic function from the original Verilog file;
the first conversion module is configured to convert the target code into a representation in the target expression mode to obtain a converted file;
a generation module configured to generate a first test stimulus file from the object code;
the first test module is configured to perform simulation test on the original Verilog file and the converted file according to the first test excitation file to obtain a first test result;
and the verification module is configured to judge whether the functions of the converted file and the original Verilog file are consistent according to the first test result.
9. The apparatus of claim 8, wherein the first test result includes a first signal output by a simulation tool when performing a simulation test with the original Verilog file, and a second signal output by a simulation tool when performing a simulation test with the converted file, and wherein the verification module is specifically configured to:
comparing the first signal with the second signal;
determining that the converted file is consistent with the function of the original Verilog file in response to the first signal being consistent with the second signal;
and in response to the first signal being inconsistent with the second signal, determining that the converted file is inconsistent with the original Verilog file.
10. The apparatus of claim 8, wherein the apparatus further comprises:
a modification module configured to modify the configuration file in response to determining that the converted file is inconsistent with the original Verilog file according to the first test result;
and the second conversion module is configured to re-acquire the target codes describing the logic functions from the original Verilog file according to the modified configuration file, and convert the re-acquired target codes into the target expression to be expressed, so as to obtain a re-converted file.
11. The apparatus of claim 8, wherein the second acquisition module is specifically configured to:
identifying codes describing logic functions from the original Verilog file;
extracting the target code describing the target logic function from the identified code.
12. The apparatus of claim 11, wherein the configuration file further comprises:
correspondence of logic functions to Verilog code representing the logic functions.
13. The apparatus of claim 12, wherein the second acquisition module is specifically configured to:
and identifying codes describing the logic function from the Verilog file according to the correspondence between the logic function and the Verilog codes used for representing the logic function.
14. The apparatus according to any one of claims 8 to 13, further comprising:
the second testing module is configured to test the original Verilog file by a second testing stimulus file after obtaining the target code describing the logic function from the original Verilog file, so as to obtain a second testing result;
the first determining module is configured to determine a target logic function included in the original Verilog file according to the second test result;
a second determination module configured to determine whether the target code is correct based on the target logic function.
15. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the Verilog file conversion method of any one of claims 1 to 7 when the program is executed by the processor.
16. A non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the Verilog file conversion method of any one of claims 1 to 7.
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| CN113312883B (en) * | 2021-05-27 | 2023-01-31 | 展讯通信（上海）有限公司 | WGL file conversion method, device, medium and system |
| CN113536718B (en) * | 2021-09-15 | 2021-12-31 | 中科亿海微电子科技（苏州）有限公司 | Method and device for verifying correctness of gate-level simulation netlist file |
| CN114707444B (en) * | 2022-02-09 | 2023-04-28 | 芯华章科技股份有限公司 | Method for compiling verification system, electronic device and storage medium |
| CN114792079A (en) * | 2022-04-22 | 2022-07-26 | 电子科技大学 | Method for converting gate-level netlist into synthesizable hardware description language code |
| CN115469909B (en) * | 2022-11-14 | 2023-06-20 | 深圳鸿芯微纳技术有限公司 | Instruction updating method, working method, device, equipment and medium of software platform |
| CN117494652A (en) * | 2023-11-14 | 2024-02-02 | 合芯科技(苏州)有限公司 | Automatic cross checking and optimizing device, method and terminal for CTL (cytotoxic T lymphocyte) and DOFILE (data file) |
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