CN112257359B

CN112257359B - Debugging method, device, debugging system and storage medium for data waveform

Info

Publication number: CN112257359B
Application number: CN202011132979.XA
Authority: CN
Inventors: 陶昱良
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-10-21
Filing date: 2020-10-21
Publication date: 2024-04-16
Anticipated expiration: 2040-10-21
Also published as: CN112257359A

Abstract

A debugging method, device, system and storage medium for data waveform. The debugging method comprises the following steps: receiving first waveform data in a first format responsive to a first data packet signal; invoking at least one packet mapping information file corresponding to at least one data protocol, the at least one packet mapping information file comprising a first packet mapping information file; inquiring the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data; and running a first data analysis function corresponding to the first waveform data to analyze the first waveform data from the first format to the second format. The debugging method can improve the efficiency of waveform debugging of the data packet in the chip design, shorten the chip design period, and can also be used for waveform debugging of the data packet of various data protocols so as to realize universal expandability.

Description

Debugging method, device, debugging system and storage medium for data waveform

Technical Field

Embodiments of the present disclosure relate to a debugging method, apparatus, debugging system, and storage medium for data waveforms.

Background

Currently, in chip designs, such as high performance graphics processor (Graphics Processing Unit, CPU) and central processing unit (Central Processing Unit, CPU) designs, design engineers verify that the design satisfies the intended function, typically by simulation. Debugging of the dummy waveform extends through the entire chip design cycle, for example, the dummy waveform includes register transfer level (RTL, register Transfer Level) dummy waveform debugging, prototype design dummy waveform debugging, gate net list (Gate net list) dummy waveform debugging, and the like. In the simulation process, each functional module is generally simulated first, and then the whole system is simulated after all functional modules pass through the simulation process. When a design engineer finds an error in the simulation process, it is necessary to perform careful debugging, find the cause of the error occurrence, and modify it. If some uncorrectable errors occur due to considerations in the system-on-chip design, a system design engineer is required to redesign the system-on-chip solution. Therefore, the simulation process is a critical loop for the entire flow of the chip design.

Disclosure of Invention

Embodiments of the present disclosure provide a debugging method, apparatus, debugging system and storage medium for data waveforms. The method for debugging the data waveform can improve the efficiency of waveform debugging of the data packet in chip design, shorten the chip design period, and can also be used for waveform debugging of the data packet of various data protocols so as to realize universal expandability.

At least one embodiment of the present disclosure provides a method for debugging a data waveform, the method for debugging a data waveform including: receiving first waveform data in a first format responsive to a first data packet signal; invoking at least one data packet mapping information file corresponding to at least one data protocol, wherein the at least one data packet mapping information file comprises a first data packet mapping information file, each of the at least one data packet mapping information file comprises a corresponding relation between a plurality of data packet signals and a corresponding plurality of data parsing functions, and the first data packet mapping information file is determined according to a specification file and a chip design file of the first data protocol; querying the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data; and running the first data analysis function corresponding to the first waveform data, and analyzing the first waveform data from the first format to a second format, wherein the first format and the second format are different.

For example, the debugging method provided in at least one embodiment of the present disclosure, before receiving the first waveform data in the first format in response to the first data packet signal, further includes: receiving a first trigger event sent by the waveform display device corresponding to the first data packet signal; generating first request information according to the first trigger event; and transmitting the first request information to the waveform display device to request the waveform display device to transmit the first waveform data corresponding to the first trigger event, wherein the waveform display device generates the first trigger event in response to the displayed first data packet signal being triggered.

For example, in the debugging method provided in at least one embodiment of the present disclosure, generating the first request information according to the first trigger event includes: calling a trigger event-callback function mapping table; searching the trigger event-callback function mapping table according to the first trigger event to obtain a first callback function corresponding to the first trigger event; and obtaining a first instruction corresponding to the first trigger event according to the first callback function to obtain the first request information comprising the first instruction, wherein the first instruction is used for requesting the waveform display device to send the first waveform data, and the trigger event-callback function mapping table comprises the corresponding relation between a plurality of trigger events and a plurality of corresponding callback functions.

For example, in the debugging method provided in at least one embodiment of the present disclosure, the first request information further includes first data signal information, and the generating the first request information according to the first trigger event further includes: obtaining the first data signal information based on the first data packet mapping information file; and transmitting the first request information including the first instruction and the first data signal information to the waveform display device to request the waveform display device to transmit the first waveform data.

For example, in the debugging method provided in at least one embodiment of the present disclosure, requesting the waveform display device to send the first waveform data includes: the waveform display device responds to the first instruction based on an instruction mapping table to obtain a first instruction response function, and sends the first waveform data based on the first instruction response function and the first data signal information, wherein the instruction mapping table comprises corresponding relations between a plurality of instructions and corresponding plurality of instruction response functions.

For example, in the debugging method provided in at least one embodiment of the present disclosure, each entry of the first data packet mapping information file includes a name of a trigger data packet signal and a signal list, where the signal list of the trigger data packet signal includes an acquisition time corresponding to a data packet signal that needs to be acquired by the trigger data packet signal, and obtaining the first data signal information based on the first data packet mapping information file includes: searching names of a plurality of triggering data packet signals included in the first data packet mapping information file, corresponding to the triggered names of the first data packet signals, determining the first data packet mapping information corresponding to the triggered first data packet signals, and determining a first signal list needing to be acquired according to the first data packet mapping information corresponding to the triggered first data packet signals, wherein the first data signal information comprises acquisition time of the data packet signals needing to be acquired in the first signal list.

For example, the debugging method provided in at least one embodiment of the present disclosure, before generating the first request information according to the first trigger event, further includes: checking the validity of the first trigger event; checking the validity of the triggered first data packet signal corresponding to the first trigger event, and in response to the first trigger event being valid and the triggered first data packet signal being valid, looking up the trigger event-callback function mapping table.

For example, in the debugging method provided in at least one embodiment of the present disclosure, checking the validity of the first trigger event includes: determining that the first trigger event is valid in response to the trigger event-callback function mapping table including a correspondence corresponding to the first trigger event; checking the validity of the triggered first data packet signal corresponding to the first trigger event, comprising: and searching for the name of the first data packet signal corresponding to the trigger among the names of the plurality of trigger data packet signals included in the first data packet mapping information file in response to the name of the first data packet signal to be triggered, and determining that the first data packet signal corresponding to the first trigger event to be triggered is valid.

For example, in the debugging method provided in at least one embodiment of the present disclosure, each of the at least one packet mapping information file includes a plurality of resolution function addresses corresponding to the plurality of data packet signals, respectively, and each of the plurality of resolution function addresses is used for obtaining a corresponding data resolution function.

For example, in the debugging method provided in at least one embodiment of the present disclosure, the at least one packet mapping information file includes a plurality of packet mapping information files, the plurality of packet mapping information files includes the first packet mapping information file, and a first resolution function address corresponding to the triggered name of the first packet signal is obtained in the first packet mapping information file by using the triggered name of the first packet signal.

For example, the debugging method provided in at least one embodiment of the present disclosure, before receiving the first waveform data in the first format in response to the first data packet signal, further includes: loading the at least one packet mapping information file and establishing communication with the waveform display apparatus.

For example, the debugging method provided in at least one embodiment of the present disclosure further includes: and determining the first data packet mapping information file to be called according to a first data protocol corresponding to the data packet where the first data packet signal is displayed by the waveform display device.

For example, the debugging method provided in at least one embodiment of the present disclosure further includes: and sending the second format of the first waveform data to an information display device so as to display information corresponding to the first waveform data on the information display device.

For example, in the debugging method provided in at least one embodiment of the present disclosure, the second format is a text format.

For example, in a debugging method provided in at least one embodiment of the present disclosure, parsing the first waveform data from the first format into the second format includes: and splitting the value of the first waveform data into at least one domain segment according to a specification file of a first data protocol corresponding to the first data packet signal, and analyzing the first waveform data into the second format according to the value of the at least one domain segment.

At least one embodiment of the present disclosure also provides a debugging apparatus for a data waveform, the debugging apparatus comprising: a data receiving module configured to receive first waveform data in a first format in response to a first data packet signal; a mapping information file calling module configured to call at least one data packet mapping information file corresponding to at least one data protocol, wherein the at least one data packet mapping information file comprises a first data packet mapping information file, each of the at least one data packet mapping information file comprises a corresponding relation between a plurality of data packet signals and a corresponding plurality of data parsing functions, and the first data packet mapping information file is determined according to a specification file and a chip design file of the first data protocol; the analysis function determining module is configured to query the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data; and a data parsing module configured to run the first data parsing function corresponding to the first waveform data, parse the first waveform data from the first format to a second format, wherein the first format and the second format are different.

At least one embodiment of the present disclosure also provides another debugging device for a data waveform, the debugging device comprising: a processor and a memory, wherein the memory has stored therein computer executable code which, when executed by the processor, performs the debugging method for a data waveform as claimed in any one of the preceding claims.

At least one embodiment of the present disclosure also provides a debug system for a data waveform, the debug system comprising: the debugging device and waveform display device of any preceding claim, the waveform display device being communicatively coupled to the debugging device, wherein the waveform display device is configured to generate and transmit a first trigger event corresponding to the displayed first data packet signal in accordance with an input operation and to transmit the first waveform data corresponding to the first trigger event based on the received first request information of the debugging device.

For example, the debug system provided by at least one embodiment of the present disclosure further includes: and the information display device is in communication connection with the debugging device and is configured to receive and display a second format of the first waveform data sent by the debugging device.

At least one embodiment of the present disclosure also provides a computer-readable storage medium having stored thereon executable code that, when executed by a processor, causes the processor to perform a debugging method for a data waveform as set forth in any one of the preceding claims.

According to the debugging method, the device, the debugging system and the storage medium for the data waveform, the first data analysis function corresponding to the first waveform data is obtained by calling the data packet mapping information file, the first data analysis function corresponding to the first waveform data is operated, the first waveform data is analyzed from the first format to the second format, the waveform data in the first format with poor readability can be analyzed to the waveform data in the second format which is readable, whether the data packet signal accords with expectations or not can be determined according to the first waveform data in the first format, so that the waveform debugging efficiency of the data packet in chip design is improved, the chip design period is shortened, and the debugging method for the data waveform can be further used for waveform debugging of the data packet of various data protocols to realize universal expandability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A is a schematic diagram of a chip design flow;

FIG. 1B is a communication schematic diagram of a system-on-chip;

FIG. 2A is a diagram of a packet signal of a protocol packet;

FIG. 2B is a diagram of packet signals of various protocol packets;

FIG. 3 is a schematic diagram of a designer manually performing waveform debugging;

FIG. 4 is a flow chart of a method for debugging a data waveform according to at least one embodiment of the present disclosure;

FIG. 5 is a flow chart illustrating a method for performing debugging for data waveforms according to at least one embodiment of the present disclosure;

FIG. 6 is a system diagram of a method for performing debugging for data waveforms according to at least one embodiment of the present disclosure;

FIG. 7 is a flow chart of a method for debugging a data waveform provided in accordance with at least one further embodiment of the present disclosure;

FIG. 8A is a diagram illustrating packet signals of various protocol packets according to at least one embodiment of the present disclosure;

FIG. 8B is a diagram of packet signals of various protocol packets according to at least one embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a debugging device using data waveforms according to at least one embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a debugging device using data waveforms according to at least another embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a debug system using data waveforms according to at least one embodiment of the present disclosure; and

fig. 12 is a schematic diagram of a storage medium according to at least one embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items.

Chip designs are typically based on the design flow of electronic design automation tools (EDA), that is, the individual steps of the integrated circuit design are accomplished by engineers on computers using a variety of EDA tools. The front-end design sequentially comprises the steps of system level design, RTL (Register Transfer Level ) design, RTL simulation, hardware prototype verification, circuit synthesis and the like, and the back-end design comprises the steps of layout design, physical verification, post simulation and the like.

Fig. 1A is a schematic flow chart of a chip design. As shown in fig. 1A, the chip design flow includes steps S01 to S11.

Step S01: architecture definition. The architecture definition may also be referred to as a behavior level (Behavioral) description. In step S01, the entire System is typically modeled in a high-level computer language (e.g., C language and System C language dedicated to integrated circuit System design), and the functions of each module are considered to be described to reflect the behavioral functions of the module.

Step S02: RTL design. RTL designs use hardware description language (a language capable of describing logic devices, such as Verilog HDL language) to describe combinational and sequential logic devices on a register-to-register basis.

Step S03: RTL simulation debugging. In order to ensure the correct function of the RTL design, the RTL needs to be simulated and debugged, namely, the RTL-level simulation waveform is debugged.

Step S04: judging whether a functional error occurs in the RTL simulation waveform debugging process. When a problem occurs in the waveform simulation of the RTL, the step S02 is performed to modify the RTL design, and the simulation waveform debugging is performed again. Step S04 may be iterated a number of times until the RTL design is not problematic. Step S08-step S010 and step S05-step S07 are entered. In order to save the development cycle of the chip design, step S08-step S010 and step S05-step S07 are typically parallel.

Step S05: physical implementation. In the physical implementation process, the RTL design is physically designed, including logic synthesis, layout and wiring, and the like. The physical design then yields the final gate level netlist.

Step S06: and (5) gate-level netlist simulation debugging. And (3) performing simulation waveform debugging based on the gate-level netlist obtained in the step S05.

Step S07: judging whether functional errors or time sequence errors occur in the process of debugging the gate-level netlist simulation waveforms. When a problem is found in the process of debugging the gate-level netlist simulation waveform, the method goes to step S02 to modify the RTL design and step S05 to modify the physical implementation process. Step S010 iterates a plurality of times until the gate level netlist is free of problems, and proceeds to step S11.

Step S08: prototype design (FPGA/integration). RTL designs are put on FPGAs (Field Programmable Gate Array, field programmable gate arrays) or emulators for prototyping verification. For example, the RTL design is put into the FPGA to perform prototype design verification, and a plurality of independent basic components can be loaded by using the FPGA programming, and the components are connected with each other to form a required actual hardware circuit, so as to verify whether the design can realize the expected function.

Step S09: and (5) performing prototype design simulation debugging. Waveform simulation is performed based on the hardware circuit in step 08.

Step S010: judging whether functional errors occur in the process of prototype design simulation debugging. When a problem is found in the process of the prototype design simulation debugging, the step S02 is performed to modify the RTL design. Step S010 will iterate a number of times until the prototype design is not problematic. Step S11 is entered.

Step S11: and (5) streaming the sheet. The streaming process includes delivering the chip design file to a factory for chip fabrication after both the prototype design simulation and the gate level netlist simulation pass. For example, a back-end physical implementation tool (e.g., a Place & Route (PR) tool) generates a GDSII file using the gate level netlist as input, the GDSII file being used in chip fabrication.

According to the above, waveform debugging is applied to a plurality of links in the course of chip design.

Fig. 1B is a communication schematic diagram of a chip system. As chip sizes become larger and designs become more complex, current SOCs (system on chip) integrate a large number of different modules (IPs) and protocols (protocols), and communication between different protocols is carried out through different packets (packets).

As shown in fig. 1B, the communication protocol 01 is, for example, AXI (Advanced eXtensible Interface), and the hardware modules 011, 012, 013, and 014 all communicate via data packets of AXI protocol. The communication protocol 02 is, for example, SDP (Scalable Data Protocol) protocol (scalable data protocol), and the hardware modules 021, 022, 023 and 024 all communicate via data packets of SDP protocol. Modules 013 and 014 communicate with the dynamic random access memory DRAM via a variety of protocol packets 001. For example, the various protocol Data packets 001 include various DDR (Double Data Rate) protocols, such as DDR4/5, GDDR (Graphic Double Data Rate) 5/6, HBM (High Bandwidth Memory) 2/3, etc. For example, modules 023 and 024 communicate with external interface PI via a variety of external protocol data packets 002. Various external protocol data packets 002 include, for example, PCIe (peripheral component interconnect express), SATA (Serial Advanced Technology Attachment), USB (Universal Serial Bus), ethernet (Ethernet), etc. Communication takes place between communication protocol 01 and communication protocol 02 via protocol bridge 03.

Data packets are typically composed of one or more multi-bit (bit) signals, the data packet formats vary widely from data protocol to data protocol, the process of debugging the simulated waveforms of these data packets is time consuming, error prone, and may be iterated multiple times. Therefore, the efficient data packet simulation waveform debugging method is helpful for reducing the debugging iteration times and shortening the chip design period.

Fig. 2A is a schematic diagram of a packet signal of a protocol packet. As shown in fig. 2A, the data packet signal 0CLK is encapsulated in a set of signal buses, which are composed of multi-bit data. For example, the signal bus is the output bus of a static memory. The waveform display device only displays the value of the data packet (e.g. 0T 0) in a certain clock period (e.g. 0x1f4897c 0) of the waveform, and the content of the data packet corresponding to the current time point of the value cannot be known clearly, so that it is necessary to analyze the signal bus and then analyze whether the data packet meets the expectations. The first waveform data 0sram to be debugged at time 0T0 on the waveform display device is 64-bit sram_dout (for example, representing static memory output data), and the display value of 64-bit sram_dout is 0x1f4897c0. It is not intuitively known what the value is, for example, by splitting the packet into field segments such as command type, host identifier, slave identifier, command data address, etc. according to table 01 below.

Table 01

Bit (bit)	[63:22]	[21:14]	[13:6]	[5:0]
					Number of bits	42 bits	8 bits	8 bits	6 bits
Domain segment	Command address	Slave identifier	Host identifier	Command type

According to table 01, the value 0x1f4897c0 is converted into a binary value, and then the values of the 0 th bit to the 5 th bit of the binary value are taken as field values of the command type. Converting the domain segment value of the binary command type into a decimal number, and searching the command type corresponding to the decimal command type according to the domain segment value of the decimal command type. For example, bits [5:0] of 0x1f4897c0 are equal to 0, 6' d0=invalid command according to the definition of the command type in the specification file of the data protocol. Therefore, the current packet signal represents an invalid command. And the packet signal is a read command according to the expectation, that is, bits [5:0] are equal to 1. Thus, it can be determined that the current packet is erroneous, requiring modification to the previous design.

There are multiple data protocols in the current chip design (as shown in fig. 1B), and the data packet formats of the different data protocols are quite different. Even with the same data protocol, there may be many different formats of data packets. Therefore, the waveform in the process of designing a chip needs to debug and analyze different protocol data packets at the same time, and the waveform analysis of each protocol data packet needs to be analyzed one by one, which is time-consuming and labor-consuming.

Fig. 2B is a schematic diagram of packet signals of various protocol packets. As shown in fig. 2B, the waveform display device displays data packets of two data protocols, wherein the first waveform data 0sram to be debugged is in a data packet of a custom data protocol, and the second waveform data 0cpu to be debugged is in a data packet of a RISC-V (Reduced Instruction Set Computer ) data protocol. For example, the value 0x1c418293 of the second waveform data 0cpu is divided into the field segments of the immediate, the source register, the opcode 2, the destination register, and the opcode 1 according to the following table 02.

Table 02

According to table 01, the corresponding command is searched according to the field value after the splitting of the numerical value 0x1c418293, and whether an error exists in the data packet is checked. When waveform simulation is wrong, the two data packets may need to be analyzed again at the same time, and even more different data packets need to be analyzed, which results in a multiple increase in debugging workload.

In the waveform debugging process, a designer usually adopts a manual debugging method, i.e. the waveform data on the waveform display device is observed by naked eyes and manual decoding work is performed. Fig. 3 is a schematic diagram of a designer manually performing waveform debugging. As shown in fig. 3, the waveform display apparatus 0V reads the waveform file. For example, RTL is simulated using a simulation tool VCS (Verilog Compile Simulator) from Synopsys, resulting in a waveform file of VCD (Value Change Dump) or FSDB (Fast Signal Data Base). The designer 0S visually observes the waveform to obtain waveform data. For example, the designer 0S may see that, for example, the first waveform data 0sram to be debugged at time 0T0 shown in fig. 2A has a value of 0x1f4897c0, and manually queries the specification file 0D of the data protocol to which the data packet belongs to obtain the first waveform data 0sram divided into the following field segments: command type (bits [5:0 ]), host identifier (bits [13:6 ]), slave identifier (bits [21:14 ]), command data address (bits [48:22 ]), etc. For example, manually decoding the first waveform data 0sram may obtain decoded waveform data 0F as: the command type is 0x0, the host identifier is 0x5f, the slave identifier is 0x22, and the command data address is 0xFA. Iterating to the next waveform data, e.g., after debugging one waveform data, continuing to debug the next waveform data. For example, the process of finding specification files and analyzing waveform data described above requires multiple iterations until all waveform data of a data packet is debugged correctly.

The manual debugging method is time-consuming and is prone to error, especially when the data size is large. For example, a 1024-bit data packet may have tens or hundreds of field segments, and when there are a large number of such data packets in the simulated waveform, the analysis is very complex and error-prone.

At present, the complexity of chip design is increased, the updating iteration of the chip is faster and faster, and a method for improving the waveform debugging efficiency and accuracy is needed to shorten the chip development period.

At least one embodiment of the present disclosure provides a debugging method for a data waveform. The debugging method for the data waveform comprises the following steps: receiving first waveform data in a first format responsive to a first data packet signal; invoking at least one data packet mapping information file corresponding to at least one data protocol, wherein the at least one data packet mapping information file comprises a first data packet mapping information file, each of the at least one data packet mapping information file comprises a corresponding relation between a plurality of data packet signals and a corresponding plurality of data parsing functions, and the first data packet mapping information file is determined according to a specification file and a chip design file of the first data protocol; inquiring the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data; and running a first data analysis function corresponding to the first waveform data, and analyzing the first waveform data from a first format to a second format, wherein the first format and the second format are different.

In the method for debugging a data waveform provided in the foregoing embodiment of the present disclosure, a first data parsing function corresponding to first waveform data is obtained by calling a data packet mapping information file, the first data parsing function corresponding to the first waveform data is operated, and the first waveform data is parsed from a first format into a second format, so that, for example, waveform data in the first format with poor readability can be parsed into waveform data in the readable second format, whether a data packet signal accords with expectations can be determined according to the first waveform data in the first format, so as to improve efficiency of waveform debugging of a data packet in a chip design, shorten a chip design period, and the method for debugging a data waveform can also be used for waveform debugging of a data packet in a plurality of data protocols, so as to realize universal scalability.

Embodiments of the present disclosure and examples thereof are described in detail below with reference to the attached drawing figures.

Fig. 4 is a flowchart of a method for debugging a data waveform according to at least one embodiment of the present disclosure. Fig. 5 is a flowchart illustrating a method for performing debugging for data waveforms according to at least one embodiment of the present disclosure. Fig. 6 is a schematic diagram of a system for performing a debugging method for data waveforms according to at least one embodiment of the present disclosure. The debugging method for data waveforms provided by the embodiment of the present disclosure as shown in fig. 4 includes steps S110 to S140. The debugging method for the data waveform as shown in fig. 6 includes step S301. The debugging method for the data waveform as shown in fig. 5 includes steps S201 to S213.

Step S110: first waveform data in a first format responsive to a first data packet signal is received.

For example, the waveform display device is triggered in response to the displayed first data packet signal. For example, as shown in fig. 6, the waveform display apparatus V1 displays a first data packet signal (e.g., data packet signal CLK) that is triggered, for example, by clicking the mouse 40. For example, waveform display device V1 may be a Verdi waveform display tool.

For example, as shown in fig. 6, the debug analysis platform P1 includes a host P10. The host computer for running the debugging method provided by the embodiment of the disclosure. The host P10 is connected to the waveform display device V1 and the information display device DISP. The debug analysis platform P1 receives first waveform data in a first format in response to the first data packet signal. The first format is a numerical format, for example, a hexadecimal numerical value (for example, a numerical value of 0x34df of the packet signal BUS1 at time T0 shown in fig. 6), and the designer cannot directly learn the content (for example, a command type or an instruction type represented by the numerical value of 0x34 df) corresponding to the first waveform data in the first format.

For example, the information display device DISP may be a device having a display function such as a display panel.

For example, as shown in fig. 5, the debug analysis platform communicates with the waveform display device V1. Step S202: the host establishes communication with the waveform display apparatus. For example, as shown in fig. 6, the host P10 communicates by establishing a standard TK (ToolKit) transmission/reception communication mechanism. For example, as shown in fig. 6, the host P10 establishes a communication slot TK1 with the waveform display apparatus V1. For example, the communication mechanism is a toolkit of TCL language (which is an interpreted programming language). The mechanism communicates through the TK standard send command and accept command. The present disclosure is not limited to the manner of communication with the waveform display apparatus.

Step S203: the debugging analysis platform is in an idle state. For example, the idle state of the debug analysis platform P1 is a state in which no trigger event or waveform data is received.

Step S204: there is no trigger event. When no trigger event occurs, debug analysis platform P1 is always in the idle state of step 203.

Step S205: the debug analysis platform receives a first trigger event. For example, in some embodiments, as shown in fig. 6, the debug analysis platform P1 receives a first trigger event 21 from the waveform display device V1 corresponding to the first data packet signaling. The waveform display device V1 generates a first trigger event 21 in response to the displayed first data packet signal (e.g., the data packet signal CLK in fig. 6) being triggered.

Step S206: and the host searches the trigger event-callback function mapping table according to the first trigger event. For example, in some embodiments, as shown in FIG. 6, the host P10 invokes a trigger event-callback function mapping table E10. The trigger event-callback function mapping table E10 includes correspondence between a plurality of trigger events and a plurality of callback functions, so that when a first trigger event sent by the waveform display device is received, a first callback function E11 corresponding to the first trigger event 21 can be found. For example, one example of a trigger event-callback function mapping table is shown in table 1.

TABLE 1

Format of the form	Name of the trigger event: name of callback function
		Example	CursorMove:cb_CursorMove(args,*kwargs)

According to the content of table 1, when the name of the trigger event is "CursorMove", the trigger event-callback function mapping table is searched, and a callback function named "cb_cursormove (ars) and kwargs" of the callback function can be obtained.

Step S207: the host checks the validity of the first trigger event. For example, in some embodiments, as shown in fig. 6, the host P10 needs to check the validity of the first trigger event, including: and determining that the first trigger event is valid in response to the trigger event-callback function mapping table including a correspondence relationship corresponding to the first trigger event. When the trigger event-callback function mapping table is searched based on the name of the first trigger event, if the corresponding first callback function is searched, the first trigger event 21 is determined to be valid, otherwise, the first trigger event 21 is determined to be invalid. Step S203 is entered when the first trigger event 21 is invalid. When the first trigger event 21 is valid, the process advances to step S208.

For example, in some embodiments, the host P10 checks the validity of the triggered first data packet signal while detecting the validity of the first trigger event. For example, the validity of the first data packet signal is determined by checking whether the name of the triggered first data packet signal corresponds to the name recorded in the first data packet map information file.

Step S208: the host executes a first callback function. For example, as shown in fig. 6, the host P10 communicates with the waveform display device V1 in the process of executing the first callback function E11, generates first request information according to the first trigger event 21 to request the waveform display device V1 to transmit first waveform data corresponding to the first trigger event 21, and receives the first waveform data.

Step S209: the host sends first request information to the waveform display device to request the waveform display device to send first waveform data corresponding to a first trigger event. For example, in some embodiments, as shown in fig. 6, the host P10 transmits the first request information to the waveform display device V1 to request the waveform display device V1 to transmit the first waveform data corresponding to the first trigger event 21. For example, the first request information may include the first instruction E21 and the first data signal information. The first request information will be described in detail later.

Step S120: at least one packet mapping information file corresponding to at least one data protocol is invoked.

For example, corresponding data packet map files are generated or written from specification files of different data protocols and chip design files (e.g., RTL files) in the chip design process. For example, as shown in fig. 6, each data protocol corresponds to a specification file D, and a chip design file R is generated during the chip design process. The specific content of the packet map file may be determined from the content defined in the specification file D, the name of the packet signal used in the packet map file may be determined from the chip design file R (e.g., RTL file), etc. The at least one data packet mapping information file each includes a correspondence of a plurality of data packet signals to a corresponding plurality of data parsing functions. And searching the data packet mapping file according to the data packet signal to obtain a data analysis function corresponding to the data packet signal.

For example, in some embodiments, the at least one packet mapping information file may include a plurality of packet mapping information files. One or more packet map information files may be invoked as required by the debugged packet waveforms as shown in fig. 6. That is, the data packet mapping file corresponding to the data protocols can be called by the data packet signal currently debugged by the debug analysis platform P1.

For example, the debugging method provided by the embodiment of the disclosure can support simulation waveform debugging analysis of a data packet of any data protocol. For example, the data packets may include various standard protocol data packets, such as various DDR protocols (DDR 4/5, LPDDR4/5, GDD 5/6, HBM2/2E/3, etc.), PCIe protocols, USB protocols, etc., various internal custom protocol data packets, other standard protocol data packets, such as RISC-V instruction data packets, ARM (Advanced RISC Machine) instruction data packets, etc.

For example, as shown in fig. 5, step S201: the debug analysis platform invokes at least one packet map information file. The at least one packet mapping information file includes a first packet mapping information file. For example, as shown in fig. 6, the debug analysis platform P1 may call a plurality of packet mapping information files 01 for debugging of a plurality of protocol packets, thereby realizing general scalability of the debug method.

For example, in some embodiments, the packet map information file is generated or written from a specification file and a chip design file, stored as a JSON (JavaScript Object Notation) file. Each entry of the at least one packet map information file contains at least one of the following items of information. The plurality of information includes: the function address (function), the name (trigger) of the trigger packet signal, and the signal list (signals). For example, the name (trigger) of the trigger packet signal may be consistent with the name of the packet signal as determined by the chip design file. The signal list includes at least one of the following information: the name of the data packet signal to be collected (name) and the collection time of the data packet signal to be collected (value).

For example, a packet mapping information file corresponding to a custom data protocol is shown below.

For example, a packet map information file corresponding to RISC-V (Reduced Instruction Set Computer ) instruction data protocol is shown below.

For example, in some embodiments, the at least one packet mapping information file includes a first packet mapping information file. The first data packet mapping information file is determined according to a specification file and a chip design file of the first data protocol. For example, the first data protocol may comprise a custom data protocol.

Step S130: and querying the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data.

For example, as shown in fig. 6, the debug analysis platform P1 may use the name (e.g. CLK) of the triggered first data packet signal to obtain a first resolution function address corresponding to the name of the triggered first data packet signal in the first data packet map information file. The first analysis function address is used to acquire a data analysis function (e.g., a first data analysis function J11) corresponding to the first waveform data.

For example, in some embodiments, the data parsing function includes a transcoding format of a data protocol corresponding to the data packet signal. For example, a data parsing function that parses a data packet signal is written according to a specification file.

Step S140: and running a first data analysis function corresponding to the first waveform data to analyze the first waveform data from the first format to the second format. For example, as shown in fig. 6, the host P10 parses the first waveform data from the first format to the second format by running the first data parsing function J11.

For example, the second format is a text format. For example, the first waveform data in the second format is a command type or an instruction type. According to the first waveform data in the second format, whether the first waveform data in the first format accords with the expectation can be directly obtained, so that whether the data packet where the first data packet signal is located is in error is judged.

For example, in some embodiments, the first data parsing function parses the input pure numerical information (first waveform data in a first format) into readable text information (first waveform data in a second format).

For example, as shown in fig. 5, step S210: the host parses the first waveform data in the first format. For example, as shown in fig. 6, the host P10 runs the first data parsing function J11 to parse the first waveform data of the first format, i.e., parse the first waveform data from the first format to the second format.

Step S211: the values of the first waveform data are split into at least one domain segment.

Step S212: the first waveform data is parsed into a second format according to the values of the at least one domain segment.

For example, step S211 and step S212 are specific procedures for performing step S210. For example, as shown in the waveform of the data packet in fig. 2A, in the process of waveform debugging, the host P10 in fig. 6 splits the waveform data in the first format into the following field segments according to table 01: bits [5:0] (command type) are 0x0, bits [13:6] (host identifier) are 0x5f, bits [21:14] (slave identifier) are 0x22, and bits [48:22] (command data address) are 0xFA. The first waveform data in the second format can be obtained according to the values of the above field segments: the command type is an invalid command. Therefore, according to the waveform data of the second format, whether the content of the data packet signal accords with the expectation can be directly judged, so that a great amount of time, manpower and material resources are saved, and the chip design period is quickened.

For example, continuing as shown in fig. 5, step S213: the first waveform data in the second format is displayed. For example, in some embodiments, as shown in fig. 6, the host P10 transmits the second format of the first waveform data to the information display device DISP to display information corresponding to the first waveform data on the information display device DISP. The designer can directly judge whether the first data packet signal which is triggered currently accords with the expectation or not according to the information corresponding to the first waveform data displayed on the information display device DISP. For example, the information corresponding to the first waveform data may include a readable command type or instruction type, or the like.

The method for debugging the data waveform in the embodiment improves the efficiency of waveform debugging of the data packet in the chip design, shortens the chip design period, and can also be used for waveform debugging of the data packet of various data protocols to realize universal scalability.

For example, as shown in fig. 6, before the waveform of the data packet displayed by the waveform display device V1 is debugged, the designer S first performs step S301: the configuration is entered. For example, in step S301, designer S chooses to parse the packets of those data protocols. For example, the designer selects the waveform display device V1 to which the host computer P10 of the debug analysis platform P1 is to be connected and in communication.

For example, waveform display device V1 may be a Verdi waveform display tool.

For example, in some embodiments, the debug analysis platform P1 establishes a communication slot TK1 with the waveform display device V1. For example, the communication slot TK1 includes a trigger event-callback function mapping table E10 and an instruction mapping table E20.

For example, as shown in fig. 6, the debug analysis platform P1 performs the debug method provided by the embodiments of the present disclosure. For example, in the process of waveform debugging, the debug analysis platform P1 needs to prepare the packet mapping information file 10 corresponding to the packet of the data protocol selected for parsing in step S301 before receiving the first waveform data in the first format in response to the first packet signal. For example, the packet map information file 10 includes correspondence between a plurality of packet signals and a corresponding plurality of data parsing functions. And searching the data packet mapping file according to the data packet signal to obtain a data analysis function corresponding to the data packet signal. For example, the packet mapping information file 10 includes a first packet mapping information file 11 corresponding to the first waveform data.

For example, in some embodiments, as shown in fig. 6, the first packet mapping information file 11 is determined according to the specification file D and the chip design file R of the first data protocol, for example, the following pieces of information are determined: the address (function) of the data parsing function, the name (trigger) of the trigger packet signal, and the signal list (signals). For example, the name (trigger) of the trigger packet signal is determined based on the name of the signal defined in the chip design file R.

For example, in some embodiments, as shown in fig. 6, debug analysis platform P1 uses the name of the triggered first packet signal to obtain a first resolution function address corresponding to the name (e.g. CLK) of the triggered first packet signal in first packet map information file 11. The first analysis function address is used to acquire a data analysis function (e.g., a first data analysis function J11) corresponding to the first waveform data. The data parsing function J10 is determined according to the specification file D of the data protocol. The data parsing function J10 includes a first data parsing function J11 of a data packet of a first data protocol. The first packet mapping information file 11 may call the first data parsing function J11 through the first data parsing function address.

For example, in some embodiments, debug analysis platform P1 invokes at least one packet mapping information file 10. For example, when the debugging analysis platform P1 performs waveform debugging on the data packets of the plurality of data protocols, the debugging analysis platform P1 calls the data packet mapping files corresponding to the plurality of data protocols to perform waveform debugging on the plurality of data packets, thereby achieving the purpose of general scalability of the debugging method.

For example, in some embodiments, as shown in fig. 6, when a designer (user) clicks on a first data packet signal (e.g., a data packet signal CLK or a data packet signal BUS1, etc.) displayed by the waveform display device V1 using the mouse 40, the waveform display device V1 is triggered in response to the displayed first data packet signal (e.g., the data packet signal CLK), generating the first trigger event 21. Correspondingly, the debug analysis platform P1 further comprises, prior to receiving the first waveform data in the first format in response to the first data packet signal: the received waveform display means corresponds to a first trigger event 21 of the first data packet signal transmission; generating first request information according to the first trigger event 21; and transmitting the first request information to the waveform display device V1 to request the waveform display device V1 to transmit the first waveform data corresponding to the first trigger event 21.

For example, in some embodiments, as shown in fig. 6, the host P10 generates the first request information according to the first trigger event, including: calling a triggering event-callback function mapping table E10; searching a trigger event-callback function mapping table E10 according to the first trigger event 21 to obtain a first callback function E11 corresponding to the first trigger event 21; the first instruction E21 corresponding to the first trigger event 21 is obtained according to the first callback function E11, so as to obtain first request information comprising the first instruction E21. The first instruction E21 is for requesting the waveform display device V1 to transmit the first waveform data. For example, the first callback function E11 is set corresponding to the first instruction E21, and the first instruction E21 is called by the first callback function E11. In executing the first callback function E11, first request information is generated to the waveform display device V1, and first waveform data corresponding to the first request information generated by the waveform display device V1 is received.

For example, in some embodiments, the trigger event-callback function mapping table E10 includes correspondence of a plurality of callback functions to a plurality of trigger events. For example, the trigger event-callback function mapping table E10 includes a first trigger event 21-a first callback function E11, a second trigger event 22-a second callback function E12.

For example, in some embodiments, as shown in fig. 6, the first request information further includes first data signal information. The host P10 generates first request information according to the first trigger event 21, and further includes: obtaining first data signal information based on the first data packet mapping information file 11; first request information including the first instruction E21 and the first data signal information is transmitted to the waveform display device V1 to request the waveform display device V1 to transmit the first waveform data. For example, the first data signal information may include information such as a name of a data packet signal of waveform data to be acquired and an acquisition time point. The waveform display device V1 transmits corresponding waveform data according to the received first data signal information.

For example, in some embodiments, each entry of the first packet map information file includes a name and signal list of the trigger packet signal. The signal list of the trigger data packet signal includes a collection time corresponding to a data packet signal that the trigger data packet signal needs to collect. For example, the name (trigger) of the trigger packet signal may be consistent with the name of the packet signal determined by the chip design file R. The signal list includes the acquisition time (denoted by value in the packet map information file) of the packet information that needs to be acquired.

For example, in some embodiments, the host P10 obtains the first data signal information based on the first data packet mapping information file, including: the names of the plurality of trigger data packet signals included in the first data packet mapping information file 11 are searched for the names corresponding to the triggered first data packet signals, the first data packet mapping information corresponding to the triggered first data packet signals is determined, and the first signal list to be acquired is determined according to the first data packet mapping information corresponding to the triggered first data packet signals. The first data signal information includes acquisition times of data packet signals to be acquired in the first signal list. For example, when the triggered first packet signal is named BUS1, the signal list including the first packet map information file 11 of which the trigger packet signal is named BUS1 is T0. That is, the packet signal name displayed by the request waveform display device V1 is waveform data of BUS1 at the time point T0.

For example, in other embodiments, the name of the data packet signal that needs to be collected may be different from the name of the first data packet signal that is triggered. At this time, the first data signal information includes the name and the acquisition time of the data packet signal to be acquired. For example, when the first data packet signal to be triggered is named CLK, the signal list including the first data packet mapping information file 11 of the first data packet signal to be triggered is named BUS1 and the time point T0. That is, the packet signal name displayed by the request waveform display device V1 is waveform data of BUS1 at the time point T0.

For example, in some embodiments, as shown in fig. 6, the host P10 requests the waveform display device V1 to transmit the first waveform data, including: the waveform display device V1 obtains the first instruction response function 31 in response to the first instruction E21 based on the instruction map E20, and transmits the first waveform data based on the first instruction response function 31 and based on the first data signal information. For example, the host P10 calls the first instruction E21 by executing the first callback function E11 according to the instruction mapping table E20, so that the first instruction response function 31 of the waveform display apparatus V1 acquires the first waveform data according to the first data signal information in response to the first instruction E21. The waveform display device V1 transmits the first waveform data through the first command response function 31.

For example, the instruction mapping table E20 includes correspondence between a plurality of instructions and corresponding plurality of instruction response functions. For example, the instruction mapping table E20 includes a first instruction E21-a first instruction response function 31, a second instruction E22-a second instruction response function 32, and the like.

For example, in some embodiments, before the host P10 generates the first request information according to the first trigger event 21, the method further includes: the validity of the first trigger event 21 is checked. The validity of the triggered first data packet signal corresponding to the first trigger event 21 is checked and in response to the first trigger event 21 being valid and the triggered first data packet signal being valid, the trigger event-callback function mapping table E10 is looked up. The validity of the check of the first triggering event 21 is already described in detail in fig. 5 and will not be described in detail here.

For example, in some embodiments, the host P10 checks the validity of the triggered first data packet signal corresponding to the first trigger event 21, including: the host P10 searches for a name corresponding to the triggered first data packet signal among the names of the plurality of trigger data packet signals included in the first data packet map information file in response to the name of the triggered first data packet signal, and determines that the triggered first data packet signal corresponding to the first trigger event is valid. For example, when the first data packet signal that is triggered is named CLK, the first data packet map information file 11 includes the name of one of the trigger data packet signals, which is the same as the name of the first data packet signal, as CLK. At this point, the triggered first data packet signal may be determined to be valid.

For example, in some embodiments, as shown in fig. 6, the host P10 runs a first data parsing function J11 that parses the first waveform data from a first format to a second format to obtain first waveform data in a readable text format.

For example, in some embodiments, as shown in fig. 6, the host P10 transmits the second format of the first waveform data to the information display device DISP to display information corresponding to the first waveform data on the information display device DISP. The designer or user can directly judge whether the first data packet signal which is triggered currently accords with the expectation or not according to the information corresponding to the first waveform data displayed on the information display device DISP. For example, the information display device DISP may be a device having a display function such as a display panel.

Fig. 7 is a flowchart of a method for debugging a data waveform according to at least one embodiment of the present disclosure. The debugging method for data waveforms provided by the embodiment of the present disclosure as shown in fig. 7 includes steps S401-S420. Steps S401-S420 show a detailed flow of the debug method for the data waveforms.

Step S401: the designer enters the configuration. For example, the designer chooses to parse the packets of those data protocols. For example, a designer selects a waveform display device that displays waveforms.

Step S402: the host of the debugging analysis platform establishes communication with the waveform display device. For example, the host of the debug analysis platform establishing communication with the waveform display device may include: and establishing a trigger event-callback function mapping table and an instruction mapping table.

Step S403: the host of the debugging analysis platform judges whether the established communication with the waveform display device is effective. That is, the subsequent processing is entered when normal instruction and information interaction with the waveform display device selected by the designer is possible. Until the communication is valid, the process advances to step S404, otherwise, the process stays at step S402.

Step S405: the data packet mapping information file is determined according to the specification file and the chip design file of the data protocol. For example, the designer determines the contents of the packet mapping information file based on the specification file D of the data protocol in which the packet is located, the signal name defined in the chip design file R, and the like. The packet map information file includes a first packet map information file. The first data packet mapping information file comprises the corresponding relation between a plurality of data packet signals and a plurality of corresponding data analysis functions. The specific content included in the first packet mapping information file is not described herein.

Step S406: the debug analysis platform invokes at least one packet map file corresponding to at least one data protocol. For example, the debug analysis platform may call a plurality of data packet mapping files corresponding to a plurality of data protocols, and the debug method may debug the data packet signals of the plurality of data protocols, respectively, to implement general scalability.

Step S404: and loading the first data packet mapping information file by a host of the debugging analysis platform. The first data packet mapping information file is determined according to a specification file and a chip design file of the first data protocol. For example, in some embodiments, the first packet mapping information file to be invoked is determined according to a first data protocol corresponding to a packet in which the first packet signal displayed by the waveform display device is located. For example, when the first data packet signal of the first data protocol is debugged, the host of the debug analysis platform loads the first data packet mapping information file. Unnecessary loading of the packet mapping information file can be avoided.

Step S407: the host of the debugging analysis platform invokes the trigger event-callback function mapping table. For example, the trigger event-callback function mapping table includes correspondence between a plurality of trigger events and a plurality of callback functions, so that when the debug analysis platform receives a first trigger event sent by the waveform display device, a first callback function corresponding to the first trigger event can be found.

Step S408: the debugging analysis platform enters an idle state. For example, the idle state is a state in which the debug analysis platform does not receive a trigger event or waveform data, and at this time, waits for the occurrence of the trigger event of the waveform display device V1.

Step S409: the waveform display device is triggered in response to the displayed first data packet signal. For example, the first data packet signal (e.g., at time T0) displayed by the waveform display device V1 is clicked by a mouse or clicked in a touch-sensitive display screen, etc. The waveform display device V1 generates a first trigger event corresponding to the triggered first data packet signal.

Step S410: the waveform display device transmits a first trigger event. For example, the waveform display device V1 transmits a first trigger event. The transmitted content includes at least the name of the triggered first data packet signal corresponding to the first trigger event.

Step S411: the host of the debugging analysis platform judges whether the event is a valid trigger event. For example, after the first trigger event is received, the idle state in step S408 is entered to determine whether the first trigger event is valid. When the first trigger event is valid, the process advances to step S412.

For example, in some embodiments, the host of the debug analysis platform checks the validity of the triggered first data packet signal while detecting the validity of the first trigger event.

Step S412: and executing a first callback function corresponding to the first trigger event by the host of the debugging analysis platform. For example, a host of the debug analysis platform communicates with the waveform display device during execution of the first callback function, generates first request information according to the first trigger event to request the waveform display device to transmit first waveform data corresponding to the first trigger event, and receives the first waveform data.

Step S413: the host of the debugging analysis platform sends a first instruction and first request information of first data signal information to the waveform display device so as to request the waveform display device to send first waveform data. For example, the first request information includes a first instruction and first data signal information. The first instruction corresponds to a first instruction response function. The first data signal information includes a point in time of a data packet signal that needs to be acquired.

Step S414: the host of the debug analysis platform requests a first instruction response function. For example, the first instruction calls a first instruction response function of the waveform display device V1, and acquires first waveform data based on the first data signal information. The first waveform data is in a first format, for example, a value corresponding to a time point of the data packet signal to be acquired.

Step S415: the waveform display device transmits first waveform data. The waveform display device V1 transmits the first waveform data through the first instruction response function.

Step S416: the host of the debugging analysis platform receives and processes the first waveform data. For example. The test analysis platform receives first waveform data in a first format in response to the first data packet signal and parses the first waveform data from the first format into a second format so that it can be directly known from the first waveform data in the second format whether the first waveform data meets expectations.

Step S417: and the debugging analysis platform queries the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data. For example, the at least one packet mapping information file each includes a plurality of parsing function addresses corresponding to the plurality of packet signals, respectively. The plurality of resolution function addresses are each used to obtain a corresponding data resolution function. For example, the first packet mapping information file includes a resolution function address corresponding to the first waveform data, and a first data resolution function corresponding to the first waveform data is called based on the resolution function address.

For example, as shown in fig. 6, the data parsing function J10 may include a plurality of data, and may be stored in a storage element, such as a read-write memory, that the debug analysis platform P1 can call by parsing a function address. For example, the data parsing function J10 may also be written in the same data file, and each data parsing function is called by a corresponding parsing function address.

Step S418: data parsing functions corresponding to different data protocols are generated according to the specification file. For example, the first data parsing function may include a decoding format of the first waveform data, from which the first waveform data may be parsed into a second format.

Step S419: the host of the debugging analysis platform runs a first data analysis function to analyze the first waveform data from a first format to a second format. For example, in some embodiments, parsing the first waveform data from the first format to the second format includes: the value of the first waveform data is split into at least one domain segment, and the first waveform data is resolved into a second format according to the value of the at least one domain segment.

Step S420: and the host computer of the debugging analysis platform sends the second format of the first waveform data to the information display device so as to display information corresponding to the first waveform data on the information display device. The designer can directly judge whether the first data packet signal triggered currently accords with the expectation or not according to the information corresponding to the first waveform data displayed on the information display device, so that the waveform debugging time is shortened, and the chip development period is shortened.

In the following embodiments, the debugging method provided in the embodiments of the present disclosure will be applied by taking RISC-V instruction data protocol packets and custom protocol packets as examples.

Fig. 8A is a schematic diagram of packet signals of various protocol packets according to at least one embodiment of the present disclosure. In the data waveforms shown in fig. 8A, the first packet signal cpu_inst is a RISC-V instruction protocol packet, and the second packet signal sram_valid is a custom protocol packet.

As shown in fig. 8A, when the user clicks on the T0 time point of the first packet signal cpu_inst using an external device such as a mouse 40, a touch pad, a keyboard, a touch screen, or the like, it is desirable to see what CPU instruction is at the T0 time point. Step S404 in the debugging method shown in fig. 7 loads the packet mapping information file corresponding to the RISC-V instruction data protocol. The specific content of this mapping information file is already given in describing fig. 5 and will not be repeated here. The data packet mapping information file of the RISC-V instruction data protocol is written according to RISC-V instruction specification documents and chip design files. The data parsing function is written according to RISC-V instruction specification documents.

For example, as shown in fig. 8A and 7, the trigger event-callback function mapping table E100 called in step S407 includes "CursorMove: cb_cursormove". When the mouse 40 clicks on the T0 point of the first packet signal cpu_inst, the name of the first trigger event is "CursorMove". In step S411, a trigger event that is valid when the first trigger event is obtained. Obtaining a first callback function corresponding to the first trigger event according to the trigger event-callback function mapping table: cb_cursormove.

For example, as shown in fig. 7, a first callback function is executed in step S412: cb_cursormove. The name "cpu_inst" of the trigger signal is found in the packet map information file corresponding to the RISC-V instruction data protocol packet according to the name "cpu_inst" of the triggered first packet signal corresponding to the first trigger event. Thus, the triggered first packet signal cpu_inst is active.

For example, in step S413 of fig. 7, according to the instruction mapping table E200 shown in fig. 8A, the instruction mapping table E200 includes a first instruction E210 and a first instruction response function: the corresponding relation of getSignalValue, the first callback function: cb_cursmove calls the first instruction E210. The first instruction E210 and the first data signal information are transmitted. The first data signal information is determined according to a data packet mapping information file of the RISC-V instruction data protocol, for example, the first data signal information includes a signal list to be acquired that is cpu_inst [31:0], and the acquisition sequence is "0" (indicating time T0, that is, corresponding to the time when the mouse 40 clicks). The first data signal information indicates the data of cpu_inst [31:0] at time point T0 to be collected.

For example, as shown in fig. 8A, the waveform display apparatus V1 executes a first instruction response function in response to the first instruction D210: getSignalValue obtains first waveform DATA DATA1 in a first format from the first DATA signal information: 0x1c418293. The waveform display device V1 converts the first waveform DATA1 in the first format: 0x1c418293 by a first instruction response function: the getSignalValue is sent out.

For example, in step S416 in fig. 7, the first waveform DATA1 in the first format is received: 0x1c418293 and analyzed. The data packet mapping information file according to RISC-V instruction data protocol data packet includes the resolution function address: riscv.inst.risovinst_player, a first data parsing function corresponding to first waveform data in a first format is obtained. The parsing function riscv.inst.riscvenst_parser parses the value "0x1c418293" of the first waveform DATA1 according to the canonical protocol of the RISC-V instruction DATA protocol, converting the pure value "0x1c418293" into a readable second format. For example, the pure value "0x1c418293" is split into a plurality of field segments according to table 02, and the corresponding CPU instruction is obtained from the value of each field segment. The current CPU instruction is the instruction addi x5, x3, (0 x1c 4) of RISC-V.

For example, as shown in fig. 8A, information corresponding to the first waveform data of the second format displayed on the information display device DISP is as follows.

Trigger signal cpu_inst

Triggering time 30733662.21ps

RISC-V instruction information:

instruction encoding 0x1c418293

Instruction name addi x5, x3, (0 x1c 4)

According to the information corresponding to the displayed first waveform data, whether the data packet where the first waveform data is located accords with the expectation or not can be directly determined, and the waveform debugging method provided by the embodiment of the disclosure can greatly reduce the waveform debugging time and shorten the chip development period.

Fig. 8B is a schematic diagram of packet signals of various protocol packets according to at least one embodiment of the present disclosure. In fig. 8B, compared with fig. 8A, for example, a designer or user clicks on the T0 time point of the second packet signal sram_valid using an external device such as a mouse 40, a touch pad, a keyboard, a touch screen, or the like. The waveform debugging process of the second data packet signal sram_valid is similar to the waveform debugging process of the first data packet signal cpu_inst, but the called data packet mapping information file and the data parsing function are different.

As shown in fig. 8B, when the mouse 40 clicks on the T0 time point of the second packet signal sram_valid, it is desirable to see what command type is at the T0 time point. Step S404 in the debugging method shown in fig. 7 loads the packet mapping information file corresponding to the custom data protocol. The specific content of this mapping information file is already given in describing fig. 5 and will not be repeated here. The data packet mapping information file of the custom data protocol is written according to the custom data protocol specification document and the chip design file. The data analysis function is written according to the custom data protocol specification document.

For example, as shown in fig. 8B and 7, the trigger event-callback function mapping table E100 called in step S407 includes "CursorMove: cb_cursormove". When the mouse 40 clicks on the T0 time point of the second packet signal sram_valid, the name of the first trigger event is "CursorMove". In step S411, a trigger event that is valid when the first trigger event is obtained. Obtaining a first callback function corresponding to the first trigger event according to the trigger event-callback function mapping table: cb_cursormove.

For example, as shown in fig. 7, a first callback function is executed in step S412: cb_cursormove. And finding the name "sram_valid" of the trigger signal in the data packet mapping information file corresponding to the custom data protocol according to the name "sram_valid" of the triggered second data packet signal corresponding to the first trigger event. Thus, the triggered second packet signal sram valid is valid.

For example, in step S413 of fig. 7, according to the instruction mapping table E200 shown in fig. 8B, the instruction mapping table E200 includes a first instruction E210 and a second instruction response function: the corresponding relation of getSignalValue, the first callback function: cb_cursmove calls the first instruction E210. The first instruction E210 and the second data signal information are transmitted. The second data signal information is determined according to the data packet mapping information file of the custom data protocol, for example, the second data signal information includes a signal list to be acquired as sram_valid and sram_dout [63:0], and the acquisition sequence is "0" (indicating time T0, that is, corresponding to the time when the mouse 40 clicks). The second data signal information represents the data of the sram_valid and the sram_dout [63:0] which need to be acquired at the time point T0. Since the sram_valid at time point T0 does not include numerical information, the actual data obtained is the sram_dout [63:0 ].

For example, in other embodiments, the second data signal information includes a list of signals to be acquired as sram_dout [63:0], with an acquisition sequence of "0".

For example, as shown in fig. 8B, the waveform display apparatus V1 executes a first instruction response function in response to the first instruction D210: getSignalValue obtains the second waveform DATA DATA2 in the first format based on the second DATA signal information: 0x3ff40c081. The waveform display device V1 converts the second waveform DATA2 of the first format: 0x3ff40c081 passes through a first instruction response function: the getSignalValue is sent out.

For example, in step S416 in fig. 7, the second waveform DATA2 of the first format is received: 0x3ff40c081 and resolved. According to the analysis function address included in the data packet mapping information file of the custom data protocol: the custom. Packeta. Custompkta_partner obtains a second data parsing function corresponding to the second waveform data in the first format. The second DATA parsing function, custom.packeta.custom kta_parser, parses the value "0x3ff40c081" of the second waveform DATA2 according to the standard protocol of the custom DATA protocol, and converts the pure value "0x3ff40c081" into a readable second format. For example, the net value "0x3ff40c081" is split into a plurality of field segments according to table 01, and the corresponding command type is obtained from the value of each field segment. The current command type is a read command with a host identifier of 0x2 (CPU 2), a SLAVE identifier of 0x3 (SLAVE 3), and a command address of 0x1ffa.

For example, as shown in fig. 8B, information corresponding to the second waveform data of the second format displayed on the information display device DISP is as follows.

Trigger signal of sram_valid

Triggering time 30734362.58ps

Custom packet information:

command type 0x1 (read Command)

Host identifier 0x2 (CPU 2)

Slave identifier 0x3 (SLAVE 3)

Command address 0x1ffa

In the embodiments shown in fig. 8A and 8B, a designer may repeatedly select different signals to analyze and debug, and switch between data packets of different data protocols (for example, by clicking waveforms of different data packets on a waveform display device with a mouse), the waveform debugging method provided in the embodiments of the present disclosure may automatically switch to a data packet signal of a corresponding data protocol, and parse the data packet signal to obtain readable data information, so as to implement general scalability. In addition, the parsing process of the data packet signal in the embodiment shown in fig. 8A and 8B takes little time (total time does not exceed 1 second), so that the efficiency of waveform debugging is greatly improved.

For example, the embodiment of the disclosure also provides a debugging device for the data waveform. Fig. 9 is a schematic structural diagram of a debugging device using data waveforms according to at least one embodiment of the present disclosure.

For example, in some embodiments, as shown in fig. 9, the debugging device 300 includes a data receiving module 310, a mapping information file invoking module 320, a parsing function determining module 330, and a data parsing module 340. For example, the above modules may be implemented using hardware (e.g., FPGA (Field Programmable Gate Array, field programmable gate array)), or software.

For example, in some embodiments, as shown in fig. 9, the data receiving module 310 is configured to receive first waveform data in a first format responsive to a first data packet signal. For example, at least one data packet displayed by the waveform display device is triggered in response to a first data packet signal, and first waveform data in a first format washed in response to the first data packet is received. The first format is a numerical format, for example, a hexadecimal numerical value, and the corresponding content (for example, command type) cannot be directly obtained from the first waveform data in the first format. For example, the waveform display device may be a Verdi waveform display tool.

For example, in some embodiments, the mapping information file invoking module 320 is configured to invoke at least one packet mapping information file corresponding to at least one data protocol. The at least one packet map information file includes a first packet map information file, and each of the at least one packet map information file includes a correspondence of a plurality of packet signals to a corresponding plurality of data parsing functions. For example, the mapping information file invoking module 320 may look up the packet mapping file to obtain a data parsing function corresponding to the packet signal according to the packet signal. For example, corresponding data packet map files are generated or written from specification files of different data protocols and chip design files (e.g., RTL files) in the chip design process.

For example, in some embodiments, the parsing function determination module 330 is configured to query the first packet mapping information file using the first waveform data to obtain a first data parsing function corresponding to the first waveform data. For example, the parsing function determination module 330 obtains a first parsing function address corresponding to the name of the triggered first packet signal in the first packet map information file using the name of the triggered first packet signal. The first analysis function address is used for acquiring a data analysis function corresponding to the first waveform data.

For example, in some embodiments, the data parsing module 340 is configured to run a first data parsing function corresponding to the first waveform data, parsing the first waveform data from a first format to a second format. The first format and the second format are different. For example, the second format is a text format. For example, the first waveform data in the second format is of a command type. According to the first waveform data in the second format, whether the first waveform data in the first format accords with the expectation can be directly obtained, so that whether the data packet where the first data packet signal is located is in error is judged.

The debugging device for data waveforms in the above embodiment improves the efficiency of waveform debugging of data packets in chip design, shortens the chip design period, and the above method for debugging data waveforms can also be used for waveform debugging of data packets of various data protocols to realize universal scalability.

For example, the embodiments of the present disclosure also provide another debugging device for data waveforms. Fig. 10 is a schematic structural diagram of a debugging device using data waveforms according to at least another embodiment of the present disclosure.

For example, as shown in fig. 10, the debugging device 400 for data waveforms is suitable for implementing the debugging method for data waveforms provided by the embodiments of the present disclosure, for example. The debugging device 400 for data waveforms may be a terminal device such as a personal computer, a notebook computer, a tablet computer, or a mobile phone, or may be a workstation, a server, a cloud service, or the like. It should be noted that the debug apparatus 400 for data waveforms shown in fig. 10 is only one example, and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

As shown in fig. 10, the debugging apparatus 400 for data waveforms may include a processing device (e.g., a central processing unit, a graphic processor, etc.) 410, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 420 or a program loaded from a storage device 480 into a Random Access Memory (RAM) 430. In the RAM430, various programs and data required for the operation of the debugging device 400 for data waveforms are also stored. The processing device 410, ROM 420, and RAM430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.

In general, the following devices may be connected to the I/O interface 450: input devices 460 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 470 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, etc.; storage devices 480 including, for example, magnetic tape, hard disk, etc.; a communication device 490. The communication device 490 may allow the debugging apparatus 400 for data waveforms to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 10 shows a debugging apparatus 400 for data waveforms, it should be understood that not all of the illustrated devices are required to be implemented or provided, and that the debugging apparatus 400 for data waveforms may alternatively be implemented or provided with more or fewer devices.

For example, according to embodiments of the present disclosure, the above-described debugging method for data waveforms may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the above-described debugging method for data waveforms. In such embodiments, the computer program may be downloaded and installed from a network via communications device 490, or from storage device 480, or from ROM 420. When executed by the processing device 410, the computer program may perform the functions defined in the debugging method for data waveforms provided by the embodiments of the present disclosure.

For example, the embodiment of the disclosure also provides a debugging system using the data waveform. Fig. 11 is a schematic structural diagram of a debug system using data waveforms according to at least one embodiment of the present disclosure.

For example, in some embodiments, as shown in fig. 11, the debugging system 500 includes the debugging device 300 as shown in fig. 9 or the debugging device 400, the information display device DISP, and the waveform display device V1 as shown in fig. 10.

For example, as shown in fig. 11, the waveform display apparatus V1 is communicatively connected to the debugging apparatus 300/400. The waveform display device V1 is configured to generate and transmit a first trigger event corresponding to the displayed first data packet signal according to an input operation, and transmit first waveform data corresponding to the first trigger event based on the received first request information of the debugging device. For example, in connection with the embodiment shown in fig. 8A, the waveform display apparatus V1 generates a first trigger event CursorMove in response to the data packet signal cpu_inst being triggered, and transmits the first trigger event to the debugging apparatus 300/400. The waveform display device V1 transmits first waveform data corresponding to a first trigger event based on the received first request information of the debugging device according to the instruction mapping table E200. The first request information includes a first instruction E210 and first data signal information. The first instruction E210 invokes a first instruction response function: getSignalValue. The waveform display device V1 obtains first waveform data from the first data signal information in response to the first instruction response function, and transmits the first waveform data to the debugging device 300/400 through the first instruction response function.

For example, as shown in fig. 11, the information display device DISP is communicatively connected to the debugging device 300/400, and the information display device DISP is configured to receive and display the second format of the first waveform data transmitted by the debugging device 300/400. The second format of the first waveform data is readable information of the protocol data packet. The information display device DISP displays readable information of the protocol data packet, for example, a command type, an instruction type, etc. The designer can directly determine whether the data packet signal accords with the expectation according to the information corresponding to the waveform data displayed by the information display device DISP, so that the waveform debugging time is shortened, and the chip development period is shortened.

For example, at least one embodiment of the present disclosure also provides a storage medium storing non-transitory computer program executable code (e.g., computer executable instructions) that, when executed by a computer, can implement the debugging method for a data waveform of any embodiment of the present disclosure; alternatively, the debugging method for data waveforms described in any embodiment of the present disclosure may be implemented when the non-transitory computer program executable code is executed by a computer.

Fig. 12 is a schematic diagram of a storage medium according to at least one embodiment of the present disclosure. As shown in fig. 12, the storage medium 700 non-transitory stores computer program executable code 701. For example, the computer program executable code 701, when executed by a computer, may perform one or more steps in accordance with the debugging method for data waveforms described above.

For example, the storage medium 700 may be applied to the above-described debugging device 400 for data waveforms. For example, the storage medium 700 may be the memory 420 in the debugging device 400 for data waveforms shown in fig. 10. For example, the related description about the storage medium 700 may refer to the corresponding description of the memory 420 in the debugging device 400 for data waveforms shown in fig. 10, and will not be repeated here.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A debug method for a data waveform, comprising:

receiving first waveform data in a first format responsive to a first data packet signal;

invoking at least one data packet mapping information file corresponding to at least one data protocol, wherein the at least one data packet mapping information file comprises a first data packet mapping information file, each of the at least one data packet mapping information file comprises a corresponding relation between a plurality of data packet signals and a corresponding plurality of data analysis functions, and the first data packet mapping information file is determined according to a specification file and a chip design file of a first data protocol, wherein a data packet where the first data packet signals are located corresponds to the first data protocol;

querying the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data; and

running the first data analysis function corresponding to the first waveform data, wherein the first data analysis function is used for analyzing the first waveform data from the first format to the second format according to a specification protocol corresponding to the specification file, the first format is different from the second format, the readability of the waveform data of the second format is higher than that of the waveform data of the first format,

Wherein prior to receiving first waveform data in a first format responsive to the first data packet signal, the method further comprises:

receiving a first trigger event sent by the waveform display device corresponding to the first data packet signal;

generating first request information according to the first trigger event, wherein the first request information comprises first data signal information; and

transmitting the first request information to the waveform display apparatus to request the waveform display apparatus to transmit the first waveform data corresponding to the first trigger event,

wherein the waveform display device is triggered in response to the displayed first data packet signal, generates the first trigger event,

generating first request information according to the first trigger event, including:

obtaining the first data signal information based on the first data packet mapping information file,

wherein each entry of said first data packet map information file comprises a name of a trigger data packet signal and a signal list, said signal list of said trigger data packet signal comprising acquisition times corresponding to data packet signals that said trigger data packet signal needs to acquire,

obtaining the first data signal information based on the first data packet mapping information file includes:

Searching for a name corresponding to the triggered first data packet signal among names of a plurality of trigger data packet signals included in the first data packet map information file, determining the first data packet map information corresponding to the triggered first data packet signal,

determining a first signal list to be acquired according to the first data packet mapping information corresponding to the triggered first data packet signal, wherein the first data signal information comprises acquisition time of the data packet signal to be acquired in the first signal list,

wherein prior to generating the first request message according to the first trigger event, the method further comprises:

checking the validity of the first trigger event.

2. The debugging method of claim 1, wherein generating first request information in accordance with the first trigger event comprises:

calling a trigger event-callback function mapping table;

searching the trigger event-callback function mapping table according to the first trigger event to obtain a first callback function corresponding to the first trigger event; and

obtaining a first instruction corresponding to the first trigger event according to the first callback function to obtain the first request information comprising the first instruction,

Wherein the first instruction is for requesting the waveform display device to transmit the first waveform data,

the trigger event-callback function mapping table comprises the corresponding relation between a plurality of trigger events and a plurality of callback functions.

3. The debugging method of claim 2, wherein sending the first request information to the waveform display device to request the waveform display device to send the first waveform data corresponding to the first trigger event comprises:

transmitting the first request information including the first instruction and the first data signal information to the waveform display device to request the waveform display device to transmit the first waveform data.

4. The debugging method of claim 3, wherein requesting the waveform display apparatus to transmit the first waveform data comprises:

the waveform display apparatus obtains a first instruction response function in response to the first instruction based on an instruction map, and transmits the first waveform data based on the first instruction response function and based on the first data signal information,

the instruction mapping table comprises the corresponding relation between a plurality of instructions and corresponding response functions of the instructions.

5. The debugging method of claim 2, further comprising, prior to generating the first request information in accordance with the first trigger event:

checking the validity of the triggered first data packet signal corresponding to the first trigger event,

and searching the trigger event-callback function mapping table in response to the first trigger event being valid and the triggered first data packet signal being valid.

6. The debugging method of claim 5, wherein,

checking the validity of the first trigger event, including:

determining that the first trigger event is valid in response to the trigger event-callback function mapping table including a correspondence corresponding to the first trigger event;

checking the validity of the triggered first data packet signal corresponding to the first trigger event, comprising:

and searching for the name of the first data packet signal corresponding to the trigger among the names of the plurality of trigger data packet signals included in the first data packet mapping information file in response to the name of the first data packet signal to be triggered, and determining that the first data packet signal corresponding to the first trigger event to be triggered is valid.

7. The debugging method of claim 6, wherein,

the at least one data packet mapping information file each comprises a plurality of resolution function addresses corresponding to the plurality of data packet signals respectively,

the plurality of resolution function addresses are each used to obtain a corresponding data resolution function.

8. The debugging method of claim 7, wherein,

the at least one packet map information file includes a plurality of packet map information files including the first packet map information file, and a first resolution function address corresponding to the name of the triggered first packet signal is acquired in the first packet map information file using the name of the triggered first packet signal.

9. The debug method according to any one of claims 1 to 8, further comprising, prior to receiving first waveform data in a first format in response to said first data packet signal:

loading the at least one packet mapping information file, and

communication with the waveform display apparatus is established.

10. The debugging method of any of claims 1-8, further comprising:

and determining the first data packet mapping information file to be called according to a first data protocol corresponding to the data packet where the first data packet signal is displayed by the waveform display device.

11. The debugging method of claim 1, further comprising:

and sending the second format of the first waveform data to an information display device so as to display information corresponding to the first waveform data on the information display device.

12. The debugging method of claim 11, wherein,

the second format is a text format.

13. The debug method of any of claims 1-8 and 11-12, wherein parsing the first waveform data from the first format to the second format comprises:

splitting the value of the first waveform data into at least one domain segment according to a specification file of a first data protocol corresponding to the first data packet signal,

and analyzing the first waveform data into the second format according to the numerical value of the at least one domain segment.

14. A debug apparatus for a data waveform, comprising:

a data receiving module configured to receive first waveform data in a first format in response to a first data packet signal;

the mapping information file calling module is configured to call at least one data packet mapping information file corresponding to at least one data protocol, wherein the at least one data packet mapping information file comprises first data packet mapping information files, each of the at least one data packet mapping information files comprises a corresponding relation between a plurality of data packet signals and a corresponding plurality of data analysis functions, and the first data packet mapping information files are determined according to a specification file and a chip design file of a first data protocol, wherein a data packet where the first data packet signals are located corresponds to the first data protocol;

The analysis function determining module is configured to query the first data packet mapping information file by using the first waveform data to obtain a first data analysis function corresponding to the first waveform data; and

a data parsing module configured to run the first data parsing function corresponding to the first waveform data, where the first data parsing function is configured to parse the first waveform data from the first format to a second format according to a specification protocol corresponding to the specification file, where the first format is different from the second format, and the second format has higher readability than the waveform data of the first format,

wherein, prior to receiving first waveform data in a first format responsive to the first data packet signal, the debugging device is further configured to:

wherein generating first request information according to the first trigger event includes:

wherein each entry of the first data packet map information file includes a name of a trigger data packet signal and a signal list including an acquisition time corresponding to a data packet signal that the trigger data packet signal needs to acquire,

Wherein the commissioning device is further configured to: and checking the validity of the first trigger event before generating the first request information according to the first trigger event.

15. A debug apparatus for a data waveform, comprising:

a processor; and

a memory, wherein the memory has stored therein computer executable code which, when executed by the processor, performs the debugging method for a data waveform of any of claims 1-13.

16. A debug system for a data waveform, comprising:

the debugging device of claim 14 or 15,

a waveform display device which is connected with the debugging device in a communication way,

wherein the waveform display device is configured to generate and transmit a first trigger event corresponding to the displayed first data packet signal according to an input operation, and transmit the first waveform data corresponding to the first trigger event based on the received first request information of the debugging device.

17. The debug system of claim 16, further comprising:

and the information display device is in communication connection with the debugging device and is configured to receive and display a second format of the first waveform data sent by the debugging device.

18. A computer readable storage medium having stored thereon executable code which when executed by a processor causes the processor to perform the debugging method for a data waveform of any of claims 1-13.