WO2021128165A1

WO2021128165A1 - Formal verification method and device, information identification method and device, and storage medium

Info

Publication number: WO2021128165A1
Application number: PCT/CN2019/128715
Authority: WO
Inventors: 刘其龙; 冯鲲鹏; 唐辉艳
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2021-07-01
Also published as: CN112567375A

Abstract

Provided are a formal verification method and device, an information identification method and device, and a storage medium. The formal verification method comprises: acquiring a first file and a second file, wherein the second file is obtained according to the first file (S501); determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises the correlation between data units in the first file and data units in the second file (S502); and performing formal verification on the second file according to the unit matching information and the first file (S503). The method improves the reliability of the formal verification of a second file.

Description

Formal verification method, information identification method, equipment and storage medium

Technical field

The embodiments of the present invention relate to the technical field of chip design, in particular to a formal verification method, an information identification method, equipment, and storage medium.

Background technique

With the rapid development of chip technology, the application of very large scale integrated circuits has become more and more extensive. At present, electronic design automation (Electronics Design Automation, abbreviated, EDA) tools are usually used to design chips. In the process of chip design, formal verification is required for each implementation step. The purpose of formal verification can ensure that the design before and after identical.

In the process of designing the chip, the EDA tool will change the naming of the various components in the design for various reasons at various stages. At this time, if the EDA tool provided by the same supplier is used, the EDA tool can adopt a unified file name matching method and search method, so that the entire formal verification process can be realized. If EDA tools provided by different vendors are used for formal verification, the EDA tools cannot recognize formal verification files due to the mismatch of unit naming information of cross-vendor EDA tools, file encryption, or incompatibility between tools from different vendors. For the formal verification tools of different manufacturers, the difficulty of formal verification is increased, and normal formal verification operations cannot even be performed.

Summary of the invention

The embodiments of the present invention provide a formal verification method, information identification method, equipment and storage medium.

The first aspect of the present invention is to provide a formal verification method, including:

Obtaining a first file and a second file, the second file being obtained according to the first file;

Determine unit matching information corresponding to the first file and the second file, where the unit matching information includes the correspondence between the data unit in the first file and the data unit in the second file relationship;

Perform formal verification on the second file according to the unit matching information and the first file.

The second aspect of the present invention is to provide an information identification method, including:

Acquiring a first file and a second file, where the second file is obtained based on the first file, and the second file includes at least one data unit;

Determine unit matching information corresponding to the second file and the first file, where the unit matching information includes the at least one data unit in the second file and the data unit in the first file Correspondence between;

The unit matching information is used to identify the data unit in the second file.

The third aspect of the present invention is to provide a method for identifying name information, including:

Acquiring the first name information of the data unit;

When the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determine the name corresponding to the first name information and the second name information Matching information

Sending the name matching information to a second electronic design tool for the second electronic design tool to identify the correspondence between the first name information and the second name information; and

Wherein, the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different .

The fourth aspect of the present invention is to provide a formal verification device, including:

The first memory is used to store computer programs;

The first processor is configured to run a computer program stored in the first memory to implement:

The fifth aspect of the present invention is to provide an information recognition device, including:

The second memory is used to store computer programs;

The second processor is configured to run a computer program stored in the second memory to implement:

The sixth aspect of the present invention is to provide a name information recognition device, including:

The third storage is used to store computer programs;

The third processor is configured to run the computer program stored in the third memory to implement:

Acquiring the first name information of the data unit;

The seventh aspect of the present invention is to provide a computer-readable storage medium, the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used in the first aspect. The formal verification method described.

The eighth aspect of the present invention is to provide a computer-readable storage medium, the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used in the second aspect. The information identification method described.

The ninth aspect of the present invention is to provide a computer-readable storage medium, the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used in the third aspect. The name information identification method described.

The formal verification method, information identification method, equipment, and storage medium provided by the embodiments of the present invention effectively ensure the stability and reliability of the formal verification operation.

Description of the drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The exemplary embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation of the application. In the attached picture:

FIG. 1 is a flow chart of the implementation of a very large scale integrated circuit provided by an embodiment of the present invention;

FIG. 2 is a flowchart of design using an electronic design automation tool provided by an embodiment of the present invention;

Figure 3 is a simplified schematic diagram of the formal verification operation shown in Figure 2;

Fig. 4 is a schematic diagram of the principle of formal verification shown in Fig. 3;

Figure 5 is a flowchart of a formal verification method provided by an embodiment of the present invention;

FIG. 6 is a flowchart of obtaining the first file and the second file in the formal verification method shown in FIG. 5;

FIG. 7 is a flowchart of obtaining the integrated netlist and the layout netlist in FIG. 6;

FIG. 8 is a flowchart of another formal verification method provided by an embodiment of the present invention;

FIG. 9 is a flowchart of an information identification method provided by an embodiment of the present invention;

FIG. 10 is a flowchart of a method for identifying name information according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a formal verification device provided by an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of an information recognition device provided by an embodiment of the present invention;

FIG. 13 is a schematic structural diagram of a name information identification device provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention.

With the rapid development of chip technology, the application of very large scale integrated circuits has become more and more extensive. Usually electronic design automation (Electronics Design Automation, referred to as EDA) tools are used to design the chip. The implementation process is shown in Figure 1, which mainly includes: designers try hardware description languages (VHDL, Verilog, or HDL, etc.) to design functions with The code is described to form the Register Transfer Level (RTL) code. Then, the RTL code is logically synthesized into a comprehensive netlist, and the layout and routing process is performed based on the comprehensive netlist to obtain the physical layout design. Perform verification and other operations on the physical layout design.

Specifically, as shown in Figure 2, a flow chart for designing using EDA tools is provided. Specifically, the design process mainly includes: obtaining RTL design code, synthesizing and optimizing the RTL design code, and obtaining the first network After the first netlist passes the formal verification, scan chain stitching can be performed based on the first netlist to obtain the second netlist. After the second netlist passes the formal verification, the physical layout design can be based on the second netlist , Obtain the third netlist, and then perform formal verification operations on the third netlist.

In the above design process, formal verification is required between each step, and the purpose of formal verification is to ensure that the design before and after are the same. At present, the existing EDA tools change the naming of the components of each register in the design for various reasons at various stages, such as: register merging unit, register ungrouping unit, etc. Under normal circumstances, if the design tool provided by an EDA supplier is selected for the entire design process, the design tool can read the register unit normally. As shown in Figure 3, the design process of the first design A using the first design tool is After the second design B, if the first design tool is used for formal verification, the entire formal verification process can be stably realized. Specifically, as shown in Figure 4, the implementation process of formal verification may include: starting formal verification, loading reference information, loading tools, loading wizard information, executing settings, matching comparison points, running formal verification operations, obtaining verification results, and then The verification result can be analyzed and processed to determine whether the formal verification operation is successful. If the formal verification operation is successful, the formal verification operation is completed; if the formal verification operation is unsuccessful, debugging is performed.

In the above process, the matching comparison point is the most critical step. Generally, the design tool can be used to automatically perform the matching operation. After an abnormality occurs at the matching comparison point, for example, due to incompatibility between the design tools of different manufacturers, it cannot be used universally between the tools of different manufacturers. At this time, in the process of formal verification, it is easy to appear inconsistent unit naming information. In the case of matching and unable to find, you need to search for the error in the results of each stage, and you need to manually add commands to match. This will not only lower the efficiency of formal verification and higher labor costs, but also easily delay the progress of the project, and It is not easy to automate the process; in addition, for users who use multiple EDA tools, it also increases the difficulty of formal verification, and at the same time, debugging is also a great obstacle.

In the following, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. As long as there is no conflict between the embodiments, the following embodiments and the features in the embodiments can be combined with each other.

FIG. 5 is a flowchart of a formal verification method provided by an embodiment of the present invention; referring to FIG. 5, this embodiment provides a formal verification method, and the execution subject of the method is a formal verification device. It can be understood that The formal verification device can be implemented as software or a combination of software and hardware. Specifically, the formal verification method may include:

Step S501: Obtain a first file and a second file, and the second file is obtained based on the first file.

Step S502: Determine unit matching information corresponding to the first file and the second file, and the unit matching information includes the correspondence between the data unit in the first file and the data unit in the second file.

Step S503: Perform formal verification on the second file according to the unit matching information and the first file.

The following is a detailed description of the above steps:

The first file may include an integrated netlist corresponding to the chip design code, and the second file may include a layout netlist corresponding to the integrated netlist. Specifically, after obtaining the chip design code, the EDA tool can be used to perform logic synthesis processing on the chip design code to obtain a comprehensive netlist corresponding to the chip design code; after the comprehensive netlist is obtained, it can be performed based on the comprehensive netlist. Place and route processing to obtain the layout netlist corresponding to the integrated netlist.

It is understandable that the information represented by the first file and the second file is not limited to the comprehensive netlist and layout netlist exemplified above, and those skilled in the art can set it according to specific application requirements and design requirements, for example: The first file may include source program files, and the second file may include a comprehensive netlist corresponding to the chip design code; alternatively, the first file may include a comprehensive netlist corresponding to the chip design code, and the second file may include A netlist generated after the test; or, the first file may include a netlist generated after a logical test, and the second file may include a layout netlist and so on.

After the first file and the second file are obtained, the first file and the second file can be analyzed and processed to determine the unit matching information corresponding to the first file and the second file according to the analysis and processing result. In some examples, In the formal verification process, if the name information of at least one data unit in the first file does not correspond to the name information of all data units in the second file, the unit corresponding to the first file and the second file can be determined Matching information. The unit matching information may include the correspondence between the data unit in the first file and the data unit in the second file.

In other examples, when the name information of at least one data unit in the second file does not correspond to the name information of all data units in the first file, it can be determined that the second file and the first file correspond to the name information. Unit matching information. The unit matching information may include the correspondence between the data unit in the second file and the data unit in the first file.

In other instances, in the formal verification process, if the data unit in the second file cannot be identified and the name information of the above data unit can be obtained, it is determined that the units corresponding to the first file and the second file match The unit matching information may include the correspondence between the name information of the data unit in the second file, the data unit in the first file and the name information of the data unit, based on the unit matching information and the name of the data unit Information to determine unrecognized data units in the second file.

In other instances, in the formal verification process, if the data unit in the second file and the name information corresponding to the data unit cannot be identified, and the input and output relationship of the data unit can be identified, it is determined to be The unit matching information corresponding to the second file and the first file. The unit matching information may include the corresponding relationship between the input/output relationship of each data unit in the second file and the input/output relationship of each data unit in the first file, so as to determine the second based on the unit matching information and the input/output relationship. The unrecognized data unit in the file and the name information corresponding to the data unit.

For example, the first file includes data unit A, data unit B, and data unit C. The names corresponding to the aforementioned data unit A, data unit B, and data unit C are name a, name b, and name c, respectively; The file includes data unit A`, data unit B` and data unit C`. The names corresponding to the above data unit A`, data unit B` and data unit C` are name a`, name b` and name c`, respectively ; Among them, the data unit A corresponds to the data unit A', the data unit B corresponds to the data unit B', and the data unit C corresponds to the data unit C'.

In one embodiment, data unit A, data unit B, and data unit C in the first file are data unit A', data unit B', and data unit C'in the second file, respectively. That is, the data unit A, data unit B, and data unit C in the first file have the same functions and/or types as the data unit A`, data unit B`, and data unit C` in the second file, but , The names of data unit A, data unit B, and data unit C in the first file are different from the names of corresponding data unit A', data unit B', and data unit C'in the second file.

In one embodiment, because the name information of the data unit in the first file is different from that in the second file, when performing formal verification on the second file, it may not be possible to identify the data unit corresponding to at least one data unit in the second file. Name information, for example: the name b` of the data unit B` cannot be recognized. When performing formal verification, for the data unit B'in the second file, it is impossible to determine which data unit in the first file this data unit B'corresponds to. Or, for the data unit B in the first file, it is impossible to determine which data unit in the second file this data unit B corresponds to. At this time, in order to be able to perform formal verification operations on the first file and the second file, the unit matching information corresponding to the first file and the second file can be determined, and the determined unit matching information can include the unit matching information in the first file. The corresponding relationship between the data unit and the data unit in the second file, that is, the unit matching information at this time includes the corresponding relationship between the data unit B` and the data unit B (for example, the name of the data unit B` and the data unit B The corresponding relationship between the data unit B'and the input/output relationship of the data unit B); the acquired unit matching information can facilitate stable formal verification operations on the first file and the second file.

Since the name information of the data unit in the first file is different from that in the second file, when performing formal verification on the second file, it may not be possible to identify the first file corresponding to at least one data unit in the second file. Data unit. In other words, when performing formal verification on the second file, it may also appear that the name information of at least one data unit in the second file does not correspond to the name information of all the data units in the first file. In one embodiment, the data unit corresponding to the function and/or type of the data unit in the second file cannot be identified in the first file. For example, for the second file, the data unit B` of the second file and the name b` corresponding to the data unit B` can be identified, and for the first file, the data unit B and the data unit B of the first file can be identified. The corresponding name b. However, it cannot be recognized that the data unit B'of the second file corresponds to the data unit B of the first file. Or it is impossible to identify the name b of the data unit B of the second file corresponding to the name b of the data unit B of the first file. For another example, for the first file, the data unit B of the first file and the name b corresponding to the data unit B can be identified. For the second file, the data unit B'of the second file and the name b'corresponding to the data unit B'can be identified. However, it cannot be recognized that the data unit B of the first file corresponds to the data unit B'of the second file. Or the name b of the data unit B of the first file cannot be identified corresponding to the name b` of the data unit B of the second file. At this time, the unit matching information corresponding to the first file and the second file is determined, and the determined unit matching information may include the correspondence between the data unit in the first file and the data unit in the second file, that is, The unit matching information includes the correspondence between the name b'of the data unit B'and the data unit B and the name b. Therefore, the acquired unit matching information facilitates stable formal verification operations on the first file and the second file.

In some examples, determining the unit matching information corresponding to the first file and the second file may include: obtaining the input correspondence relationship for the register unit based on the integrated netlist and the layout netlist. According to the input correspondence, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained.

Specifically, after the comprehensive netlist and the layout netlist are obtained, the comprehensive netlist and the layout netlist can be analyzed and processed, so as to obtain the input and output corresponding relationship for the register unit, and then the input and output corresponding relationship can be obtained and integrated according to the input and output relationship. The unit matching information corresponding to the netlist and the layout netlist.

For example, if the input-output connection relationship of register unit A in the integrated netlist is consistent or similar to the input-output connection relationship of register unit C in the layout netlist, then the register unit A in the integrated netlist and the layout netlist Corresponding to the register unit C. That is, the register unit A in the integrated netlist matches the register unit C in the layout netlist. In one embodiment, the integrated netlist includes register unit A, and the input signal of register unit A is the output signal of register unit B. At this time, the layout netlist includes register unit C. When the input signal is the output signal of the register unit B`, and the register unit B` corresponds to the register unit B, and the register A and the register C have no other components directly connected to them respectively, the register unit A in the integrated netlist is considered Corresponds to register unit C in the layout netlist. That is, the register unit A in the integrated netlist matches the register unit C in the layout netlist. In addition, a unit matching relationship is generated, and the unit matching information indicates that the register unit A of the integrated netlist corresponds to the register unit C of the layout netlist.

It is understandable that the correspondence relationship existing in the unit matching information can be a one-way correspondence relationship, for example: the correspondence relationship from the register unit A of the integrated netlist to the register unit C of the layout netlist, or the layout netlist The corresponding relationship between the register unit C of the integrated netlist and the register unit A of the integrated netlist; or, the corresponding relationship existing in the unit matching information can also be a two-way corresponding relationship, that is, it can include: from the register unit A of the integrated netlist to the layout The correspondence between the register unit C of the netlist and the correspondence between the register unit C of the layout netlist and the register unit A of the integrated netlist.

In other examples, determining the unit matching information corresponding to the first file and the second file may include: obtaining the correspondence between the input and output components of the register unit and the register unit name correspondence based on the integrated netlist and the layout netlist relationship. According to the corresponding relationship between the input and output components of the register unit and the corresponding relationship between the name of the register unit, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained. For example, if the name of the first register unit in the integrated netlist and the name of the second register unit in the layout netlist have the same keyword, the first register unit in the integrated netlist and the second register unit in the layout netlist The register unit corresponds.

Specifically, after the comprehensive netlist and the layout netlist are obtained, the comprehensive netlist and the layout netlist can be analyzed and processed, so as to obtain the input correspondence and the name correspondence for the register unit, and then the input correspondence and the name correspondence may be obtained according to the input correspondence and The name correspondence relationship obtains the unit matching information corresponding to the integrated netlist and the layout netlist.

For example, the comprehensive netlist includes register unit A, the name information of register unit A is name information a, and the input information of register unit A is register unit B. At this time, the register unit is included in the layout netlist C, the name information of the register unit C is the name information c, the input information of the register unit C is the register unit B`, and when the register unit B` corresponds to the register unit B, unit matching information can be generated, and the unit matches The information includes the corresponding relationship between the register unit A and the register unit C, and/or the corresponding relationship between the name information a and the name information c. The corresponding relationship included in the unit matching information is similar to the corresponding relationship in the foregoing embodiment, that is, the corresponding relationship The relationship can be a one-way correspondence or a two-way correspondence.

After the unit matching information is obtained, the second file can be formally verified based on the unit matching information and the first file, thereby effectively ensuring the stability and reliability of the formal verification of the second file.

The formal verification method provided in this embodiment determines the unit matching information corresponding to the first file and the second file by acquiring the first file and the second file, and then performs the second file based on the unit matching information and the first file. Formal verification, since the unit matching information can include the correspondence between the data unit in the first file and the data unit in the second file, it can be realized when formal verification devices from different vendors are used for formal verification. It can also perform formal verification operations stably and effectively, which not only guarantees the quality and efficiency of formal verification operations, but also reduces the difficulty of formal verification for users who use multiple EDA tools. At the same time, it is also useful for debugging. It provides great convenience and further improves the practicability of the method.

Fig. 6 is a flowchart of obtaining the first file and the second file in the formal verification method shown in Fig. 5; on the basis of the above-mentioned embodiment, referring to Fig. 6, the first file includes the code corresponding to the chip design For the corresponding integrated netlist, when the second file includes the layout netlist corresponding to the integrated netlist, acquiring the first file and the second file in this embodiment may include:

Step S601: Obtain a comprehensive netlist corresponding to the chip design code, and the comprehensive netlist includes a register unit.

Step S602: Obtain the layout netlist based on the integrated netlist, and the name information of the register unit in the integrated netlist is different from the name information of the corresponding register unit in the layout netlist.

Among them, after obtaining the chip design code, logic synthesis processing can be performed on the chip design code, so that a comprehensive netlist corresponding to the chip design code can be obtained. At this time, the comprehensive netlist may include one or more register units; After the comprehensive netlist is obtained, the comprehensive netlist can be analyzed and processed to obtain the layout netlist. Specifically, the process of obtaining the layout netlist based on the comprehensive netlist may include: using a preset tool to place and route the comprehensive netlist Process to obtain the layout netlist corresponding to the integrated netlist; at this time, the name information of the register unit in the integrated netlist is different from the name information of the corresponding register unit in the layout netlist.

It is understandable that the comprehensive netlist can include all the first register units and the first name information corresponding to the first register unit; the layout netlist can include all the second register units and the second register unit. Corresponding second name information; the first register unit in the integrated netlist corresponds to the second register unit in the layout netlist.

It should be noted that the preset tool can be a preset EDA tool used to perform placement and routing processing on the integrated netlist. The preset tool and the formal verification device can belong to the same supplier, or the preset tool and formal verification The equipment can also belong to different suppliers. As shown in Figure 7, the comprehensive netlist can be processed by the preset tool to obtain the layout netlist. At this time, the preset tool can generate unit matching information, and then can be based on the unit matching information and The first file, formal verification of the second file.

In this embodiment, by obtaining the integrated netlist corresponding to the chip design code, and then obtaining the layout netlist based on the integrated netlist, the accurate and reliable acquisition of the integrated netlist and the layout netlist is effectively ensured.

Fig. 8 is a second flowchart of a formal verification method provided by an embodiment of the present invention; in the above-mentioned embodiment, referring to Fig. 8, the method in this embodiment can be applied to a formal verification device. When performing formal verification operations, the following situations may occur: in the first file, the data unit or the name information of the data unit in the first file corresponding to at least one data unit in the second file cannot be identified, or, In the second file, the data unit or the name information of the data unit in the second file corresponding to the name information of at least one data unit in the first file cannot be identified. For the convenience of description, the foregoing situations in the formal verification device are collectively referred to as the inability of the formal verification device to recognize the register unit. Specifically, the method may include:

Step S801: Check whether the formal verification device and the preset tool belong to the same supplier.

Step S802: When the formal verification device and the preset tool belong to different suppliers, it is determined that the formal verification device cannot recognize the correspondence between the register units respectively located in different files generated by the preset tool. or,

Step S803: When the formal verification device and the preset tool belong to the same supplier, it is determined that the formal verification device can identify the register unit.

After obtaining the formal verification equipment and preset tools, in order to ensure the quality and efficiency of the formal verification operation, the formal verification equipment and preset tools can be tested, that is, whether the formal verification equipment and the preset tools belong to the same supplier Specifically, the identification information of the first supplier of the formal verification device and the identification information of the second supplier of the preset tool can be obtained. The identification information of the first supplier and the second supplier identification information can be used to detect whether the formal verification device is connected to the preset tool. Whether the tools belong to the same supplier. When the identification information of the first supplier and the identification information of the second supplier are the same, it can be determined that the formal verification device and the preset tool belong to the same supplier, and the formal verification device at this time can identify the register unit. When the first supplier identification information and the second supplier identification information are different, it can be determined that the formal verification device and the preset tool belong to different suppliers, and it can be determined that the formal verification device cannot identify the register unit.

In some instances, after determining that the formal verification device can identify the register unit, the method further includes:

Step S804: Perform formal verification on the layout netlist by using the formal verification device and the integrated netlist.

Among them, when the formal verification device can identify the register unit, it can directly use the formal verification device and the integrated netlist to perform formal verification on the layout netlist, thereby improving the quality and efficiency of formal verification.

It should be noted that the above steps are optional steps, that is, when the layout netlist is configured to perform formal verification operations, the method in this embodiment may include the above step S804; if there is no configuration to perform formal verification on the layout netlist During the operation, the method in this embodiment does not include the above step S804.

In specific applications, the first file can be a comprehensive netlist corresponding to the chip design code, and the second file can be a layout netlist corresponding to the comprehensive netlist, and the comprehensive netlist is placed and routed through a preset tool. So you can get the layout netlist. Then take the use of a formal verification device belonging to a different vendor from the preset tool to perform formal verification operations on the layout netlist as an example. Because the name information of the register unit in the integrated netlist is different from the name information of the register unit in the layout netlist , Therefore, the formal verification operation can be realized through the unit matching information. Specifically, the formal verification method may include:

Step 1: Use the preset tool to analyze and process the comprehensive netlist to obtain the layout netlist. Specifically, when the layout netlist is obtained, the marking information corresponding to the preset tool can be added to the layout netlist.

Step 2: Use the preset tool to automatically generate unit matching information, which corresponds to the integrated netlist and the layout netlist.

Specifically, the script in the preset tool can be used to automatically generate unit matching information. The unit matching information can include the input correspondence between the register units in the layout netlist after the register units in the comprehensive netlist are processed by the preset tool. relationship.

Step 3: Use formal verification equipment and unit matching information to perform formal verification operations on the layout netlist.

Among them, the operation process of the formal verification includes the matching of the register unit, and the formal verification after the matching is to verify whether the input signals of the matching unit are the same, so as to determine whether the formal verification is successful. Specifically, after the unit matching information is obtained, the corresponding relationship between the naming information of the register unit in the layout netlist and the naming information of the register unit in the comprehensive netlist can be determined based on the unit matching information, so that the layout can be realized based on the unit matching information. The netlist performs formal verification operations.

The formal verification method provided by this application embodiment takes into account the incompatibility characteristics of different design tools. At the same time, in order to ensure the quality and efficiency of the formal verification operation, when the name information of any register unit changes, unit matching information can be generated, and then When using different design tools for formal verification, the unit matching information can be used to identify the register unit, thereby ensuring the accuracy of the matching of the name information of the register unit. It should be noted that this method can process a large number of files. In turn, the scope of application of the method is improved; at the same time, the efficiency and success rate of formal verification are also improved, and the possibility of data loss during the file conversion process is also reduced, which is convenient for query and location of subsequent debugging problems.

FIG. 9 is a flowchart of an information recognition method provided by an embodiment of the present invention; referring to FIG. 9, this embodiment provides an information recognition method, and the execution subject of the method is an information recognition device, and it can be understood that The information recognition device can be implemented as software or a combination of software and hardware. Specifically, the information identification method may include:

Step S901: Obtain a first file and a second file. The second file is obtained from the first file, and the second file includes at least one data unit.

Step S902: Determine unit matching information corresponding to the second file and the first file. The unit matching information includes the correspondence between at least one data unit in the second file and the data unit in the first file.

Step S903: Use the unit matching information to identify the data unit in the second file.

The following is a detailed description of the above steps:

In some examples, the first file includes an integrated netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the integrated netlist; or, the first file includes source program files, and the second file includes The integrated netlist corresponding to the chip design code; or, the first file includes the integrated netlist corresponding to the chip design code, and the second file includes the netlist generated after logic testing; or, the first file includes logic testing The generated netlist, the second file includes the layout netlist.

It is understandable that when the first file and the second file represent different information, at least one data unit included in the second file may also have different manifestations. For example, when the second file is a netlist file, The at least one data unit included in the second file may be at least one register unit. Similarly, when the first file is a netlist file, the first file may include at least one register unit, and the name information of the at least one register unit in the first file is different from the name information of the corresponding register unit in the second file.

In some instances, the second file is obtained by processing the first file by the first electronic design automation tool; the first file, the second file, and the unit matching information are used for data processing of the second electronic design automation tool at the same time, Among them, the first electronic design automation tool is different from the second electronic design automation tool.

Further, when it is detected that the first electronic design automation tool changes at least one first data unit in the first file and generates at least one data unit stored in the second file, determine at least one data unit in the second file Corresponding to at least one first data unit in the first file.

Further, the first file, the second file, and the unit matching information are used for the data processing of the second electronic design automation tool at the same time, including: the first file and the unit matching information are used for the second electronic design automation tool to the second file at the same time. The formal verification process.

In some instances, when the name information corresponding to at least one data unit in the second file cannot be identified, the unit matching information corresponding to the first file and the second file is determined; or, when in the first file, it cannot be When a data unit corresponding to the name information of at least one data unit in the second file is identified, the unit matching information corresponding to the second file and the first file is determined.

Specifically, determining the unit matching information corresponding to the second file and the first file may include: obtaining input correspondence and name correspondence for the register unit based on the first file and the second file; and according to the input correspondence and name correspondence The relationship obtains unit matching information corresponding to the first file and the second file.

In some instances, determining the unit matching information corresponding to the second file and the first file may include: obtaining the input correspondence relationship of at least one data unit based on the first file and the second file; and obtaining the input correspondence relationship with the first file according to the input correspondence relationship. The file and the unit matching information corresponding to the second file.

After the unit matching information is obtained, the unit matching information can be used to identify the data unit in the second file, which effectively guarantees the accuracy and reliability of information identification, thereby facilitating the application and processing of the second file.

It should be noted that the specific implementation process, implementation effect, and implementation principle of the above method steps in this embodiment are similar to the specific implementation process, implementation effect, and implementation principle of the method of the embodiment shown in Figure 5 to Figure 8 in the above example. For parts that are not described in detail in this embodiment, reference may be made to related descriptions of the embodiments shown in FIGS. 5 to 8. Refer to the description in the embodiment shown in FIG. 5 to FIG. 8 for the execution process and technical effect of this technical solution, and will not be repeated here.

10 is a flowchart of a method for identifying name information provided by an embodiment of the present invention; referring to FIG. 10, this embodiment provides a method for identifying name information, and the subject of the method is a name information identifying device. It is understood that the name information identification device can be implemented as software or a combination of software and hardware. Specifically, the name information identification method may include:

Step S1001: Obtain the first name information of the data unit.

Step S1002: When the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determine the name matching information corresponding to the first name information and the second name information.

Step S1003: Send the name matching information to the second electronic design tool for the second electronic design tool to identify the correspondence between the first name information and the second name information.

Among them, the first electronic design tool and the second electronic design tool are different; at this time, when the first electronic design tool is used to change the data unit from the first name information to the second name information, in order to ensure that other electronic design tools (section The second electronic design tool) can accurately identify the second name information of the data unit, and the first electronic design tool can determine the name matching information corresponding to the first name information and the second name information. Specifically, the first name information of the data unit is stored in the first file, and the second name information of the data unit is stored in the second file. At this time, the name matching information can be understood as corresponding to the first file and the second file. Correspondence of the name of the data unit. In some instances, during the chip design process, the first file is generated before the second file. Alternatively, the first file and the second file are both files generated during the chip design process, and the first file is used to generate the second file.

In some instances, the second electronic design tool is used for the formal verification of chip design. At this time, after the second electronic design tool obtains the name matching information, the second file can be performed based on the name matching information and the above-mentioned first file. Formal verification to ensure that the first document and the second document meet the preset requirements.

In some instances, the name matching information may include first name information, second name information, and an index between the first name information and the second name information; or, the name matching information includes first name information, second name information Information, and an index between the second name information and the first name information; or, the name matching information may also include: the first name information, the second name information, and the index between the first name information and the second name information Bidirectional index information.

After the name matching information is determined, the name matching information can be sent to the second electronic design tool. At this time, the second electronic design tool can identify the second name information of the data unit in the second file and the first file based on the name matching information. The corresponding relationship between the first name information of the data unit in the data unit, thereby realizing effective identification of the data unit.

The name information identification method provided in this embodiment determines the first name by acquiring the first name information of the data unit, and when the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit The information corresponds to the name matching information of the second name information, and the name matching information is sent to the second electronic design tool, which effectively ensures that the second electronic design tool can identify the corresponding relationship between the first name information and the second name information , Which effectively guarantees the accuracy and reliability of name information identification, facilitates the use of different electronic design tools to identify the name information of data units, and further expands the scope of application of the method.

In some examples, sending the name matching information to the second electronic design tool may include: storing the name matching information about the first name information and the second name information in the name matching file; and sending the name matching file to the second electronic design tool. 2. Electronic design tools.

Specifically, when the name matching information is sent to the second electronic design tool, in order to ensure the safety and reliability of the name matching information transmission, the name matching information about the first name information and the second name information can be stored in a name matching file Then, the name matching file is sent to the second electronic design tool, thereby improving the stability and reliability of the method.

Figure 11 is a schematic structural diagram of a formal verification device provided by an embodiment of the present invention; referring to Figure 11, this embodiment provides a formal verification device that can perform the formal verification shown in Figure 5 above method. Specifically, the formal verification device may include:

The first memory 12 is used to store computer programs;

The first processor 11 is configured to run a computer program stored in the first memory 12 to implement:

Obtain the first file and the second file, and the second file is obtained from the first file;

Determining unit matching information corresponding to the first file and the second file, where the unit matching information includes the correspondence between the data units in the first file and the data units in the second file;

According to the unit matching information and the first file, the second file is formally verified.

The structure of the formal verification device may also include a first communication interface 13 for the electronic device to communicate with other devices or a communication network.

In some examples, the first processor 11 is further configured to: when the name information corresponding to at least one data unit in the second file cannot be identified, determine the unit matching information corresponding to the first file and the second file; In the first file, when the data unit corresponding to the name information of at least one data unit in the second file cannot be identified, the unit matching information corresponding to the first file and the second file is determined.

In some examples, the first file includes an integrated netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the integrated netlist.

In some examples, when the first processor 11 obtains the first file and the second file, the first processor 11 is configured to: obtain a comprehensive netlist corresponding to the chip design code, and the comprehensive netlist includes a register unit; The layout netlist is obtained based on the integrated netlist, and the name information of the register unit in the integrated netlist is different from the name information of the corresponding register unit in the layout netlist.

In some examples, the comprehensive netlist includes all the first register units and the first name information corresponding to the first register unit; the layout netlist includes all the second register units and the information corresponding to the second register unit. Second name information; the first register unit in the integrated netlist corresponds to the second register unit in the layout netlist.

In some examples, when the first processor 11 obtains the layout netlist based on the integrated netlist, the first processor 11 is configured to: use a preset tool to perform placement and routing processing on the integrated netlist to obtain the corresponding integrated netlist The layout netlist.

In some instances, the first processor 11 is also used to: detect whether the formal verification device and the preset tool belong to the same supplier; when the formal verification device and the preset tool belong to different suppliers, determine that the formal verification device cannot Identify the correspondence between the register units located in different files generated by the preset tool; or, when the formal verification device and the preset tool belong to the same supplier, it is determined that the formal verification device can identify the register unit.

In some examples, the first processor 11 is further configured to: after determining that the formal verification device can identify the register unit, use the formal verification device and the integrated netlist to perform formal verification on the layout netlist.

In some examples, when the first processor 11 determines the unit matching information corresponding to the first file and the second file, the first processor 11 is configured to: obtain the register unit based on the integrated netlist and the layout netlist According to the input corresponding relationship, obtain the unit matching information corresponding to the integrated netlist and the layout netlist.

In some examples, when the first processor 11 determines the unit matching information corresponding to the first file and the second file, the first processor 11 is configured to: obtain the register unit based on the integrated netlist and the layout netlist The input correspondence relationship and name correspondence relationship; according to the input correspondence relationship and the name correspondence relationship, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained.

The device shown in Fig. 11 can execute the methods of the embodiments shown in Figs. 5-8. For parts that are not described in detail in this embodiment, please refer to the relevant descriptions of the embodiments shown in Figs. 5-8. Refer to the description in the embodiment shown in FIG. 5 to FIG. 8 for the execution process and technical effect of this technical solution, and will not be repeated here.

FIG. 12 is a schematic structural diagram of an information recognition device provided by an embodiment of the present invention; referring to FIG. 12, this embodiment provides an information recognition device that can perform the information recognition shown in FIG. 9 above method. Specifically, the information identification device may include:

The second memory 22 is used to store computer programs;

The second processor 21 is configured to run a computer program stored in the second memory 22 to implement:

Acquiring a first file and a second file, the second file is obtained according to the first file, and the second file includes at least one data unit;

Determining unit matching information corresponding to the second file and the first file, where the unit matching information includes a correspondence between at least one data unit in the second file and a data unit in the first file;

Wherein, the structure of the information identification device may further include a second communication interface 23 for the electronic device to communicate with other devices or a communication network.

In some examples, the second processor 21 is configured to: when the name information corresponding to at least one data unit in the second file cannot be identified, determine the unit matching information corresponding to the first file and the second file; or When the data unit corresponding to the name information of at least one data unit in the second file cannot be identified in the first file, the unit matching information corresponding to the second file and the first file is determined.

In some examples, the first file includes at least one register unit, and the name information of the at least one register unit in the first file is different from the name information of the corresponding register unit in the second file; In the case of a file and a second file, the second processor 21 is configured to obtain the second file based on the first file.

In some examples, when the second processor 21 determines the unit matching information corresponding to the second file and the first file, the second processor 21 is configured to: obtain information about the register unit based on the first file and the second file The input correspondence relationship and the name correspondence relationship; the unit matching information corresponding to the first file and the second file is obtained according to the input correspondence relationship and the name correspondence relationship.

In some instances, when it is detected that the first electronic design automation tool changes at least one first data unit in the first file and generates at least one data unit stored in the second file, it is determined that at least one of the second files is The data unit corresponds to at least one first data unit in the first file.

In some examples, the first file, the second file, and the unit matching information are used for data processing of the second electronic design automation tool at the same time, including: the first file and the unit matching information are used for the second electronic design automation tool at the same time. 2. The formal verification process of documents.

In some examples, when the second processor 21 determines the unit matching information corresponding to the second file and the first file, the second processor 21 is configured to: obtain at least one piece of data based on the first file and the second file The input corresponding relationship of the unit; the unit matching information corresponding to the first file and the second file is obtained according to the input corresponding relationship.

The device shown in FIG. 12 can execute the method of the embodiment shown in FIG. 9. For parts that are not described in detail in this embodiment, reference may be made to the related description of the embodiment shown in FIG. 9. For the implementation process and technical effects of this technical solution, refer to the description in the embodiment shown in FIG. 9, which will not be repeated here.

FIG. 13 is a schematic structural diagram of a name information recognition device provided by an embodiment of the present invention; referring to FIG. 13, this embodiment provides a name information recognition device that can perform the name information recognition device shown in FIG. 10 The name information identification method. Specifically, the name information identification device may include:

The third memory 32 is used to store computer programs;

The third processor 31 is configured to run a computer program stored in the third memory 32 to implement:

Acquiring the first name information of the data unit;

When the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determine the name matching information corresponding to the first name information and the second name information;

Sending the name matching information to the second electronic design tool for the second electronic design tool to identify the correspondence between the first name information and the second name information; and

Wherein, the first name information of the data unit is stored in the first file, and the second name information of the data unit is stored in the second file, and the first electronic design tool and the second electronic design tool are different.

Wherein, the structure of the name information identification device may further include a third communication interface 33 for the electronic device to communicate with other devices or a communication network.

In some examples, when the third processor 31 sends the name matching information to the second electronic design tool, the third processor 31 is configured to: store the name matching information about the first name information and the second name information in The name matching file; and, sending the name matching file to the second electronic design tool.

In some examples, the name matching information includes first name information, second name information, and an index between the first name information and the second name information; or, the name matching information includes first name information, second name information, And the index between the second name information and the first name information.

In some instances, the second electronic design tool is used for formal verification of chip design.

In some instances, during the chip design process, the first file is generated before the second file.

In some examples, the first file and the second file are both files generated during the chip design process, and the first file is used to generate the second file.

The device shown in FIG. 13 can execute the method of the embodiment shown in FIG. 10. For parts that are not described in detail in this embodiment, reference may be made to the related description of the embodiment shown in FIG. 10. For the implementation process and technical effects of this technical solution, refer to the description in the embodiment shown in FIG. 10, which will not be repeated here.

In addition, an embodiment of the present invention provides a computer storage medium for storing computer software instructions used by an electronic device, which includes a program for executing the formal verification method in the method embodiment shown in FIGS. 5 to 8 above.

The embodiment of the present invention provides a computer storage medium for storing computer software instructions used by an electronic device, which includes a program for executing the information identification method in the method embodiment shown in FIG. 9.

The embodiment of the present invention provides a computer storage medium for storing computer software instructions used by an electronic device, which includes a program for executing the name information identification method in the method embodiment shown in FIG. 10.

The technical solutions and technical features in each of the above embodiments can be singly or combined in case of conflict with the present invention, as long as they do not exceed the cognitive scope of those skilled in the art, they all belong to the equivalent embodiments within the protection scope of this application. .

In the several embodiments provided by the present invention, it should be understood that the disclosed related devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be divided. It can be combined or integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present invention essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. , Including several instructions to make a computer processor (processor) execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage media include: U disk, mobile hard disk, Read-Only Memory (ROM), Random Access Memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes.

The above are only the embodiments of the present invention, which do not limit the scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the description and drawings of the present invention, or directly or indirectly applied to other related technologies In the same way, all fields are included in the scope of patent protection of the present invention.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention. range.

Claims

A formal verification method, characterized in that it includes:

Obtaining a first file and a second file, the second file being obtained according to the first file;

Determine unit matching information corresponding to the first file and the second file, where the unit matching information includes the correspondence between the data unit in the first file and the data unit in the second file relationship;

Perform formal verification on the second file according to the unit matching information and the first file.
The method of claim 1, wherein:

When the name information corresponding to at least one of the data units in the second file cannot be identified, determine the unit matching information corresponding to the first file and the second file;

When the data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, it is determined that the data unit corresponds to the first file and the second file. Corresponding unit matching information.
The method of claim 1, wherein:

The first file includes an integrated netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the integrated netlist.
The method according to claim 3, wherein obtaining the first file and the second file comprises:

Acquiring a comprehensive netlist corresponding to the chip design code, the comprehensive netlist including a register unit;

The layout netlist is obtained based on the integrated netlist, and the name information of the register unit in the integrated netlist is different from the name information of the corresponding register unit in the layout netlist.
The method of claim 4, wherein:

The comprehensive netlist includes all first register units and first name information corresponding to the first register units;

The layout netlist includes all second register units and second name information corresponding to the second register units;

The first register unit in the integrated netlist corresponds to the second register unit in the layout netlist.
The method according to claim 4, wherein obtaining the layout netlist based on the comprehensive netlist comprises:

Use a preset tool to perform placement and routing processing on the integrated netlist to obtain a layout netlist corresponding to the integrated netlist.
The method according to claim 6, wherein the method is applied to a formal verification device, and the method further comprises:

Detecting whether the formal verification device and the preset tool belong to the same supplier;

When the formal verification device and the preset tool belong to different suppliers, it is determined that the formal verification device cannot recognize the correspondence between the register units located in different files generated by the preset tool. ;or,

When the formal verification device and the preset tool belong to the same supplier, it is determined that the formal verification device can identify the register unit.
The method according to claim 7, wherein after determining that the formal verification device can identify the register unit, the method further comprises:

Using the formal verification device and the comprehensive netlist, formal verification is performed on the layout netlist.
The method according to any one of claims 4-8, wherein the determining unit matching information corresponding to the first file and the second file comprises:

Based on the comprehensive netlist and the layout netlist, acquiring the input correspondence for the register unit;

According to the input correspondence, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained.
The method according to any one of claims 4-8, wherein the determining unit matching information corresponding to the first file and the second file comprises:

Based on the comprehensive netlist and the layout netlist, obtaining the input correspondence and the name correspondence for the register unit;

According to the input correspondence and the name correspondence, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained.
An information recognition method, characterized in that it comprises:

Acquiring a first file and a second file, where the second file is obtained based on the first file, and the second file includes at least one data unit;

Determine unit matching information corresponding to the second file and the first file, where the unit matching information includes the at least one data unit in the second file and the data unit in the first file Correspondence between;

The unit matching information is used to identify the data unit in the second file.
The method of claim 11, wherein:

When the name information corresponding to at least one of the data units in the second file cannot be identified, determine the unit matching information corresponding to the first file and the second file; or,

When the data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, it is determined that the data unit corresponds to the second file and the first file. Corresponding unit matching information.
The method of claim 11, wherein:

The first file includes a comprehensive netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the comprehensive netlist; or

The first file includes a source program file, and the second file includes a comprehensive netlist corresponding to the chip design code; or

The first file includes a comprehensive netlist corresponding to the chip design code, and the second file includes a netlist generated after logic testing; or

The first file includes a netlist generated after logic testing, and the second file includes a layout netlist.
The method according to claim 11, wherein the first file includes at least one register unit, and the name information of the at least one register unit in the first file corresponds to the register in the second file The name information of the unit is different; and

The obtaining of the first file and the second file includes:

The second file is obtained based on the first file.
The method according to claim 14, wherein the determining unit matching information corresponding to the second file and the first file comprises:

Obtaining input correspondence and name correspondence for the register unit based on the first file and the second file;

Acquire unit matching information corresponding to the first file and the second file according to the input correspondence and the name correspondence.
The method of claim 11, wherein:

The second file is obtained by processing the first file by a first electronic design automation tool; the first file, the second file, and the unit matching information are simultaneously used for the second electronic design automation Data processing of the tool, wherein the first electronic design automation tool and the second electronic design automation tool are different.
The method of claim 16, wherein:

When it is detected that the first electronic design automation tool changes at least one first data unit in the first file and generates the at least one data unit stored in the second file, determine the second The at least one data unit in the file corresponds to the at least one first data unit in the first file.
The method of claim 17, wherein:

The first file, the second file, and the unit matching information are simultaneously used for data processing of a second electronic design automation tool, including:

The first file and the unit matching information are simultaneously used in the formal verification process of the second file by the second electronic design automation tool.
The method according to any one of claims 14-18, wherein determining unit matching information corresponding to the second file and the first file comprises:

Acquiring the input correspondence of the at least one data unit based on the first file and the second file;

Acquire unit matching information corresponding to the first file and the second file according to the input correspondence relationship.
A method for identifying name information, which is characterized in that it includes:

Acquiring the first name information of the data unit;

When the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determine the name corresponding to the first name information and the second name information Matching information

Sending the name matching information to a second electronic design tool for the second electronic design tool to identify the correspondence between the first name information and the second name information; and

Wherein, the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different .
22. The method of claim 20, wherein sending the name matching information to a second electronic design tool comprises:

Storing name matching information about the first name information and the second name information in a name matching file; and

Sending the name matching file to the second electronic design tool.
The method of claim 20, wherein:

The name matching information includes the first name information, the second name information, and an index between the first name information and the second name information; or

The name matching information includes the first name information, second name information, and an index from the second name information to the first name information.
The method of claim 20, wherein:

The second electronic design tool is used for formal verification of chip design.
The method of claim 20, wherein:

In the chip design process, the first file is generated before the second file.
The method of claim 20, wherein:

Both the first file and the second file are files generated during the chip design process, and the first file is used to generate the second file.
A formal verification device, characterized in that it comprises:

The first memory is used to store computer programs;

The first processor is configured to run a computer program stored in the first memory to implement:

Obtaining a first file and a second file, the second file being obtained according to the first file;

Determine unit matching information corresponding to the first file and the second file, where the unit matching information includes the correspondence between the data unit in the first file and the data unit in the second file relationship;

Perform formal verification on the second file according to the unit matching information and the first file.
The device according to claim 26, wherein the first processor is further configured to:

When the name information corresponding to at least one of the data units in the second file cannot be identified, determine the unit matching information corresponding to the first file and the second file;

When the data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, it is determined that the data unit corresponds to the first file and the second file. Corresponding unit matching information.
The device of claim 26, wherein:

The first file includes an integrated netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the integrated netlist.
The device according to claim 28, wherein when the first processor obtains the first file and the second file, the first processor is configured to:

Acquiring a comprehensive netlist corresponding to the chip design code, the comprehensive netlist including a register unit;

The layout netlist is obtained based on the integrated netlist, and the name information of the register unit in the integrated netlist is different from the name information of the corresponding register unit in the layout netlist.
The device of claim 29, wherein:

The comprehensive netlist includes all first register units and first name information corresponding to the first register units;

The layout netlist includes all second register units and second name information corresponding to the second register units;

The first register unit in the integrated netlist corresponds to the second register unit in the layout netlist.
The device according to claim 29, wherein when the first processor obtains the layout netlist based on the integrated netlist, the first processor is configured to:

Use a preset tool to perform placement and routing processing on the integrated netlist to obtain a layout netlist corresponding to the integrated netlist.
The device according to claim 31, wherein the first processor is further configured to:

Detecting whether the formal verification device and the preset tool belong to the same supplier;

When the formal verification device and the preset tool belong to different suppliers, it is determined that the formal verification device cannot identify the register unit; or,

When the formal verification device and the preset tool belong to the same supplier, it is determined that the formal verification device can identify the register unit.
The device according to claim 32, wherein the first processor is further configured to:

After it is determined that the formal verification device can identify the register unit, the formal verification device and the integrated netlist are used to perform formal verification on the layout netlist.
The device according to any one of claims 29-33, wherein when the first processor determines the unit matching information corresponding to the first file and the second file, the first A processor for:

Based on the comprehensive netlist and the layout netlist, acquiring the input correspondence for the register unit;

According to the input correspondence, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained.
The device according to any one of claims 29-33, wherein when the first processor determines the unit matching information corresponding to the first file and the second file, the first A processor for:

Based on the comprehensive netlist and the layout netlist, obtaining the input correspondence and the name correspondence for the register unit;

According to the input correspondence and the name correspondence, the unit matching information corresponding to the integrated netlist and the layout netlist is obtained.
An information recognition device, characterized in that it comprises:

The second memory is used to store computer programs;

The second processor is configured to run a computer program stored in the second memory to implement:

Acquiring a first file and a second file, where the second file is obtained based on the first file, and the second file includes at least one data unit;

Determine unit matching information corresponding to the second file and the first file, where the unit matching information includes the at least one data unit in the second file and the data unit in the first file Correspondence between;

The unit matching information is used to identify the data unit in the second file.
The device according to claim 36, wherein the second processor is configured to:

When the name information corresponding to at least one of the data units in the second file cannot be identified, determine the unit matching information corresponding to the first file and the second file; or,

When the data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, it is determined that the data unit corresponds to the second file and the first file. Corresponding unit matching information.
The device of claim 36, wherein:

The first file includes a comprehensive netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the comprehensive netlist; or,

The first file includes a source program file, and the second file includes a comprehensive netlist corresponding to the chip design code; or,

The first file includes a comprehensive netlist corresponding to the chip design code, and the second file includes a netlist generated after logic testing; or,

The first file includes a netlist generated after logic testing, and the second file includes a layout netlist.
The device according to claim 36, wherein the first file includes at least one register unit, and the name information of the at least one register unit in the first file corresponds to the register in the second file The name information of the unit is different; and

When the second processor obtains the first file and the second file, the second processor is configured to:

The second file is obtained based on the first file.
The device according to claim 39, wherein when the second processor determines the unit matching information corresponding to the second file and the first file, the second processor is configured to :

Obtaining input correspondence and name correspondence for the register unit based on the first file and the second file;

Acquire unit matching information corresponding to the first file and the second file according to the input correspondence and the name correspondence.
The device of claim 36, wherein:

The second file is obtained by processing the first file by a first electronic design automation tool; the first file, the second file, and the unit matching information are simultaneously used in the second electronic design automation Data processing of the tool, wherein the first electronic design automation tool and the second electronic design automation tool are different.
The device of claim 41, wherein:

When it is detected that the first electronic design automation tool changes at least one first data unit in the first file and generates the at least one data unit stored in the second file, determine the second The at least one data unit in the file corresponds to the at least one first data unit in the first file.
The device of claim 42, wherein:

The first file, the second file, and the unit matching information are used for data processing of a second electronic design automation tool at the same time, including:

The first file and the unit matching information are simultaneously used in the formal verification process of the second file by the second electronic design automation tool.
The device according to any one of claims 39-43, wherein when the second processor determines the unit matching information corresponding to the second file and the first file, the first file Two processors for:

Acquiring the input correspondence of the at least one data unit based on the first file and the second file;

Acquire unit matching information corresponding to the first file and the second file according to the input correspondence relationship.
A name information recognition device, which is characterized in that it comprises:

The third storage is used to store computer programs;

The third processor is configured to run the computer program stored in the third memory to implement:

Acquiring the first name information of the data unit;

When the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determine the name corresponding to the first name information and the second name information Matching information

Sending the name matching information to a second electronic design tool for the second electronic design tool to identify the correspondence between the first name information and the second name information; and

Wherein, the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different .
The device according to claim 45, wherein when the third processor sends the name matching information to the second electronic design tool, the third processor is configured to:

Storing name matching information about the first name information and the second name information in a name matching file; and

Sending the name matching file to the second electronic design tool.
The device of claim 45, wherein:

The name matching information includes the first name information, the second name information, and an index between the first name information and the second name information; or,

The name matching information includes the first name information, second name information, and an index from the second name information to the first name information.
The device of claim 45, wherein:

The second electronic design tool is used for formal verification of chip design.
The device of claim 45, wherein:

In the chip design process, the first file is generated before the second file.
The device of claim 45, wherein:

Both the first file and the second file are files generated during the chip design process, and the first file is used to generate the second file.
A computer-readable storage medium, wherein the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used to implement any one of claims 1-10 The formal verification method described in the item.
A computer-readable storage medium, wherein the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used to implement any one of claims 11-19 The information identification method described in the item.
A computer-readable storage medium, wherein the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used to implement any one of claims 20-25 The name information identification method described in the item.