CN105740487A - Method for verifying consistency between layout and schematic on basis of process design kit - Google Patents
Method for verifying consistency between layout and schematic on basis of process design kit Download PDFInfo
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- CN105740487A CN105740487A CN201410752111.8A CN201410752111A CN105740487A CN 105740487 A CN105740487 A CN 105740487A CN 201410752111 A CN201410752111 A CN 201410752111A CN 105740487 A CN105740487 A CN 105740487A
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Abstract
The invention discloses a method for verifying the consistency between a layout and a schematic on the basis of a process design kit. According to the method, device serial numbers are automatically added to the port names of parameterized devices in a QA library through adopting an automatic process, so that the uniqueness of all the port names in the QA library is achieved so as to achieve the requirement of LVS QA, the generation time of an LVS QA library is decreased, more comprehensive LVS QA is obtained and the human cost is saved; and the method can be applied to all the technology nodes at present, and is wide in application.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of domain based on Process design kit and schematic diagram consistency verification method.
Background technology
Process design kit (ProcessDesignKit, it is called for short PDK) it is the data-linkage platform connecting chip design and chip manufacturing, along with IC design is increasingly sophisticated, development technology design packet also sets up checking reference flowchart for reducing the design cost of costliness and evading the market risk very easily produced and be necessary.Domain and schematic diagram consistency checking (LayoutVersusSchematic, it is called for short LVS) it is one of the emphasis assembly of Process design kit, it is customized development according to technique information requirement, and purposes is in that whether the domain helping Chevron Research Company's checking designed is consistent with schematic diagram netlist.
nullAt present，Manufacture the advanced device meeting design requirement in a large number，Substantial amounts of QA storehouse (QualityAssurancepattern) is needed [to include principle graphical diagram (schematicsymbol)、Parameterized device domain (Pcelllayout)、Port-mark text] remove comprehensive LVSQA，To be quickly carried out next flow process，And under advanced technology node，Along with quantity and the composition of device become to become increasingly complex，Thousands of domain has needed LVSQA，Adopt existing sample test storehouse (Sampletestpattern)，Owing to needing to spend the more substantial amounts of device interface of time series analysis，So that the port that can interconnect is connected together，And one by one plus corresponding device interface title，And then be difficult to carry out next flow process on time，This is just badly in need of wanting the automatic mode of a kind of optimization to complete LVSQA.
Summary of the invention
For above-mentioned Problems existing, a kind of domain based on Process design kit of disclosure and schematic diagram consistency verification method, to overcome the substantial amounts of device interface of time series analysis needing cost more in prior art, the port that can interconnect is connected together, and one by one plus corresponding device interface title, the problem that can be only achieved LVSQA demand.
To achieve these goals, the application describes a kind of domain based on Process design kit and schematic diagram consistency verification method, wherein, comprises the steps:
Process design kit is provided, and generates multiple QA schematic libraries comprising parameterized device principle graphical diagram according to this Process design kit；
Obtain each schematic diagram port absolute coordinate in described QA schematic library in described parameterized device principle graphical diagram, and according to this absolute coordinate, each schematic diagram port in described QA schematic library arranges corresponding mark；
The QA domain storehouse comprising parameterized device domain is generated according to described QA schematic library；
Obtain each domain port absolute coordinate in described QA domain storehouse in described parameterized device domain, and according to this absolute coordinate, each domain port in described QA domain storehouse arranges corresponding label；
Wherein, each described mark is all unique in described QA schematic library, and each described label is also all unique in described QA domain storehouse.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described method also includes: obtain the device class name in described Process design kit, and according to this device class name, all of parameterized device is classified, to generate multiple QA schematic library comprising parameterized device principle graphical diagram.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, be sequentially generated the plurality of QA schematic library comprising parameterized device principle graphical diagram according to described device class name.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described method also includes:
Extract the mark of the relative coordinate values of each schematic diagram port and this schematic diagram port in described parameterized device principle graphical diagram, and according to this parameterized device principle graphical diagram relative coordinate values in QA schematic library, obtain each schematic diagram port absolute coordinate in described QA schematic library in described parameterized device principle graphical diagram.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described mark includes the title of described schematic diagram port and the device serial number of the parameterized device at this schematic diagram port place.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described method also includes: after utilizing described QA schematic library to produce the QA domain storehouse comprising parameterized device domain, described QA domain storehouse is grouped by the mode of operation of device classification, so that described QA domain storehouse meets the demand of LVS inspection.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described method also includes:
Extract the label of the relative coordinate values of each domain port and this domain port in described parameterized device domain, and according to this parameterized device domain relative coordinate values in described QA domain storehouse, obtain each domain port absolute coordinate in described QA domain storehouse in described parameterized device domain.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described label includes the title of described domain port and the device serial number of the parameterized device at this domain port place.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described method also includes: what judge label in described QA domain storehouse and described QA schematic library identifies whether consistent, and generates a QA storehouse according to above-mentioned judged result.
The above-mentioned domain based on Process design kit and schematic diagram consistency verification method, wherein, described QA storehouse comprises and all records the report file of diversity information between described QA domain storehouse and described QA schematic library.
Foregoing invention has the advantage that or beneficial effect:
Domain based on Process design kit disclosed by the invention and schematic diagram consistency verification method, by adopting automatic flow to make the port title of the parameterized device in QA storehouse automatically add device serial number, thus having reached all of the port title uniqueness in QA storehouse, to reach the requirement of LVSQA, not only reduce the generation time in LVSQA storehouse, it is thus achieved that more fully LVSQA, and save human cost, and current all of technology node can be applicable to, it is widely used.
Concrete accompanying drawing explanation
By reading detailed description non-limiting example made with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.The part that labelling instruction identical in whole accompanying drawings is identical.Can not be drawn to scale accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is that background of invention middle port uses the interconnective schematic diagram of physical cord；
Fig. 2 does not use the interconnective schematic diagram of physical cord between embodiment of the present invention middle port；
Fig. 3 is the schematic flow sheet of the embodiment of the present invention domain based on Process design kit and schematic diagram consistency verification method；
Fig. 4 is present invention effect schematic diagram compared with background technology.
Detailed description of the invention
The invention discloses the method for domain involved by Autocad instrument and schematic diagram consistency checking in integrated circuit, below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
In the present invention, same nationality is expressed comparatively intuitively the function information of circuit by circuit theory diagrams, need the circuit received describes information or the next automatic generative circuit schematic diagram of data (such as circuit meshwork list file), thereby through the parameterized device in circuit and port thereof being positioned layout and annexation carries out self routing or illusory wiring (connecting without physical cord), it is achieved the circuit theory diagrams of tool anticipation circuit functional character export accurately.Finally use such as eda tool to run LVS verification Fileview domain whether consistent with device parameters with the port of schematic diagram device, and then verify whether LVS file is write correct.
Fig. 3 is the schematic flow sheet of the embodiment of the present invention domain based on Process design kit and schematic diagram consistency verification method, as shown in Figure 3:
The present embodiment relates to a kind of domain based on Process design kit and schematic diagram consistency verification method, comprises the steps:
Step S1: Process design kit is provided, obtain the device class name in this Process design kit, and according to this device class name, all of parameterized device is classified, to be sequentially generated multiple QA schematic library comprising parameterized device principle graphical diagram according to device class name；Above-mentioned parameter device principle graphical diagram and the parameterized device form of expression in QA schematic library, actually still refer to parameterized device；In an embodiment of the present invention, this device class name refers to that such as (resistor starts name using as identification using R_ as key word, capacitor starts name using as identification using C_ as key word, common metal-oxide-semiconductor starts name using as identification using M_ as key word, etc.) etc the title of a class device.
Generally, the to be fetched netlist data of schematic diagram that domain device is corresponding or information (such as metal-oxide-semiconductor name: M_ model _ wide length _ port leakage _ port source _ port grid _ port backing has been reflected completely based on the unit title of device in the parameter rule unbound document for defined parameters device of input, the data being transfused to GDS are recorded as: M_N_W8L1_D_S_G_B (GND)), design tool can generate, for each unit, the subdirectory named with unit name automatically, and range site name information generates the schematic diagram netlist that domain device is corresponding under subdirectory, i.e. QA schematic library.
Step S2: extract non-line in above-mentioned parameter device principle graphical diagram or treat the relative coordinate values of each schematic diagram port of line and the mark (pinlabel) of this schematic diagram port, further according to this parameterized device principle graphical diagram relative coordinate values in QA schematic library, converse above-mentioned schematic diagram port absolute coordinate in QA schematic library；This is critically important for the position confirming schematic diagram port, if circuit drawing is divided into grid with certain pixel rule, then parameterized device can be placed by grid lines.Each parameterized device is substantially rendered as rectangular patterns when circuit design, border is provided with a number of indefinite port or pin, characterization parameter component graphics size and position can be taken by the position in such as its some corner to determine coordinate, consequently, it is possible to the position that certain parameterized device is on circuit theory diagrams (QA schematic library) just can be determined.It is readily appreciated that, according to parameterized device relative coordinate values in QA schematic library, just can converse each schematic diagram port absolute coordinate in QA schematic library in above-mentioned parameter device principle graphical diagram, and then obtain the absolute coordinate in QA schematic library of each schematic diagram port in above-mentioned parameter device principle graphical diagram.
Wherein, above-mentioned mark includes the title of schematic diagram port and the device serial number of the parameterized device at this schematic diagram port place.
In an embodiment of the present invention, above-mentioned QA schematic library has between the schematic diagram port of same names need not interconnect by physical cord.
nullStep S3，Adopt eda software (such as cadence、Workview etc.) program module that provides，According to each schematic diagram port learned in above-mentioned steps S2 absolute coordinate in QA schematic library，Each schematic diagram port in QA schematic library arranges corresponding mark (pinlabeladd)，Namely each schematic diagram port in QA schematic library adds the title of this schematic diagram port and the device serial number of the parameterized device at this schematic diagram port place，In this process，Device serial number due to the parameterized device at the title of schematic diagram port this schematic diagram port place by automatic filling，Thus reaching the title of this schematic diagram port uniqueness in QA schematic library，Namely uniquely (that is each mark is all at QA schematic library，Mark on each port is set and all in QA schematic library, this port can be different from other ports).
Step S4, design tool adopts and drives, with schematic diagram, the function generating domain, namely the QA domain storehouse comprising parameterized device domain is automatically generated according to QA schematic library, in an embodiment of the present invention, above-mentioned parameter element layout and the parameterized device form of expression in QA domain storehouse, actually still refer to parameterized device.
This QA domain storehouse generally also can be grouped with the mode of operation of device classification, makes the domain of device meet the demand of LVS inspection.
Step S5, extract non-line in above-mentioned parameter element layout or treat the label (pintext) of relative coordinate values and this domain port of each domain port of line, further according to this parameterized device domain relative coordinate values in QA domain storehouse, converse the absolute coordinate in QA domain storehouse of the domain port in above-mentioned parameter element layout, and then obtain the absolute coordinate in QA domain storehouse of each domain port in above-mentioned parameter element layout.
Wherein, above-mentioned label includes the title of domain port and the device serial number of the parameterized device at this domain port place.
Additionally, in an embodiment of the present invention, having between the domain port of same names in above-mentioned QA domain storehouse need not interconnect by physical cord.
nullStep S6，Adopt eda software (such as cadence、Workview etc.) program module that provides，According to each domain port learned in above-mentioned steps S5 absolute coordinate in QA domain storehouse，Each domain port in QA domain storehouse arranges corresponding mark (pinlabeladd)，Namely each domain port in QA domain storehouse adds the title of this domain port and the device serial number of the parameterized device at this domain port place，In this process，Device serial number due to the parameterized device at the title of domain port this domain port place by automatic filling，Thus reaching the title of this domain port uniqueness in QA domain storehouse，Namely uniquely (that is each label is all in QA domain storehouse，Label on each port is set and all in QA domain storehouse, this port can be different from other ports).
Step S7, judge that label in QA domain storehouse is consistent with identifying whether in QA schematic library, and generate a QA storehouse according to above-mentioned judged result, complete the structure in LVSQA storehouse, wherein, this QA storehouse comprises and all records the report file of diversity information between QA domain storehouse and QA schematic library.
In an embodiment of the present invention, PDK instrument utilizes the automatic calling technological rule file of script to carry out LVS consistency check, implement to automatically analyze to the comparative result run, provide analysis destination file, according to present invention spirit, user side passes through interpretation of result file, it should be apparent that learn that whether the electricity rule file needing to verify of LVS is correct, learn result with less manpower with in the shorter time limit, if the electricity rule file of exploitation is wrong, at once can revise and perform iteration checking.Furthermore according to present invention spirit, the title of domain port all device serial number by automatic filling in the title of the schematic diagram port in QA schematic library or QA domain storehouse, thus having reached the title of all schematic diagram ports title at QA schematic library and all domain ports uniqueness in QA domain storehouse, identification process is simplified, therefore this port can be substantially that void is broken or floating mode is arranged, specifically, layout result corresponding to the parameterized device on grid lines, go between parameterized device with the passage between row or column with row without arranging or distributing the physical connection of any reality to couple some ports.
Fig. 1 is that background of invention middle port uses the interconnective schematic diagram of physical cord；Fig. 2 does not use the interconnective schematic diagram of physical cord between embodiment of the present invention middle port；Shown in Fig. 1 and Fig. 2:
In an embodiment of the present invention, without above-mentioned automatic flow, because the same port title in same QA storehouse necessarily needs to interconnect (as shown in Figure 1) with physical cord, person skilled needs first to analyze thousands of device interface, the port that can interconnect is connected together, and one by one plus corresponding device interface title, can be only achieved the requirement of LVSQA, the present invention does not then need (as shown in Figure 2).
It addition, in an embodiment of the present invention, the partial information in the PolySiOnLVSQA storehouse of 28nm is as shown in the table:
In addition, Fig. 4 is present invention effect schematic diagram compared with background technology, as shown in Figure 4, 1 is adopt the method for the present invention and adopt the method for background technology to complete LVSQA contrast schematic diagram of (Resource) in resource, 2 is adopt the method for the present invention and adopt the method for background technology to complete LVSQA contrast schematic diagram in time, 3 is adopt the method for the present invention and adopt the method for background technology to complete LVSQA contrast schematic diagram of (Accuracy) in degree of accuracy, wherein, it is not filled by the schematic diagram that square is background technology of shade, it is filled with the schematic diagram that square is the present invention of shade, as shown in Figure 4, the method of the present invention is while decreasing resource and time, also improve the degree of accuracy of LVSQA.
From above-described embodiment, automatic flow provided by the invention is greatly accelerated the flow process of QA, schematic diagram port/domain port the title making the parameterized device in QA storehouse adds device serial number automatically, thus having reached all schematic diagrams port/domain port title uniqueness in QA storehouse, and meet the requirement of LVSQA, and then decreasing the generation time in LVSQA storehouse while, obtain more fully LVSQA, and saved human cost, and current all of technology node can be applicable to, it is widely used.
It should be appreciated by those skilled in the art that those skilled in the art are realizing described change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case has no effect on the flesh and blood of the present invention, does not repeat them here.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned particular implementation, the equipment and the structure that are not wherein described in detail to the greatest extent are construed as and are practiced with the common mode in this area；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or it being revised as the Equivalent embodiments of equivalent variations, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (10)
1. the domain based on Process design kit and schematic diagram consistency verification method, it is characterised in that comprise the steps:
Process design kit is provided, and generates multiple QA schematic libraries comprising parameterized device principle graphical diagram according to this Process design kit；
Obtain each schematic diagram port absolute coordinate in described QA schematic library in described parameterized device principle graphical diagram, and according to this absolute coordinate, each schematic diagram port in described QA schematic library arranges corresponding mark；
The QA domain storehouse comprising parameterized device domain is generated according to described QA schematic library；
Obtain each domain port absolute coordinate in described QA domain storehouse in described parameterized device domain, and according to this absolute coordinate, each domain port in described QA domain storehouse arranges corresponding label；
Wherein, each described mark is all unique in described QA schematic library, and each described label is also all unique in described QA domain storehouse.
2. the domain based on Process design kit as claimed in claim 1 and schematic diagram consistency verification method, it is characterized in that, described method also includes: obtain the device class name in described Process design kit, and according to this device class name, all of parameterized device is classified, to generate multiple QA schematic library comprising parameterized device principle graphical diagram.
3. the domain based on Process design kit as claimed in claim 2 and schematic diagram consistency verification method, it is characterised in that be sequentially generated the plurality of QA schematic library comprising parameterized device principle graphical diagram according to described device class name.
4. the domain based on Process design kit as claimed in claim 1 and schematic diagram consistency verification method, it is characterised in that described method also includes:
Extract the mark of the relative coordinate values of each schematic diagram port and this schematic diagram port in described parameterized device principle graphical diagram, and according to this parameterized device principle graphical diagram relative coordinate values in QA schematic library, obtain each schematic diagram port absolute coordinate in described QA schematic library in described parameterized device principle graphical diagram.
5. the domain based on Process design kit as claimed in claim 4 and schematic diagram consistency verification method, it is characterised in that described mark includes the title of described schematic diagram port and the device serial number of the parameterized device at this schematic diagram port place.
6. the domain based on Process design kit as claimed in claim 1 and schematic diagram consistency verification method, it is characterized in that, described method also includes: after utilizing described QA schematic library to produce the QA domain storehouse comprising parameterized device domain, described QA domain storehouse is grouped by the mode of operation of device classification, so that described QA domain storehouse meets the demand of LVS inspection.
7. the domain based on Process design kit as claimed in claim 1 and schematic diagram consistency verification method, it is characterised in that described method also includes:
Extract the label of the relative coordinate values of each domain port and this domain port in described parameterized device domain, and according to this parameterized device domain relative coordinate values in described QA domain storehouse, obtain each domain port absolute coordinate in described QA domain storehouse in described parameterized device domain.
8. the domain based on Process design kit as claimed in claim 7 and schematic diagram consistency verification method, it is characterised in that described label includes the title of described domain port and the device serial number of the parameterized device at this domain port place.
9. the domain based on Process design kit as claimed in claim 1 and schematic diagram consistency verification method, it is characterized in that, described method also includes: judges that label in described QA domain storehouse is consistent with identifying whether in described QA schematic library, and generates a QA storehouse according to above-mentioned judged result.
10. the domain based on Process design kit as claimed in claim 1 and schematic diagram consistency verification method, it is characterised in that described QA storehouse comprises and all records the report file of diversity information between described QA domain storehouse and described QA schematic library.
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