CN114297739A - Identification processing method and device for layout verification, server and storage medium - Google Patents
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Abstract
The disclosure provides an identification processing method, an identification processing device, a server and a storage medium for layout verification, which can identify position information of a target layout graph in an input instruction after the input instruction received by a system end is acquired; after the identification name of the target layout graph is determined, determining the posture information of the identification of the target layout graph according to the input parameters received by the system end; and indexing the position information of the target layout graph, and placing the graph identifier of the target layout graph at the corresponding position of the target layout graph, so that a designer is helped to quickly and accurately establish and extract the connection relation between graphs in any module of the integrated circuit layout in the subsequent verification process, quickly position problems and modify the layout, and the working efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of computer aided design of integrated circuits, and in particular, to an identifier processing method, device, server and storage medium for layout verification in semiconductor integrated circuit design.
Background
An Integrated Circuit (IC) board diagram is an intermediate link between a Circuit system and an IC process, and is an essential important link. The layout design is a physical realization link and is also an important conversion from a symbolized circuit diagram to an actual physical layer, a three-dimensional circuit system can be changed into a two-dimensional plane diagram through the integrated circuit layout design, and the two-dimensional plane diagram is reduced into a three-dimensional structure based on silicon materials through process processing.
In the process of designing the integrated circuit layout, a plurality of labels (Label) are usually added, the Label is an information Label of different layers at different positions, and in the process of drawing the layout, the Label needs to be continuously created according to the Label designed by a schematic diagram, the real-time information of the drawing layout and the design habit of an engineer for identification. The Label can be composed of any English character and number and some basic symbols, the length of the Label is not limited in theory, but the Label is usually identified by the least characters because the layout of the chip is very complicated and is very small in size. The connection relationship of the circuit can be marked by establishing the connection relationship between the marks and the patterns, different electric potentials can be marked, and the marks can be used for checking whether the connection relationship of the circuit is correct or not and also can be used for checking whether the problem of open circuit or short circuit exists in the circuit or not. With the continuous development of integrated circuit technology, the scale of layout data is continuously increased, and the connection relationship is more and more complex. In a hierarchical layout, it is increasingly important to quickly establish a connection relationship between a tag and a graph. In the prior art, if the connection relation between units between two modules in a layout is required to be known, manual operation is required to be carried out on each line, and if the statistics is carried out on one line by one line, the efficiency is low; if the statistics are performed on a group of lines, uncertain results such as sequence errors may occur. And after the statistics is finished, manual inspection is needed, so that the efficiency is low, and the error rate is high.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides an identifier processing method, an identifier processing apparatus, a server, and a storage medium for layout verification.
In one aspect, the present disclosure provides an identifier processing method for layout verification, including:
acquiring an input instruction received by a system end, and identifying the position information of a target layout graph in the input instruction;
determining the identification name of the target layout graph, and determining the posture information of the identification of the target layout graph according to the input parameters received by the system end; and
and indexing the position information of the target layout graph, and placing a graph identifier of the target layout graph at a corresponding position.
Preferably, the position information of the target layout pattern includes: the position of the layer where the target layout graph is located, and the detailed area of the target layout graph distributed in the layer.
Preferably, the gesture information of the aforementioned graphic marker includes: the font, size and shape of the graphic identifier, and the area positions of the graphic identifier distributed in the target layout graphic.
Preferably, the step of indexing the position information of the target layout pattern and placing the pattern identifier of the target layout pattern at the corresponding position thereof includes:
indexing the position information of the target layout graph, and determining a placing area of a graph identifier in the target layout graph according to the input parameters; and
and when the placing area exceeds the effective area of the target layout graph, performing rotation, translation and/or mirror image operation on the graph identifier until the placing area is positioned in the effective area of the target layout graph.
Preferably, the identification name of the target layout pattern is used for representing the electrical performance of the target layout pattern in the whole circuit.
On the other hand, the present disclosure also provides an identifier processing apparatus for layout verification, which includes:
the first input module is used for acquiring an input instruction received by the system end;
the second input module is used for acquiring input parameters received by the system end;
and the identification processing module is respectively in communication connection with the first input module and the second input module and is used for identifying the position information of the target layout graph in the input instruction, determining the identification name of the target layout graph, indexing the position information of the target layout graph and placing the graph identification of the target layout graph at the corresponding position.
Preferably, the aforementioned tag processing module comprises a microprocessor for:
and determining a placing region of the graph identifier in the target layout graph according to the input parameters, and when the placing region exceeds the effective region of the target layout graph, performing rotation, translation and/or mirroring operation on the graph identifier by algorithm planning and control until the placing region is positioned in the effective region of the layout graph.
Preferably, the aforementioned tag processing module comprises a microprocessor for:
and determining a placing region of the graph identifier in the target layout graph according to the input parameters, and executing rotation, translation and/or mirror image operation on the graph identifier according to the input instruction when the placing region exceeds the effective region of the target layout graph.
In another aspect, the present disclosure further provides a server, including:
a processor;
a memory for storing one or more programs;
wherein, when the aforementioned one or more programs are executed by the aforementioned processor, the aforementioned processor implements the aforementioned identification processing method for layout verification.
In yet another aspect, the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, wherein the program, when executed by a processor, implements the identification processing method for layout verification as described above.
The beneficial effects of this disclosure are: the identification processing method, the identification processing device, the server and the storage medium for verifying the layout can identify the position information of a target layout graph in an input instruction after the input instruction received by a system end is acquired; after the identification name of the target layout graph is determined, determining the posture information of the identification of the target layout graph according to the input parameters received by the system end; and indexing the position information of the target layout graph, and placing the graph identifier of the target layout graph at the corresponding position of the target layout graph, so that a designer is helped to quickly and accurately establish and extract the connection relation between graphs in any module of the integrated circuit layout in the subsequent verification process, quickly position problems and modify the layout, and the working efficiency is improved.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic flowchart illustrating an identification processing method for layout verification according to an embodiment of the present disclosure;
fig. 2 is a schematic block diagram illustrating a structure of an identifier processing apparatus for layout verification according to a second embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a parameter setting interface identified in the identification processing device shown in FIG. 2;
FIGS. 4a to 4c are schematic diagrams of models of the identifier processing apparatus shown in FIG. 2 in different application scenarios, respectively;
fig. 5 shows a schematic structural diagram of a server provided in the third embodiment of the present disclosure.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
With the development of integrated circuit technology, the feature size of a chip is smaller and smaller, the integration level of a single chip is continuously improved, the structure and the process are increasingly complex, and the scale of a layout database is multiplied. With the expansion of layout scale, design rules required to be verified at various stages of integrated circuit design are increasing. Design Rule Check (DRC) of an integrated circuit Layout and consistency Check (LVS) of the integrated circuit Layout and a schematic diagram become more and more important, and they play an important role in reducing Design errors, Design cost and risk of Design failure. In the design of a very large scale integrated circuit, the layout scale expands sharply, and how to quickly locate the problem in the layout becomes another challenge in the design of the integrated circuit.
In the process of IC (integrated circuit) design or FPD (flat panel display) design, layout design is a physical implementation link and is also an important transition from a symbolic circuit diagram to an actual physical layer. With the continuous improvement of the manufacturing process, the complexity of the process is multiplied, the number of metal layers is increased more and more, and the area of a chip is reduced more and more in order to improve the integration rate and reduce the power consumption, so that the layout design is more and more challenging. How to find the port of a certain device in a huge layout or mark the meaning represented by any one wire is a good news for solving the problems by creating a Label (identification). It is an essential tool for layout designers to create various labels in the process of drawing the layout.
If a layout designer wants to place a Label containing several characters on a narrow wire or place a Label with the same direction according to metal wires in different directions, the Label with upright characters is placed at the positions after being rotated, but the characters in the rotated Label can be inverted or laid down, which is very inconvenient for the designer to draw or read the layout. Therefore, the method supports the user-defined arrangement mode of the characters of the Label, can conveniently place the Label in any narrow space in the layout, and a layout engineer can also select the proper arrangement mode of the Label characters according to the trend of the metal wire.
In the prior art, if the connection relation between units between two modules in a layout is required to be known, manual operation is required to be carried out on each line, and if the statistics is carried out on one line by one line, the efficiency is low; if the statistics are performed on a group of lines, uncertain results such as sequence errors may occur. And after the statistics is finished, manual inspection is needed, so that the efficiency is low, and the error rate is high. The invention provides an identification processing method for layout verification in integrated circuit design based on an Electronic Design Automation (EDA) tool, which is beneficial to a designer to quickly and accurately extract the connection relation between integrated circuit layout modules, quickly locate problems and modify a layout, thereby improving the working efficiency.
The present disclosure is described in detail below with reference to the accompanying drawings.
The first embodiment is as follows:
fig. 1 shows a schematic flow diagram of an identification processing method for layout verification according to an embodiment of the present disclosure, fig. 3 shows a schematic diagram of a parameter setting interface identified in the identification processing apparatus shown in fig. 2, and fig. 4a to 4c respectively show model schematic diagrams of the identification processing apparatus shown in fig. 2 in different application scenarios.
Referring to fig. 1 and fig. 3 to 4c, an embodiment of the present disclosure provides an identification processing method for layout verification in integrated circuit design based on an Electronic Design Automation (EDA) tool, which can be applied in integrated circuit design and liquid crystal panel design, and a graphic identification (Label) is automatically generated and placed by the EDA tool, and in this embodiment, the identification processing method includes:
step S110: and acquiring an input instruction received by a system end, and identifying the position information of the target layout graph in the input instruction.
In step S110, with the enlargement of the layout scale, the design rules required to be verified at each stage of the integrated circuit design are increased continuously, and how to establish the electrical connection between different graphs in each layer correspondingly and quickly, so that problem location and correction in the verification of various subsequent rules are a huge challenge. In this process, the position information of the target layout pattern includes: the position of the layer where the target layout graph is located, and the detailed area of the target layout graph distributed in the layer. In this embodiment, a user specifies a graph to be identified, and may automatically obtain a layer name to which the graph belongs through script information, and represent the layer to which the graph identifier belongs by using the layer name. Fig. 4c is a model diagram of a layer to which the layer name of the specified graph in this embodiment is automatically obtained and which is represented by using the layer name m1.drawing, and the graph identifier corresponding to the layer name is represented by using the layer name m1. drawing. Further, according to a graph designated by a user, a distribution area of the graph in the layer where the graph is located is automatically detected and is used as an effective area for generating the graph identifier. Fig. 4b shows that the specified graph is a metal Wire (Wire), then the position of the layer of the metal Wire in the layout and the distribution area of the layer are automatically detected, obviously, the left side is not in the effective area of the layer, and a model schematic of the graph identifier cannot be generated and placed, and fig. 4c shows that the model schematic of the graph identifier can be generated and placed in the effective area.
Step S120: and determining the identification name of the target layout graph, and determining the posture information of the target layout graph identification according to the input parameters received by the system end.
In step S120, the aforementioned identification name of the target layout pattern is used to characterize the electrical performance of the target layout pattern in the overall circuit. The aforementioned input parameters include typed graphic identification font information, height information, shape information, and a distribution region where the generated graphic identification pattern is located in the graphic, and the interface schematic of the input parameters is shown in fig. 3. The generated graphic identifier is required to accord with the integrated circuit layout design or liquid crystal panel design rule, can be identified by a verification tool, and is used for verifying the connection relation between objects according to the graphic identifier. Accordingly, the aforementioned gesture information of the graphic identifier includes: the font, size (mainly height), shape of the graphic identifier, and the location of the region where the graphic identifier is distributed in the target layout graphic, as shown in fig. 4 a. The user can specify the object (graph) required to generate the graph identifier (Label), and automatically generate the name of the graph identifier according to the script information of the object. FIG. 4a is a model illustration of a user-specified target layout pattern being VSS in an implementation scenario, and a pattern identifier having an identifier name of VSS is generated according to the target layout pattern.
Step S130: and indexing the position information of the target layout graph, and placing a graph identifier of the target layout graph at a corresponding position.
In step S130, the step of indexing the position information of the target layout pattern and placing the pattern identifier of the target layout pattern at the corresponding position may specifically include:
indexing the position information of the target layout graph, and determining a placing (distribution) area of a graph identifier in the target layout graph according to the input parameters; and
when the placement region exceeds the effective region of the target layout pattern, as shown in fig. 4b, the pattern identifier is rotated, translated and/or mirrored until the placement region is located in the effective region of the target layout pattern, as shown in fig. 4 c.
In the processing procedure of the graphical identifier of this embodiment, the user may automatically place the graphical identifier on the target graph, or may specify a series of options such as rotating the graphical identifier by an angle, translating, and/or mirroring the graphical identifier. The simple and effective realization can greatly save the huge time cost spent by a layout design engineer in generating and processing the graphic identifier, and effectively accelerate the layout design.
Specifically, for example: and (3) generating a graphic identification pattern when the mouse moves on the user-specified graphic, and clicking a left mouse button to automatically place the graphic identification. After the graphic identification pattern appears, the rotation and mirror image operation of the graphic identification can be realized through a right mouse button or a Shift + right button, and a Ctrl + right button, so that the graphic layer of the graphic identification is generated, and the position of the graphic layer of the designated graphic is the same.
Therefore, the method can help designers to quickly and accurately process the connection relation between the graphs in each module of the integrated circuit layout so as to quickly locate problems and modify the layout, thereby improving the working efficiency.
Example two:
fig. 2 is a schematic block diagram illustrating a structure of an identifier processing apparatus for layout verification according to a second embodiment of the present disclosure.
Referring to fig. 2 to fig. 4c, a second embodiment of the present disclosure provides an identification processing apparatus 100 for layout verification in an integrated circuit design, where the identification processing apparatus 100 is based on an Electronic Design Automation (EDA) tool and is configured to perform the identification processing method according to the first embodiment. In this embodiment, the identifier processing apparatus 100 includes: a first input module 110, a second input module 120 and an identification processing module 130,
the first input module 110 is configured to obtain an input instruction received by the system end, for example, information that can be generated through script data, and input an instruction by using a peripheral device connected to a data port, so as to establish an index channel between the script data information and each graph in the layout layer,
the second input module 120 is configured to obtain input parameters received by the system, where the input parameters include typewritten font information, height information, shape information, and distribution area of the generated graphic identification pattern in the graphic, and an interface schematic of the input parameter is shown in fig. 3,
the identifier processing module 130 is respectively connected to the first input module 110 and the second input module 120 in a communication manner, and is configured to identify position information of a target layout pattern in an input instruction, determine an identifier name of the target layout pattern, index the position information of the target layout pattern, and place a pattern identifier of the target layout pattern at a corresponding position.
Further, in this embodiment, the aforementioned identifier processing module 130 includes a microprocessor 131, and in one embodiment, the microprocessor 131 is configured to: and determining a placing region of the graph identifier in the target layout graph according to the input parameters, and when the placing region exceeds the effective region of the target layout graph, performing rotation, translation and/or mirroring operation on the graph identifier by algorithm planning and control until the placing region is positioned in the effective region of the layout graph.
In another alternative embodiment, the microprocessor 131 may be used to: and determining a placing region of the graph identifier in the target layout graph according to the input parameters, and executing rotation, translation and/or mirror image operation on the graph identifier according to the input instruction when the placing region exceeds the effective region of the target layout graph.
Therefore, when the identifier processing apparatus 100 provided in the embodiment of the present disclosure executes the identifier processing method described in the first embodiment, not only the workload of the user on the system side can be greatly reduced, but also errors caused by manual operation of the user can be effectively avoided, and the efficiency of layout design is effectively improved.
Example three:
fig. 5 shows a schematic structural diagram of a server provided in the third embodiment of the present disclosure.
Referring to fig. 5, the present disclosure also proposes a block diagram of an exemplary server suitable for implementing the first embodiment of the present disclosure. It should be understood that the server shown in fig. 5 is only an example, and should not bring any limitation to the function and the scope of the application of the embodiments of the present disclosure.
As shown in FIG. 5, server 200 is in the form of a general purpose computing device. The components of server 200 may include, but are not limited to: one or more processors or processing units 210, a memory 220, and a bus 201 that couples the various system components (including the memory 220 and the processing unit 210).
The system memory 220 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)221 and/or cache memory 222. The server 200 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 223 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 5, often referred to as a "hard drive"). Although not shown in FIG. 5, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 201 by one or more data media interfaces. Memory 220 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the disclosure.
Program/utility 224 having a set (at least one) of program modules 2241 may be stored, for example, in memory 220, such program modules 2241 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination of which may comprise an implementation of a network environment. Program modules 2241 generally perform the functions and/or methods of the embodiments described in the embodiments of the present disclosure.
Further, the server 200 may also be communicatively connected to a display 300 for displaying the result and progress of the identification process in the verification of the integrated circuit layout data, and the display 300 may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some embodiments, the display 300 may also be a display screen with an input device or a touch screen.
Further, the server 200 may also communicate with one or more devices that enable a user to interact with the server 200, and/or with any devices (e.g., network cards, modems, etc.) that enable the server 200 to communicate with one or more other computing devices. Such communication may be through input/output (I/O) interfaces 230. Also, server 200 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet) via network adapter 240. As shown, network adapter 240 communicates with the other modules of server 200 via bus 201. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the server 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
The processing unit 210 executes various functional applications and data processing by running programs stored in the system memory 220, for example, implementing an identification processing method for integrated circuit layout verification provided in the first embodiment of the present disclosure.
Example four
The fourth embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program (or referred to as computer-executable instructions) is stored, where the computer program is used, when executed by a processor, to execute the identification processing method for integrated circuit layout verification provided in the first embodiment of the present disclosure, and the method includes:
acquiring an input instruction received by a system end, and identifying the position information of a target layout graph in the input instruction;
determining the identification name of the target layout graph, and determining the posture information of the identification of the target layout graph according to the input parameters received by the system end; and
and indexing the position information of the target layout graph, and placing a graph identifier of the target layout graph at a corresponding position.
The computer storage media of the disclosed embodiments may take any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. Computer program code for carrying out operations for embodiments of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (10)
1. An identification processing method for layout verification, comprising:
acquiring an input instruction received by a system end, and identifying position information of a target layout graph in the input instruction;
determining the identification name of the target layout graph, and determining the posture information of the identification of the target layout graph according to the input parameters received by a system end; and
and indexing the position information of the target layout graph, and placing the graph identifier of the target layout graph at the corresponding position of the position information.
2. The tag processing method according to claim 1, wherein the position information of the target layout pattern includes: the position of the layer where the target layout graph is located, and the detailed area of the target layout graph distributed in the layer.
3. The identity processing method of claim 2, wherein the pose information of the graphical identity comprises: the font, size and shape of the graphic identifier and the region positions of the graphic identifier distributed in the target layout graphic.
4. The tag processing method according to claim 3, wherein said step of indexing the position information of the target layout pattern and placing the pattern tag of the target layout pattern at the corresponding position thereof comprises:
indexing the position information of the target layout graph, and determining a placing area of a graph identifier of the target layout graph according to the input parameters; and
and when the placement area exceeds the effective area of the target layout graph, performing rotation, translation and/or mirroring operation on the graph identifier until the placement area is positioned in the effective area of the target layout graph.
5. The tag processing method according to claim 4, wherein the tag name of the target layout pattern is used for characterizing the electrical performance of the target layout pattern in the whole circuit.
6. An identification processing device for layout verification, comprising:
the first input module is used for acquiring an input instruction received by the system end;
the second input module is used for acquiring input parameters received by the system end;
and the identification processing module is respectively in communication connection with the first input module and the second input module and is used for identifying the position information of the target layout graph in the input instruction, determining the identification name of the target layout graph, indexing the position information of the target layout graph and placing the graph identification of the target layout graph at the corresponding position.
7. The tag processing apparatus of claim 6, wherein the tag processing module comprises a microprocessor to:
and determining a placement area of the graph identifier in the target layout graph according to the input parameters, and when the placement area exceeds the effective area of the target layout graph, performing rotation, translation and/or mirroring operation on the graph identifier by algorithm planning and control until the placement area is positioned in the effective area of the target layout graph.
8. The tag processing apparatus of claim 6, wherein the tag processing module comprises a microprocessor to:
and determining a placement area of a graph identifier in the target layout graph according to the input parameters, and executing rotation, translation and/or mirroring operation on the graph identifier according to the input instruction when the placement area exceeds the effective area of the target layout graph.
9. A server, comprising:
a processor;
a memory for storing one or more programs;
wherein the one or more programs, when executed by the processor, cause the processor to implement the identification processing method for layout verification as claimed in any one of claims 1 to 5.
10. A computer-readable storage medium, on which a computer program is stored, wherein the program, when being executed by a processor, implements an identification processing method for layout verification according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111613804.5A CN114297739A (en) | 2021-12-27 | 2021-12-27 | Identification processing method and device for layout verification, server and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111613804.5A CN114297739A (en) | 2021-12-27 | 2021-12-27 | Identification processing method and device for layout verification, server and storage medium |
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| CN114297739A true CN114297739A (en) | 2022-04-08 |
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| CN116029257A (en) * | 2023-02-14 | 2023-04-28 | 弈芯科技(杭州)有限公司 | Method and device for identifying connection relation of graphics in layout verification |
| CN117556781A (en) * | 2024-01-12 | 2024-02-13 | 杭州行芯科技有限公司 | Target pattern determining method and device, electronic equipment and storage medium |
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| CN117556781B (en) * | 2024-01-12 | 2024-05-24 | 杭州行芯科技有限公司 | Target pattern determining method and device, electronic equipment and storage medium |
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