JP2017021571A - Semiconductor integrated circuit, and design support device and design method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the execution of a LVS even though there is a wiring error in a portion of a semiconductor integrated circuit of a layout verification object.SOLUTION: A semiconductor integrated circuit includes a circuit netlist read part 102 for reading a circuit netlist, a circuit layout data read part 103 for reading circuit layout data, a cell library read part 104 for reading a cell library, and an untargeted verification region data read part 105 for reading untargeted verification region data representing an untargeted region in the circuit layout data. The semiconductor integrated circuit includes verifying data generation means (boundary recognition part 106, boundary information analysis part 107, verifying circuit netlist generation part 108, and verifying circuit layout data generation part 109) for generating circuit layout data and a circuit netlist of a verification target region on the basis of the read data.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor integrated circuit, a design support apparatus and a design method thereof.

  In recent years, development of LSIs (Large Scale Integrated Circuits) and the like has been strongly demanded for further scale-up, higher performance, and multi-functionality due to technology miniaturization. For this reason, development is more complicated than in the past, and the design period has become very long. On the other hand, a product equipped with an LSI or the like is required to shorten a design period in order to be put on the market faster.

  In the layout design of a semiconductor integrated circuit, the design is guaranteed by timing verification after the placement and wiring process. After that, it is necessary to guarantee the design by layout verification for the data whose design is guaranteed by the timing verification. Layout verification is the final step of layout design, and it is known that there are verification items such as DRC (Design Rule Check) and LVS (Layout vs Schematic).

FIG. 13 is a flowchart showing an example of the layout verification design method described in Patent Document 1.
As shown in the figure, first, a mask layout pattern (circuit layout data) of an electronic device is read (step S101), and designed circuit information (circuit netlist) is read (step S102). Next, DRC of the mask layout pattern read in step S101 is performed (step S103), and then it is determined whether or not there is an error (step S104).

  If an error is detected as a result of DRC (step S104: No), mask layout pattern correction is required (step S105). On the other hand, if no error is detected as a result of DRC (step S104: Yes), ERC (Electrical Rule Check) of the mask layout pattern read in step S101 is performed, and the signal line is opened. A short circuit is detected (step S106).

  Next, it is determined whether or not there is an error (step S107). If an error is detected as a result of ERC (step S107: No), it is necessary to correct the mask layout pattern (step S108). On the other hand, if no error is detected as a result of ERC (step S107: Yes), LVS of the mask layout pattern read in step S101 and the circuit information read in step S102 is subsequently performed (step S109). .

  Next, it is determined whether or not there is an error (step S110). If an error is detected as a result of LVS (step S110: No), mask layout pattern correction is required (step S111). On the other hand, if no error is detected as a result of the LVS (step S110: Yes), it is verified that the mask layout pattern matches the circuit information.

  Thus, in the conventional layout design verification method, LVS is executed after no error is detected by ERC. The reason is that, when there is a wiring error in ERC, particularly when there is a wiring short, it is an incorrect connection, so even if LVS is executed in this state, the circuit information does not match and the accuracy of the LVS verification result decreases. Because.

  However, the conventional layout design verification method has a problem that LVS cannot be executed until there is no wiring error in the entire layout verification target circuit.

  The present invention has been made to solve such a problem, and an object of the present invention is to make it possible to execute LVS even if there is a wiring error in a part of a semiconductor integrated circuit subject to layout verification. .

  A design support device for a semiconductor integrated circuit according to the present invention comprises: circuit layout data reading means for reading circuit layout data of a semiconductor integrated circuit; circuit net list reading means for reading a circuit net list of the semiconductor integrated circuit; and the circuit layout data. Non-verification area data reading means for reading the non-verification area data representing the non-verification area, and based on the circuit netlist, the circuit layout data, and the non-verification area data, A design support apparatus for a semiconductor integrated circuit, comprising: verification data generation means for generating circuit layout data and a circuit netlist.

  According to the present invention, LVS can be executed even if there is a wiring error in a part of a semiconductor integrated circuit subject to layout verification.

1 is a block diagram showing a hardware configuration of a layout verification apparatus including a design support apparatus for a semiconductor integrated circuit according to an embodiment of the present invention. It is a block diagram which shows the function structure of the design support apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. 5 is a flowchart showing the operation of the semiconductor integrated circuit design support apparatus according to the embodiment of the present invention. It is a flowchart which shows the boundary information analysis process in FIG. It is a figure which shows an example of the circuit layout data of 1 chip | tip verified with the layout verification apparatus containing the design support apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. FIG. 6 is a diagram showing a first example of a non-verification area set in the circuit layout data shown in FIG. 5. It is a figure which shows an example of the format of the file which describes the area | region which is not verification object shown in FIG. FIG. 6 is a diagram showing a circuit configuration in consideration of an internal power supply configuration in the circuit layout data shown in FIG. 5. It is a figure for demonstrating the designated coordinate trace process with respect to the circuit layout data shown in FIG. It is a figure for demonstrating the size of the point which moves in the designated coordinate trace process shown in FIG. 9, and a data acquisition interval. It is a figure which shows the 2nd example of the non-verification area | region set to the circuit layout data shown in FIG. It is a figure which shows an example of the format of the file which described the non-verification area | region shown in FIG. It is a flowchart which shows an example of the conventional layout verification design method.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<Hardware configuration of design support device>
FIG. 1 is a block diagram showing the hardware configuration of a layout verification apparatus including a semiconductor integrated circuit design support apparatus (hereinafter referred to as a design support apparatus) according to an embodiment of the present invention.

  As shown in the figure, the layout verification apparatus 100 includes a CPU 1, a ROM 2, a RAM 3, a keyboard 4, a mouse 5, a display device 6, and an HD (hard disk) 7 each connected to the CPU 1.

  The CPU 1 controls the entire apparatus. The ROM 2 stores an OS (operating system) program. The OS program is executed when the layout verification apparatus 100 is activated. The RAM 3 is used as a work area when the layout verification process is executed.

  The keyboard 4 and the mouse 5 as operation means function as a human interface and are used for various settings in the layout verification process. The display device 6 also functions as a human interface, and is used for displaying the contents of various settings and the operating state of the device.

  In addition to the layout verification program, the HD 7 stores a circuit net list, circuit layout data, cell library, non-verification area data, verification circuit net list, and verification circuit layout data, which will be described later.

  The layout verification program is read from the HD 7 to the RAM 3 and executed. The layout verification program may be recorded on a recording medium (for example, CD-ROM) other than HD7 and read to the RAM 3 by a corresponding reading device (CD-ROM drive device).

<Functional configuration of design support device>
FIG. 2 is a block diagram showing a functional configuration of the design support apparatus according to the embodiment of the present invention.
As illustrated, the design support apparatus 101 includes a circuit netlist reading unit 102, a circuit layout data reading unit 103, a cell library reading unit 104, a non-verification area data reading unit 105, a boundary recognition unit 106, and a boundary information analysis unit 107. , A verification circuit netlist generation unit 108 and a verification circuit layout data generation unit 109 are provided. Each unit constituting the design support apparatus 101 is a functional block realized by the CPU 1 reading and executing a layout verification program from the HD 7.

  Here, the circuit net list reading unit 102, the circuit layout data reading unit 103, the cell library reading unit 104, and the non-verification area data reading unit 105 are respectively a circuit net list reading unit, a circuit layout data reading unit, This corresponds to the non-verification area data reading means. The boundary recognition unit 106, the boundary information analysis unit 107, the verification circuit netlist generation unit 108, and the verification circuit layout data generation unit 109 correspond to the verification data generation unit according to the present invention.

  The circuit net list reading unit 102, the circuit layout data reading unit 103, and the cell library reading unit 104 are respectively supplied from the circuit net list storage unit 72, the circuit layout data storage unit 73, and the cell library storage unit 74. The cell library is read and stored in the RAM 3.

  The circuit netlist is data including connection information of circuit elements and wirings in the semiconductor integrated circuit, and is generated by a circuit diagram editor, a placement and routing tool, or the like. The circuit netlist has a hierarchical structure. For example, the top layer (first layer) is data relating to a functional block, and the second layer is various logic circuits (AND circuit, OR, which are internal circuits in the functional block). Circuit, flip-flop circuit, etc.) cell data.

  The cell library is a library of cell data including shapes (graphic data) such as various cells (AND circuit, OR circuit, flip-flop circuit, I / O buffer), and internal configuration data (transistors and wirings).

  The circuit layout data is mask pattern data generated by a placement and routing tool from a circuit netlist having a hierarchical structure and a cell library, and includes position information on a chip of a semiconductor integrated circuit circuit element and wiring.

  The non-verification area data reading unit 105 reads the non-verification area data from the non-verification area data storage unit 75. The non-verification area data is data representing an area to be excluded from the layout verification target in the mask pattern represented by the circuit layout data. This non-verification data is preset for each circuit layout data.

  The boundary recognition unit 106 includes a circuit net list read by the circuit net list reading unit 102, circuit layout data read by the circuit layout data reading unit 103, a cell library read by the cell library reading unit 104, and a non-verification target. Based on the non-verification area data read by the area data reading unit 105, a portion that is not subject to layout verification in the circuit layout data is recognized, and the outer edge of the non-verification area, that is, the non-verification area and the verification target area, Is stored in the RAM 3.

  Based on the coordinate information stored in the boundary recognition unit 106, the boundary information analysis unit 107 receives text data (flip-flop circuit, AND circuit, GND, VCC, etc.), graphic data, or layout data of the circuit at the boundary part. Obtained and stored in the RAM 3. Details of the procedure for acquiring these data will be described later with reference to FIG.

  The verification circuit net list generation unit 108 reads a verification circuit net list that reflects the information stored in the boundary information analysis unit 107 with respect to the circuit net list read and stored by the circuit net list reading unit 102. It is generated and stored in the verification circuit netlist storage unit 76.

  The verification circuit layout data generation unit 109 generates verification layout data that reflects the information stored in the boundary information analysis unit 107 with respect to the layout data read and stored by the circuit layout data reading unit 103. And stored in the circuit layout data storage unit 77 for verification.

  As will be described later, the verification circuit netlist and the verification circuit layout data are verified by LVS. That is, the design support apparatus 101 generates data that enables LVS verification to be performed at a desired location even during a layout design and a wiring short circuit remains.

  Since layout verification is a known technique, the design support apparatus 101 may be incorporated in the layout verification apparatus 100 as in this embodiment, and data created by the design support apparatus 101 may be directly or indirectly generated. May be read by the layout verification apparatus to perform layout verification.

<Operation of layout verification data generator>
FIG. 3 is a flowchart showing the operation of the design support apparatus 101.

  As shown in the figure, first, the circuit net list is read by the circuit net list reading unit 102 (step S1), the circuit layout data is read by the circuit layout data reading unit 103 (step S2), and the cell library is read by the cell library reading unit 104. (Step S3) and non-verification area data reading unit 105 read non-verification area data (step S4) in parallel. Steps S1 to S4 may be performed sequentially.

  Next, boundary recognition (step S5) is performed by the boundary recognition unit 106. Next, boundary information analysis (step S6) is performed by the boundary information analysis unit 107. Details of this step will be described later with reference to FIGS. 4 and 8 to 10.

  Next, verification circuit netlist generation by the verification circuit netlist generation unit 108 (step S7) and verification circuit layout data generation by the verification circuit layout data generation unit 109 (step S8) are performed in parallel. Steps S7 and S8 may be performed sequentially.

  The verification circuit netlist generated in step S7 is used for LVS, and the verification circuit layout data generated in step S8 is used for DRC, ERC, and LVS. In the DRC, it is confirmed whether or not the verification layout data satisfies the design standard value. In ERC, the presence or absence of a wiring error (short, open, etc.) is confirmed. In the LVS, it is confirmed whether or not the verification circuit layout data is created according to the verification circuit netlist (including the presence or absence of a wiring error). In other words, the subsequent operation is obtained by replacing the layout data and circuit information read in steps S101 and S102 in FIG. 13 with the verification circuit layout data and the verification circuit netlist, respectively.

<Boundary information analysis processing>
FIG. 4 is a flowchart showing the boundary information analysis processing in FIG.
First, designated coordinate trace processing (step S61) is executed. In this process, the circuit layout data on the boundary line between the non-verification area and the verification target area represented by the non-verification area data among the circuit layout data is sampled at a predetermined size and a predetermined interval, Get the data. These sizes and intervals are sizes and intervals that do not cause any problem in acquiring circuit layout data (a specific example of the size, interval, and acquired data will be described later with reference to FIG. 10).

  Next, a non-verification area analysis process (step S62) is executed. In this process, a signal required as a net list and a signal required as a layout are acquired from the data acquired in step S61.

  Next, a data correction process (step S63) for the non-verification area is executed. In this process, the circuit layout data and circuit netlist on the boundary are deleted based on the information acquired in step S62. When all the circuit layout data and circuit netlist on the boundary are deleted, the processing shown in FIG.

  In step S63, not only the data on the boundary but also all circuit layout data and circuit netlist in the non-verification area may be deleted. Thereby, the data amount to hold | maintain can be reduced.

  That is, in step S63, the layout is deleted only in the portion (on the boundary) in accordance with the moved trajectory, and the connection with the portion to be excluded is eliminated. In this process, since only the information related to LVS verification is changed, the data amount hardly changes. Portions that are not subject to LVS verification (within the boundary) other than the information acquired by tracing need not be retained as information, and may be deleted from the circuit netlist and circuit layout data. Therefore, the amount of data to be retained is reduced by deleting data that is not subject to LVS verification.

<Example of circuit layout data>
FIG. 5 is a diagram showing an example of one-chip circuit layout data verified by the design support apparatus 101 according to the embodiment of the present invention. Here, for convenience of explanation, only the I / O buffer and its wiring located in the peripheral part of the chip are shown, and the internal logic and its wiring located in the central part of the chip are omitted.

  The circuit layout data 200 includes wirings 201 to 207 and divider cells 211 to 214. The LVS verification can be performed by giving the wirings 201, 205, and 207 the LVS attribute (text) as ground wirings named GND, GND3, and GND4, respectively. Further, the LVS verification can be performed by giving the wirings 202, 203, 204, and 206 the LVS attribute (text) as the power supply wirings named VCC1, VCC2, VCC3, and VCC4, respectively. Here, GND3 and VCC3 and GND4 and VCC4 are paired.

  Divider cells 211 to 214 are I / O buffers for cutting power supply wiring and ground wiring. The I / O buffers (blocks shown by rectangles) other than the divider cells 211 to 214 are power supply cells.

<First setting example of non-verification area>
FIG. 6 is a diagram illustrating a first example of a non-verification region set in the circuit layout data illustrated in FIG.

  The non-verification area 300 is an area to be set as being out of LVS. Here, the shape of the outer edge of the non-verification region 300 is a rectangle, and the bending points (vertices in the case of a rectangle) are P1, P2, P3, and P4 in the counterclockwise order from the lower left corner. The positions of the vertices P1, P2, P3, and P4 are expressed in the form of two-dimensional coordinates (X coordinate, Y coordinate) on the chip.

  FIG. 7 is a diagram showing an example of a format of a file describing the non-verification area shown in FIG. Here, the text 400 composed of “ExemptArea” represents an instruction for causing the apparatus to recognize the non-verification area, and the coordinates (400, 400), (4600, P4) of P1, P2, P3, and P4 designated after that are indicated. 400), (4600, 4600), and (400, 4600) are connected by a straight line, and the apparatus is set as a non-LVS verification target area. Here, the lower left corner of the chip is the origin of coordinates, but the other end (for example, the upper left corner) may be the origin.

<Circuit configuration considering internal power source configuration>
FIG. 8 is a diagram showing a circuit configuration in consideration of the internal power supply configuration in the circuit layout data shown in FIG.

  In this figure, since the wiring 2001 is connected to the wiring 202, the wiring 2001 is given the LVS attribute as the power supply wiring named VCC1 which is the same as the LVS attribute of the wiring 202. Further, since the wiring 2002 is connected to the wiring 201, the wiring 2002 has the LVS attribute as a ground wiring named GND that is the same as the LVS attribute of the wiring 201. 6 is a rectangle formed by the outer edge of the non-verification region 300 shown in FIG. 6, that is, the boundary line between the non-verification region 300 and the verification target region (hereinafter referred to as the boundary). Rectangle 310).

<Specified coordinate trace processing for circuit layout data>
FIG. 9 is a diagram for explaining the designated coordinate trace processing (step S61 in FIG. 4) for the circuit layout data shown in FIG. FIG. 10 is a diagram for explaining the size of a moving point and the data acquisition interval in the designated coordinate tracing process shown in FIG.

  In FIG. 9, an arrow 2101 indicates that data is acquired by moving from the lower left end of the boundary rectangle 310 (vertex P1 of the non-verification region 300) to the lower right end (same P2). Similarly, an arrow 2102 represents a movement from the lower right end to the upper right end (P3), an arrow 2103 represents a movement from the upper right end to the upper left end (P4), and an arrow 2104 represents a movement from the upper left end to the lower left end. .

  In this way, when moving in the direction of the arrows 2101 to 2104 in order, the figure touched during the movement while moving at a point and interval of a size that does not cause a problem to obtain circuit layout data, and the text information touched to the figure To get.

  That is, as shown in FIG. 10A, a sufficiently small point 2201 that does not cause a problem in acquiring circuit layout data such as a minimum unit of wiring is sufficiently short as shown in a point group 2202 in FIG. 10B. Move at intervals. This figure shows the time when moving in the direction of the arrow 2101. Here, information such as the LVS attribute, metal coordinates, metal layer, and metal width of the intersecting wiring 2101 and wiring 2102 is acquired and stored in the RAM 3.

  For example, “SPECIALNETS” in DEF (Design Exchange Format), which is a layout data (circuit layout data) format for automatic placement and routing, is a special net (wiring) that represents the attributes of power supply and GND. Information such as a wiring name, a wiring layer, and coordinates is stored. Not only DEF but also layout data of automatic placement and routing generally stores information such as wiring names, wiring layers, coordinates, etc., so these text information on the database of automatic placement and routing tools Metal information can be acquired.

  Similarly, the circuit layout data and the circuit net list data on the boundary rectangle 310 are acquired by repeating the movement in the directions of arrows 2102, 2103, and 2104. Then, when the coordinates (400, 400) of P1 are reached, all the points designated as the boundary have been passed, and the processing is terminated. In this case, it moves counterclockwise, but it may move clockwise. The movement start position may not be the lower left corner.

  The point size and movement interval described here can be changed according to the development technology of the semiconductor integrated circuit. At this time, the layout of the locus of the moved point is deleted (for example, in the case of FIG. 10B, the LVS attribute of the wiring 2101 and the wiring 2102 and information such as the metal coordinates, the metal layer, the metal width, etc. are deleted). Since the upper wiring is not connected, the LVS attribute is not propagated.

  It is possible to output the circuit layout data and the circuit net list corrected as described above as the verification circuit net list and the verification circuit layout data by a known technique.

<Second setting example of non-verification area>
FIG. 11 is a diagram showing a second example of the non-verification region set in the circuit layout data shown in FIG.

  The non-verification area 320 is an area that is desired to be set not to be an LVS target. Here, the shape of the non-verification region 320 is a hexagon obtained by adding two rectangles, and the bending points are P11, P12, P13, P14, P15, and P16 in the counterclockwise order from the lower left corner. The positions of the bending points P11 to P16 are expressed in the form of two-dimensional coordinates (X coordinate, Y coordinate) on the chip. Thus, the shape of the outer edge of the verification target region can be an arbitrary polygon.

  FIG. 12 is a diagram showing an example of a format of a file describing the non-verification area shown in FIG. Here, an instruction for causing the apparatus to recognize the non-verification area is shown, and coordinates (400, 400), (4600, 400), (4, P11, P12, P13, P14, P15, P16 designated thereafter are represented. 4600, 3500), (3500, 3500), (3500, 4600), (400, 4600) are connected by a straight line, and the apparatus is set as an LVS verification non-target area. Here, the lower left corner of the chip is the origin of coordinates, but the other end (for example, the upper left corner) may be the origin.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention.

  DESCRIPTION OF SYMBOLS 100 ... Layout verification apparatus 101 ... Design support apparatus 102 ... Circuit net list reading part 103 ... Circuit layout data reading part 104 ... Cell library reading part 105 ... Non-verification area data reading part 106 ... Boundary recognition part , 107 ... boundary information analysis unit, 108 ... verification circuit net list generation unit, 109 ... verification circuit layout data generation unit.

JP-A-6-37183 (paragraph 0005, FIG. 11)

Claims (6)

Circuit layout data reading means for reading circuit layout data of a semiconductor integrated circuit;
Circuit net list reading means for reading a circuit net list of the semiconductor integrated circuit;
Of the circuit layout data, the non-verification area data reading means for reading the non-verification area data representing the non-verification area,
Verification data generation means for generating circuit layout data and circuit netlist of a verification target area based on the circuit netlist, the circuit layout data, and the non-verification area data;
A device for supporting design of a semiconductor integrated circuit. The design support apparatus for a semiconductor integrated circuit according to claim 1,
The non-verification region data is a design support device for a semiconductor integrated circuit, comprising data representing coordinates of polygonal bending points that constitute a boundary between the non-verification region and the verification region. The design support apparatus for a semiconductor integrated circuit according to claim 2,
A design support apparatus for a semiconductor integrated circuit, wherein the polygon is a rectangle. The design support apparatus for a semiconductor integrated circuit according to claim 2,
The verification data generation means includes boundary information analysis means for acquiring wiring and circuit element information on the boundary, and results of acquisition of the information by the boundary information analysis means as the read circuit layout data and circuit network. A design support apparatus for a semiconductor integrated circuit, comprising data generation means for generating a circuit net list and circuit layout data of the verification target area by reflecting the result in a list. A circuit layout data reading process for reading circuit layout data of a semiconductor integrated circuit;
A circuit net list reading step of reading a circuit net list of the semiconductor integrated circuit;
Of the circuit layout data, a non-verification area data reading step for reading non-verification area data representing a non-verification area;
A verification data generation step for generating circuit layout data and a circuit netlist of a verification target region based on the circuit netlist, the circuit layout data, and the non-verification region data;
A method for designing a semiconductor integrated circuit. A semiconductor integrated circuit designed by the method for designing a semiconductor integrated circuit according to claim 5.

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