CN103106294A - Territory programming method for static random access memory compiler - Google Patents
Territory programming method for static random access memory compiler Download PDFInfo
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Abstract
The invention provides a territory programming method for a static random access memory compiler. The territory programming method for the static random access memory compiler comprises that the position, needing to be programmed, in a territory is marked, a marked text content or a marked image contains information needed by generation of the territory according to a center regular; the complier identifies an existing mark in the territory and records information such as a coordinate, text content and image size which are needed by programming; and the compiler finds the position needing operation according to extracted information and through search or calculation and conducts territory operation on the position. According to the territory programming method for the static random access memory compiler, the marks in the territory serve as carriers, in the meantime that normal territory design is not influenced, the information needed by territory programming is directly embedded in the territory without the requirement for adding the information after finish of the territory and territory design time is shortened; the information needed by the territory programming is automatically extracted so that manual power and time are saved; and in the territory programming, a procedure is operated according to the marks without reference to specific territory information, so that the compiler is large in flexibility and transportability.
Description
[technical field]
The present invention relates to the static RAM design field, particularly a kind of domain programmed method for the static RAM compiler.
[background technology]
Static RAM (SRAM) is a kind of common random access memory, is widely used in integrated circuit fields.Wherein be applicable to the static RAM IP(intellecture property of integrated circuit SOC (system on a chip) (SoC:System on Chip): Intelligent Property) be most widely used at present, become one of most basic IP of integrated circuit technology line.SRAM IP generally pays the user with the form of compiler and uses, and the user can generate the SRAM of specified vol, shape and performance according to the demand of oneself with compiler.
The SRAM compiler can generate the several data file that comprises domain.The ultimate principle that compiler generates domain is the module splicing, begins to be spliced to form high-level module from elementary cell, and then these modules are spliced until finally form a complete domain.Traditional SRAM compiler is in realizing the process of this domain splicing with programming, and layout information that can program is required such as coordinate, size etc., directly writes in program, in case cause domain to change, need to remodify and program compiler.The required layout information of program is obtained by designer's manual measurement after being to complete layout design in some traditional SRAM compilers in addition, needs more time and manpower, causes the design cycle longer.
[summary of the invention]
The object of the invention is to propose a kind of domain programmed method for the static RAM compiler, when guaranteeing not affect layout design, accomplished separating of layout design and program design, shortened the design cycle, and made compiler have greater flexibility and portability.
For achieving the above object, the present invention adopts following technical scheme:
A kind of domain programmed method for the static RAM compiler comprises the following steps:
The first step, in elementary cell layout design process, when compiler is spliced domain, the information of needs is embedded in the elementary cell domain; Described information adds in domain with the form of mark;
Existing mark in second step, compiler identification elementary cell domain, the information that needs when splicing domain to extract;
The 3rd step, compiler find by searching or calculating the position that needs operation according to the information of extracting, and carry out the domain operation in this position.
The present invention further improves and is: described mark comprises figure and text label.
Mark is positioned on some auxiliary layers that do not affect normal layout design.
The present invention further improves and is: described information comprises layout contour, punching mark and port label;
Layout contour is a pictorial symbolization, and its rule is: use an auxiliary layer (such as the BORDER layer) to draw a rectangle as the profile of elementary cell domain.The position of this rectangle is by the determining positions of the domain of elementary cell.For for simplicity, make this rectangle lower left corner be positioned at (0,0) some during the elementary cell layout design, the coordinate in the upper right corner is exactly the layout size of this elementary cell;
The punching mark is a text label, and its rule is: use an auxiliary layer (such as the TXT layer) to do a text label in the center of needs punching; The coordinate of this label is exactly the position that needs punching; The content of text of this label has comprised the information of punching needs, and can be used for identifying different punching marks.
Port label is to be combined by a figure and a text label, and its rule is: at first use an auxiliary layer (such as the TXT layer) to do a text label in the position of port; The coordinate of this label is exactly the position of port; Next uses this auxiliary layer to draw a rectangle as the shape of port, the position of the text label of marking before the profile of rectangle has comprised, and the width of rectangle equals the width of this port metal wire.
The present invention further improves and is: the content of text of the label of punching mark comprises three parts and is separated by underscore " _ ", first " VIA " represents that this is a punching mark, second portion represents the type of needs punching, and third part is that the title of label is used for distinguishing the different punching mark of same elementary cell domain;
The content of text of the label of port label comprises three parts and is separated by underscore " ", first " PIN " represents that this is a port label, second portion need to represent the metal level type of port, and third part is that the title of port is used for distinguishing the different port label of same elementary cell domain.
The present invention further improves and is: it is exported as a GDSII file after completing the elementary cell layout design; Compiler directly reads in the GDSII file, find figure and the text mark that meets rule described in the first step in each elementary cell domain by scanning, and relevant information is extracted from the GDSII file: find to belong to the BORDER layer and lower left corner coordinate is (0,0) rectangle is recorded the title of the elementary cell at the coordinate in its upper right corner and place; Find to belong to TXT layer and content of text with the text label of " VIA " or " PIN " beginning, the title of the elementary cell at its coordinate, content of text and place is recorded; Find the rectangle that belongs to the TXT layer, if this rectangle has comprised that one belongs to TXT layer and content of text with the coordinate of the text label of " PIN " beginning, with the coordinate in the lower left corner and the upper right corner of rectangle, the title of the content of text of included text label and place elementary cell is recorded.
The present invention further improves and is: described elementary cell domain comprises: storage unit module, word-line decoder module, data input/output module and control module.
The present invention further improves and is: add the process of mark to carry out simultaneously with the design process of domain in the domain of elementary cell.Needs according to programming when layout design make marks, and the text label of mark or figure have comprised the needed information of generation domain according to certain rule.Text label is arranged in specific figure layer of domain upward or has the text that meets certain rule.The information that text label can comprise comprises coordinate and content of text, and wherein content of text can be entered according to certain rule message composition that needs of programming.Pictorial symbolization is arranged in a specific figure layer of domain.The information that figure can comprise comprises coordinate, size, border and figure layer;
The present invention further improves and is: existing mark in compiler identification domain, and record the information that the programmings such as its coordinate, content of text, dimension of picture need.Compiler is identified and its coordinate, size, border and figure layer information is extracted the figure that is positioned on the specific pattern layer.Compiler is identified and its coordinate and content of text is extracted being positioned on the specific pattern layer or having the label that meets certain regular content of text.
The present invention further improves and is: compiler finds by searching or calculating the position that needs operation according to the label information that extracts, and carries out the domain operation in this position.Position in domain can accurately represent with coordinate.Compiler can obtain its coordinate by searching certain mark, as the position of domain operation; Compiler also can be on the basis of known coordinate, according to and known module between position relationship be of a size of side-play amount with pictorial symbolization, calculate the position of required domain operation.
With respect to prior art, the present invention has the following advantages:
The present invention proposes a kind of domain programmed method for the static RAM compiler, with the carrier that is labeled as in domain, during the information that when not affecting normal layout design, the domain programming is needed is directly embedded into domain, do not need to add again after domain is completed by the time, can shorten the time of layout design; Extract by the method for the automatic identification marking of compiler the information that the domain programming needs, saved manpower and time; Operate according to mark in program when carrying out the domain programming, do not need to relate to concrete layout information, accomplished separating of layout design and program design, make compiler have greater flexibility and portability.
[description of drawings]
Fig. 1 is process flow diagram of the invention process.
Fig. 2 generates the example of domain according to a SRAM compiler of the invention process.
Fig. 3 is the partial schematic diagram that adds in basic territory unit CTRL after mark.
Fig. 4 is the partial schematic diagram that adds in basic territory unit DEC1 after mark.
Fig. 5 is the profile schematic diagram of basic territory unit IO1 and ROW1.
Fig. 6 calculates the schematic diagram of stitching position according to dimension of picture in the domain splicing.
Fig. 7 selects the schematic diagram of punch position according to text label in the domain splicing.
Fig. 8 is the schematic diagram of according to figure and text mark, port TM being programmed in the domain splicing.
[embodiment]
Below in conjunction with accompanying drawing, embodiments of the present invention are described further.
See also shown in Figure 1ly, Fig. 1 is process flow diagram of the invention process.
The first step adds domain with mark by the slip-stick artist in elementary cell layout design process in.For convenience's sake, the lower left corner coordinate of stipulating all elementary cell domains all is positioned at (0,0) point.What need interpolation is marked with three kinds: layout contour, punching, port.
Layout contour is a pictorial symbolization, its rule is: use BORDER layer (auxiliary layer in layout design) to draw a rectangle as the profile of elementary cell domain, this rectangle lower left corner is positioned at (0,0) point, and the coordinate in the upper right corner is exactly the layout size of this elementary cell;
The punching mark is a text label, and its rule is: use TXT layer (auxiliary layer in layout design) to do a text label in the center of needs punching.The coordinate of this label is exactly the position that needs punching.The content of text of this label comprises three parts and is separated by underscore " _ ", first " VIA " represents that this is a punching mark, second portion represents the type (namely being connected to other one deck from certain one deck punching) of needs punching, and third part is that the title of label is used for distinguishing the different punching mark of same elementary cell domain.
Port label is to be combined by a figure and a text label, and its rule is: at first use the TXT layer to do a text label in the position of port.The coordinate of this label is exactly the position of port.The content of text of this label comprises three parts and is separated by underscore " _ ", first " PIN " represents that this is a port label, second portion need to represent the metal level type (being certain one deck metal) of port, and third part is that the title of port is used for distinguishing the different port label of same elementary cell domain.Next uses the TXT layer to draw a rectangle as the shape of port, the position of the text label of marking before the profile of rectangle has comprised, and the width of rectangle equals the width of this port metal wire.
Second step is identified existing mark in the elementary cell domain by compiler, and records the information of its coordinate, content of text, dimension of picture programming needs.It is exported as a GDSII file after completing the elementary cell layout design.The GDSII file is the binary stream file of a standard format, compiler directly reads in the GDSII file, find figure and the text mark that meets rule described in the first step in each elementary cell domain by scanning, and relevant information is extracted from the GDSII file: find to belong to the BORDER layer and lower left corner coordinate is (0,0) rectangle is recorded the title of the elementary cell at the coordinate in its upper right corner and place; Find to belong to TXT layer and content of text with the text label of " VIA " or " PIN " beginning, the title of the elementary cell at its coordinate, content of text and place is recorded; Find the rectangle that belongs to the TXT layer, if this rectangle has comprised that one belongs to TXT layer and content of text with the coordinate of the text label of " PIN " beginning, with the coordinate in the lower left corner and the upper right corner of rectangle, the title of the content of text of included text label and place elementary cell is recorded.
The 3rd step compiler finds by searching or calculating the position that needs operation according to the information of extracting, and carries out the domain operation in this position.Wherein calculate and refer to conventional coordinate transform, as translation, mirror image, rotation etc.Layout contour is used for the concatenation of domain, and the punching mark is used for carrying out punch operation on domain, and port label is used for adding the operation of port on domain.Each mark can be by the title of its place elementary cell and the title unique definite (layout contour even only needs the title of place elementary cell) of mark, therefore when programming, only need to be in program the title of assigned tags place elementary cell and the title of mark itself, compiler just can find by the record of searching the second step generation layout information of concrete operations needs with complete operation.Owing to not comprising concrete layout information in compiler program, in case therefore domain is revised, only need to the reform first step and second step get final product.
See also shown in Figure 2ly, Fig. 2 generates the example of domain according to SRAM compiler of the invention process.Elementary cell one has 4: storage unit module ROW1, word-line decoder module DEC1, data input/output module IO1 and control module CTRL.The width of each storage unit module ROW1 is identical with the width of data input/output module IO1, corresponding a data.The height of each storage unit module ROW1 is identical with the height of word-line decoder module DEC1, corresponding this root word line (WL).The width of word-line decoder module DEC1 is identical with the width of control module CTRL.Compiler splices complete domain according to the difference of data bit width and word line number on the basis of described 4 elementary cells.Shown in Fig. 2, for data bit width is 4, word line number is 4 situation.
See also shown in Figure 3ly, Fig. 3 is the partial schematic diagram that adds in basic territory unit CTRL after mark.The input ports such as the address of SRAM, order, clock all are positioned at control module CTRL place, and the TM in Fig. 3 is exactly an input port.At first use the BORDER layer to draw a rectangle as profile, the coordinate in its lower left corner (0,0), the coordinate (A, B) in the upper right corner, its domain is wide is A, height is B.Secondly do text label " PIN_M2_TM " and rectangle at port TM at outgoing position place's use TXT layer, expression port TM is connected with outside by the metal wire that belongs to M2 layer (second layer metal), the place is marked by rectangle in the position, the width means of rectangle the width of the M2 line of telling.Use the TXT layer to be respectively text label " VIA_M2M1_TM_VDD " and " VIA_M2M1_TM_VSS " in the M2 of port TM line and the center that crosses of the power supply vdd line that is positioned at M1 layer (first layer metal) and ground VSS line at last, represent that described two positions may need to carry out punch operation, concrete coordinate is the coordinate of respective labels, and the punching type is that the M2 layer is to the M1 layer.The mark punching that is called " TM_VDD " in name will make the TM port be connected to power supply, namely be fixed as ' 1 '; The mark punching that is called " TM_VSS " in name will make the TM port be connected to ground, namely be fixed as ' 0 '.All the other ports all can be done similar processing except TM.
See also shown in Figure 4ly, Fig. 4 is the partial schematic diagram that adds in basic territory unit DEC1 after mark.This elementary cell is a code translator.At first use the BORDER layer to draw a rectangle as profile, the coordinate in its lower left corner (0,0), the coordinate (C, D) in the upper right corner, its domain is wide is C, height is D.Secondly compiler need to all be positioned at the M2 layer from signal wire A, AN, B, the BN(that comes from control module CTRL when splicing, and AN is the designature of A, and BN is the designature of B) two two inputs (I1 and I2) that are connected to code translator of middle selection.First input I1 crosses with the A, the AN that are positioned at the M2 layer at the M1 layer, uses the TXT layer to be respectively text label " VIA_M2M1_A " and " VIA_M2M1_AN " in the center of described intersection; Second input I2 crosses with the B, the BN that are positioned at the M2 layer at the M1 layer, uses the TXT layer to be respectively text label " VIA_M2M1_B " and " VIA_M2M1_BN " in the center of described intersection; Just can find punch position accurately by above-described four punching compilers.
See also shown in Figure 5ly, Fig. 5 is the profile schematic diagram of basic territory unit IO1 and ROW1.Punching mark and port label do not show in Fig. 5, have only shown the layout contour mark that is used for concatenation.The profile of storage unit module ROW1 is a rectangle that is positioned at the BORDER layer, lower left corner coordinate (0,0), upper right corner coordinate (E, D).The profile of data input/output module IO1 is a rectangle that is positioned at the BORDER layer, lower left corner coordinate (0,0), upper right corner coordinate (F, B).
See also shown in Figure 6ly, Fig. 6 calculates the schematic diagram of stitching position according to dimension of picture in the domain splicing.Compiler is exactly with program, splicing as shown in Figure 6 to be realized.Due to the existence of layout contour mark, when concatenation, program only need to be known the module that newly adds and the position relationship between existing module, and concrete coordinate is according to this relation with extract label information and calculate.
Splicing generation module ROW4: point is placed a ROW1 in (0,0), and second ROW1 is positioned at directly over first ROW1, program calculate as can be known that the placement coordinate of second ROW1 should be (0, D).By that analogy, the coordinate of the 3rd and the 4th ROW1 should be respectively (0,2D), (0,3D).The lower left corner coordinate of the ROW4 module after completing is (C, 4D) for (0,0) upper right corner coordinate.
Splicing generation module COL: point is placed an IO1 in (0,0), ROW4 be positioned at IO1 directly over, program calculate as can be known that the placement coordinate of ROW4 should be (0, B).The lower left corner coordinate of the COL module after completing is (C, B+4D) for (0,0) upper right corner coordinate.
Splicing generation module DEC4: point is placed a DEC1 in (0,0), and second DEC1 is positioned at directly over first DEC1, program calculate as can be known that the placement coordinate of second DEC1 should be (0, D).By that analogy, the coordinate of the 3rd and the 4th DEC1 should be respectively (0,2D), (0,3D).The lower left corner coordinate of the DEC4 module after completing is (A, 4D) for (0,0) upper right corner coordinate.
Splicing generation module MID: point is placed a CTRL in (0,0), DEC4 be positioned at CTRL directly over, program calculate as can be known that the placement coordinate of DEC4 should be (0, B).The lower left corner coordinate of the MID module after completing is (A, B+4D) for (0,0) upper right corner coordinate.
Splicing generates complete domain: point is placed a COL in (0,0), and second COL is positioned at the front-right of first COL, and program calculates as can be known that the placement coordinate of second COL should be (C, 0).By that analogy, since second COL from a left side be successively MID, the 3rd COL and the 4th COL backward.Their placement coordinate is respectively (2C, 0), (2C+A, 0) and (3C+A, 0).The lower left corner coordinate of the complete domain after completing is (4C+A, B+4D) for (0,0) upper right corner coordinate.
See also shown in Figure 7ly, Fig. 7 selects the schematic diagram of punch position according to text label in the domain splicing.When splicing generation module DEC4, (I1 is connected with I2 and is connected is different: first DEC1 produces WL0, and its input end I1 is connected to AN, and input end I2 is connected to BN in the input of 4 DEC1 module needs; Second DEC1 produces WL1, and its input end I1 is connected to AN, and input end I2 is connected to B; The 3rd DEC1 produces WL2, and its input end I1 is connected to A, and input end I2 is connected to BN; The 4th DEC1 produces WL3, and its input end I1 is connected to A, and input end I2 is connected to B.This different linker can be by realizing in different mark punchings.In Fig. 7, carry out punch operation on the 3rd DEC1.Due to the existence of punching mark, program only need to be known to punch in " VIA_M2M1_A " of the 3rd DEC1 and " VIA_M2M1_BN " mark and gets final product.When generating domain, program according to the set-point coordinate of the 3rd DEC1 (0,2D) and the coordinate Calculation of above two the described marks that extract go out, need the coordinate of punch position in the DEC4 module, then at this coordinate place according to content of text, create the M2 layer and get final product to the connecting hole of M1 layer.
See also shown in Figure 8ly, Fig. 8 is the schematic diagram of according to figure and text mark, port TM being programmed in the domain splicing.Need all of the port is processed after the splicing of completing complete domain.Shown in Figure 8, be that two kinds of possible Different treatments: TM of port TM are that an input port or TM fixedly connect power supply or ground.According to different conditions, program can be selected wherein a kind of processing mode automatically: when TM fixedly connect power supply, program need to be punched in " VIA_M2M1_TM_VDD " mark; When the TM solid ground, program need to be punched in " VIA_M2M1_TM_VSS " mark; When TM was an input port, program need to be located to do label " TM " and create the port designation at " PIN_M2_TM ".When generating domain, program according to the CTRL module position in the MID module and the set-point coordinate of MID module in complete domain can to calculate the set-point coordinate of CTRL in complete domain be (2C, 0), then be marked at the coordinate of CTRL as reference point according to the above that extracts, further calculate these and be marked at position in complete domain, and carry out corresponding operating.
Claims (7)
1. a domain programmed method that is used for the static RAM compiler, is characterized in that, comprises the following steps:
The first step, in elementary cell layout design process, when compiler is spliced domain, the information of needs is embedded in the elementary cell domain; Described information adds in domain with the form of mark;
Existing mark in second step, compiler identification elementary cell domain, the information that needs when splicing domain to extract;
The 3rd step, compiler find by searching or calculating the position that needs operation according to the information of extracting, and carry out the domain operation in this position.
2. a kind of domain programmed method for the static RAM compiler according to claim 1, is characterized in that, described mark comprises figure and text label, and is positioned on some auxiliary layers that do not affect normal layout design.
3. a kind of domain programmed method for the static RAM compiler according to claim 1, is characterized in that, described information comprises layout contour, punching mark and port label;
Layout contour is a pictorial symbolization, and its rule is: use an auxiliary layer to draw a rectangle as the profile of elementary cell domain; This rectangle position is by the determining positions of the domain of elementary cell;
The punching mark is a text label, and its rule is: use an auxiliary layer to do a text label in the center of needs punching; The coordinate of this label is exactly the position that needs punching; The content of text of this label has comprised the information of punching needs, and can be used for identifying different punching marks;
Port label is to be combined by a figure and a text label, and its rule is: at first use an auxiliary layer to do a text label in the position of port; The coordinate of this label is exactly the position of port; Next uses this to assist and draws layer by layer a rectangle as the shape of port, the position of the text label of marking before the profile of rectangle has comprised, and the width of rectangle equals the width of this port metal wire.
4. a kind of domain programmed method for the static RAM compiler according to claim 3, it is characterized in that, the content of text of the label of punching mark comprises three parts and is separated by underscore " _ ", first " VIA " represents that this is a punching mark, second portion represents the type of needs punching, and third part is that the title of label is used for distinguishing the different punching mark of same elementary cell domain;
The content of text of the label of port label comprises three parts and is separated by underscore " _ ", first " PIN " represents that this is a port label, second portion need to represent the metal level type of port, and third part is that the title of port is used for distinguishing the different port label of same elementary cell domain.
5. according to claim 3 or 4 described a kind of domain programmed methods for the static RAM compiler, is characterized in that, it exported as a GDSII file after completing the elementary cell layout design; Compiler directly reads in the GDSII file, find figure and the text mark that meets rule described in the first step in each elementary cell domain by scanning, and relevant information is extracted from the GDSII file: find to belong to the BORDER layer and lower left corner coordinate is (0,0) rectangle is recorded the title of the elementary cell at the coordinate in its upper right corner and place; Find to belong to TXT layer and content of text with the text label of " VIA " or " PIN " beginning, the title of the elementary cell at its coordinate, content of text and place is recorded; Find the rectangle that belongs to the TXT layer, if this rectangle has comprised that one belongs to TXT layer and content of text with the coordinate of the text label of " PIN " beginning, with the coordinate in the lower left corner and the upper right corner of rectangle, the title of the content of text of included text label and place elementary cell is recorded.
6. a kind of domain programmed method for the static RAM compiler according to claim 3 is characterized in that:
The auxiliary layer that layout contour uses is the BORDER layer; Make this rectangle lower left corner be positioned at (0,0) some during the elementary cell layout design, the coordinate in the upper right corner is exactly the layout size of this elementary cell;
The auxiliary layer that the punching mark uses is the TXT layer;
The auxiliary layer that port label is used is the TXT layer.
7. a kind of domain programmed method for the static RAM compiler according to claim 1, is characterized in that, described elementary cell domain comprises: storage unit module, word-line decoder module, data input/output module and control module.
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| 凌利军: "高性能低功耗嵌入式SRAM的设计与实现", 《中国优秀硕士学位论文全文数据库》 * |
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