CN116227407B - Method for forming module boundary of physical layout and related equipment - Google Patents
Method for forming module boundary of physical layout and related equipment Download PDFInfo
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- CN116227407B CN116227407B CN202211669139.6A CN202211669139A CN116227407B CN 116227407 B CN116227407 B CN 116227407B CN 202211669139 A CN202211669139 A CN 202211669139A CN 116227407 B CN116227407 B CN 116227407B
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
The application provides a method and related equipment for forming a module boundary of a physical layout. The method comprises the following steps: dividing a layout area of the physical layout into a plurality of grids; determining a plurality of standard units contained in a plurality of modules of the chip design corresponding to the physical layout, wherein the plurality of modules comprise target modules; inserting the standard cells into a plurality of grids of the layout area according to the positions of the standard cells on the physical layout; a first mark is given to the grids of standard cells inserted with the target module, a second mark is given to the grids of standard cells not inserted with any standard cells, and a third mark is given to the grids of standard cells inserted with other modules; filling the grids which are positioned inside the target module and marked as second marks with first marks according to the marks of each grid; merging the grids according to the mark of each grid after filling; the grid marked as the first mark and merged together is taken as the boundary of the target module.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a method for forming a module boundary of a physical layout and related devices.
Background
Electronic design automation (Electronic Design Automation, EDA for short) refers to a design method for completing the processes of functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule inspection, etc.) and the like of a very large scale integrated circuit (VLSI) chip by using Computer Aided Design (CAD) software.
In the digital chip design process, layout planning (Floorplan) is an important ring, and the quality of the layout planning directly affects the timing and wiring quality of the overall design. The user needs to analyze the layout planning of the hierarchical design of different functional modules through a layout browser window of the layout and wiring tool. Therefore, the boundary of different modules is displayed on the layout, which is beneficial to helping the user analyze the position relation among the modules and further judge the rationality of the layout planning, including the rationality of the layout. However, the inventors of the present application have found that, in the related art, there are problems such as unclear and irregular boundaries obtained by an algorithm for generating module boundaries.
Disclosure of Invention
In view of the above, the present application proposes a method and related apparatus for forming a module boundary of a physical layout, so as to solve or partially solve the above-mentioned problems.
In a first aspect of the present application, a method for forming a module boundary of a physical layout is provided, including:
dividing a layout area of the physical layout into a plurality of grids;
determining a plurality of standard units contained in a plurality of modules of the chip design corresponding to the physical layout, wherein the plurality of modules comprise target modules;
inserting the standard cells into the grids of the layout area according to the positions of the standard cells on the physical layout;
assigning a first mark to a grid of standard cells inserted with the target module, assigning a second mark to a grid of standard cells not inserted with any standard cells, and assigning a third mark to a grid of standard cells inserted with other modules;
filling a grid, which is positioned inside the target module and marked as a second mark, with the first mark according to the mark of each grid;
merging the grids according to the mark of each grid after filling;
a grid marked as the first mark and merged together is taken as a boundary of the target module.
In a second aspect of the application, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of the first aspect.
In a third aspect of the application, there is provided a non-transitory computer readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of the first aspect.
In a fourth aspect of the application, there is provided a computer program product comprising computer program instructions which, when run on a computer, cause the computer to perform the method of the first aspect.
The method and the related equipment for forming the module boundary of the physical layout can form the module boundary which is clear and regular, and improve the user experience.
Drawings
In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 shows a schematic hardware structure of an exemplary computer device according to an embodiment of the present application.
Fig. 2A shows a basic structural schematic of an EDA tool according to an embodiment of the application.
FIG. 2B illustrates a schematic diagram of the basic execution flow of one compute command of an EDA tool, according to an embodiment of the present application.
Fig. 3 shows a flow diagram of an exemplary method provided by an embodiment of the application.
Fig. 4A shows a schematic diagram of an exemplary layout area according to an embodiment of the present application.
Fig. 4B shows a schematic diagram of inserting standard cells in a layout area according to an embodiment of the present application.
Fig. 4C shows a schematic diagram of a layout area 410 of an insertion mark according to an embodiment of the present application.
Fig. 4D shows a schematic diagram after filling the first mark in the first direction according to an embodiment of the present application.
Fig. 4E shows a schematic diagram after filling the first mark in the second direction according to an embodiment of the application.
Fig. 4F shows a schematic diagram after merging grids in a first direction according to an embodiment of the present application.
Fig. 4G shows a schematic diagram after merging the grids in the second direction according to an embodiment of the present application.
Fig. 4H shows another schematic diagram after merging the grids in the second direction according to an embodiment of the present application.
Fig. 4I shows another schematic diagram after merging the grids in the second direction according to an embodiment of the present application.
Fig. 4J shows another schematic diagram after merging the grids in the second direction according to an embodiment of the present application.
Fig. 5A shows an effect diagram of a module boundary generated using the related art.
Fig. 5B shows a schematic view of the effect of the module boundary generated by the method according to the embodiment of the present application.
Detailed Description
The present application will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Fig. 1 shows a schematic structural diagram of a computer device 100 according to an embodiment of the present application. The computer device 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the device via a bus 110.
The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.
The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in fig. 1, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) as well as data to be processed. The processor 102 may also access stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile storage or nonvolatile storage. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.
The network interface 106 may be configured to provide communication with other external devices to the computer device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.
Peripheral interface 108 may be configured to connect computer apparatus 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.
Bus 110 may be configured to transfer information between the various components of computer device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.
It should be noted that although the above-described device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the device may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary for implementing the embodiments of the present application, and not all the components shown in the drawings.
Fig. 2A shows a basic structural schematic of an EDA tool 200 according to an embodiment of the application.
As shown in fig. 2A, the user portion is above the dashed line; below the dashed line is an EDA tool 200, which EDA tool 200 may be implemented by the apparatus 100 shown in fig. 1. In some embodiments, the EDA tool 200 may be implemented as EDA software. More specifically, the EDA tool 200 may be software that performs Placement (Placement) and Routing (Routing) based on a chip design. Simulation tool 200 can include a Tcl command (or graphical/window interface) module 204, computing modules (e.g., a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc.), and a database system 212. The user 202 may operate the EDA tool 200 by entering relevant commands in a Tcl command (or graphical/window interface) module 204.
Tcl command module 204 functions primarily as message passing or command passing. Tcl command module 204 may read instructions entered by user 202 into simulation tool 200 and may assign and pass to the corresponding computing module to perform specific tasks based on the specific content of the instructions.
The calculation modules may be divided into, for example, a plane calculation module 206, a Route calculation module 208, an Optimization calculation module 210, and the like, according to the calculation tasks. The space calculation module 206 may be configured to calculate a reasonable placement position for all components, the Route calculation module 208 may be configured to calculate a reasonable wire connection manner between components, and the Optimization calculation module 210 may be configured to optimize the placement position and the wire connection manner between components. The computation of these computation modules may be performed, for example, in the processor 102 of fig. 1.
Database system 212 may be used to fully record, store, etc., all information (e.g., location, orientation, size, configuration, wire connection, etc.) of the chip being emulated or designed. Such information may be stored, for example, in memory 104 of fig. 1.
FIG. 2B illustrates a basic execution flow 220 of one compute command of the EDA tool 200, according to an embodiment of the present application. As shown in FIG. 2B, at step 222, user 202 may issue a command (e.g., a do_place command) to the EDA tool 200 through a command interface or Graphical User Interface (GUI) provided by the Tcl command module 204. Tcl command module 204 then parses this command and distributes it to the corresponding computing module (e.g., space computing module 206) at step 224. In step 226, each computing module performs the specific calculations that each needs to perform. During this time, each computing module needs to (at high frequency, repeatedly) retrieve the data in database system 212 to perform the computation, as shown in step 228. After the calculations are completed, each calculation module may write the calculation results to database system 212 and return the calculation results to Tcl command module 204, as shown in step 230. At step 232, the tcl command module 204 returns the calculation result to the user 202 via a command interface or Graphical User Interface (GUI), and the EDA tool 200 ends the processing of a calculation command. In step 234, the user may evaluate based on the calculation and then determine the next plan.
Layout planning (Floorplan), generally refers to placing macro cells (hard macro) into a design and meeting the requirements of a subsequent standard cell (standard cell) layout. Generalized layout planning also includes designing aspect ratios of Die (Die), placing I/O pads, pure physical unit (Welltap, endcap) insertion, power grid planning, etc.
In the digital chip design process, layout planning (Floorplan) is an important ring, and the quality of the layout planning directly affects the timing and wiring quality of the overall design. The user needs to analyze the layout planning of the hierarchical design of different functional modules through a layout browser window of the layout and wiring tool. The hierarchical design divides the whole design task into a plurality of sub-modules according to functions so as to realize and verify respectively, and the difficulty of design and simulation verification is greatly reduced. Meanwhile, the layout and wiring tool displays the boundaries of the design modules in the layout browser, so that the user is helped to analyze the position relationship among the modules by displaying the boundaries of different modules on the layout, and the rationality of layout planning, including the rationality of layout, is further judged.
Along with the continuous increase of the scale of chip design, the single module of hierarchical design has the following characteristics:
1) Standard cells (standard cells) and macro cells (hard macro) are increasingly involved;
2) The distribution on the physical layout is also more and more complex;
3) The different modules are mutually inserted, and the boundary is more and more complex.
In addition, the layout of hierarchically designed modules also follows some of the following features:
1) Standard cells (macro cells) are all orthogonal rectangles;
2) Standard cells (macro cells) are all aligned in a particular row after layout is completed, with no intersection coverage.
There are many ways to determine the boundaries of a hierarchically designed module with the above features.
One is to use convex hull method or concave hull method to calculate the boundary. The disadvantage of this approach is that the boundaries obtained with this approach are not orthogonal polygons and the contours are relatively coarse.
Another approach is to employ the Amoeba algorithm. The disadvantage of this approach is that the computation speed is slow and it is not possible to handle cases where standard cells overlap and are not aligned with rows.
Yet another approach is a progressive scanning algorithm. A disadvantage of this approach is that the display is too rough to represent a good indication of module interpenetration.
In view of this, the embodiment of the application provides a method for forming a module boundary of a physical layout, which combines a raster method to improve the sampling speed and combines a scan line algorithm to ensure the drawing precision.
Fig. 3 shows a flow diagram of an exemplary method 300 provided by an embodiment of the application. The method 300 may be implemented by the computer device 100 of fig. 1 and may be implemented as part of the functionality of the EDA tool 200 of fig. 2A. As shown in fig. 3, the method 300 may further include the following steps.
In step 302, a layout area of the physical layout is divided into a plurality of grids (bins).
Fig. 4A shows a schematic diagram of an exemplary layout area 400 according to an embodiment of the application.
As shown in fig. 4A, the layout area 400 is divided into 6×6 grids.
The size of the grids determines the sampling accuracy, and optionally, the minimum height (row) and the minimum width (site) of Standard cells (Standard cells) in a plurality of modules designed according to the chip corresponding to the physical layout can be used as the size of each grid. Optionally, the entire layout area 400 (grid matrix) covers the size of the chip design corresponding to the physical layout.
In step 304, a plurality of standard cells included in a plurality of modules of the chip design corresponding to the physical layout are determined, where the plurality of modules includes a target module. Alternatively, the plurality of standard cells corresponding to the physical layout may be determined by traversing all standard cells of all modules included in the chip design.
In step 306, the plurality of standard cells are inserted into the plurality of grids of the layout area according to their locations on the physical layout. The position of each module of the chip design on the physical layout can be determined according to the layout planning result.
Fig. 4B shows a schematic diagram of inserting standard cells in a layout area according to an embodiment of the present application.
As shown in FIG. 4B, taking the example of a target module currently being processed, a standard cell 402 of the target module, a standard cell 406 of a non-target module (i.e., other modules in the chip design than the target module) and a blank grid without any intervening standard cells are shown in FIG. 4B.
In step 308, a first mark is assigned to the grid of standard cells in which the target module is inserted, a second mark is assigned to the grid in which no standard cells are inserted, and a third mark is assigned to the grid of standard cells in which other modules are inserted.
Fig. 4C shows a schematic diagram of a layout area 410 of an insertion mark according to an embodiment of the present application.
As shown in fig. 4C, a grid containing standard cells of the target module may be marked as a first mark (e.g., 1). Alternatively, in marking the first mark, whenever a standard cell of the target module occupies a portion of the grid, the grid is marked as the first mark regardless of the size of the occupied area. A grid containing only standard cells of non-target modules may then be marked as a third mark (e.g., -1), i.e., when one grid includes both standard cells of target modules and standard cells of non-target modules, then the grid is marked as a first mark instead of a third mark. Finally, the tag that does not contain any standard cells is referred to as a second tag (e.g., 0).
In this way, the target module currently being processed is distinguished from other modules and the blank area by three markers for subsequent processing.
In step 310, the grids that are marked as second markers inside the target module are filled with the first markers according to the markers of each grid. Since the grid marked as the second mark corresponds to a blank area, which is understood to be part of the target module when it is located inside the target module when it borders the target module, the first mark corresponding to the target module is filled.
As an alternative embodiment, the filling may be performed row by row along the first direction of the layout area; then filling line by line along a second direction of the layout area; wherein the first direction and the second direction intersect. In this way, the filling is performed line by line from two directions, and the grids marked as the second marks in the target modules can be fully found, so that the filling is completed, and the inter-module penetration area displayed by the blank area is not easy to appear in the finally formed boundary.
In some embodiments, the filling in the first direction of the layout area (e.g., filling in line from bottom to top) line by line may include:
for each row of grids, finding a first grid marked as a first mark (e.g., 1) along the second direction (e.g., from left to right);
searching in the second direction from the first grid marked as first mark;
the searched grid marked as the second mark (e.g., -0) is filled with the first mark until a grid marked as the third mark (e.g., -1) is encountered.
If the row of grids has not been searched for when encountering a grid marked with a third mark (e.g., -1), the above steps continue to be repeated until all "internal" blank grids of the row have been filled. Filling of the next row then begins until filling of all rows is completed, as shown in fig. 4D.
In some embodiments, row-by-row filling (e.g., column-by-column filling from left to right) along a second direction of the layout area includes:
for each row of grids, finding a first grid marked as a first mark (e.g., 1) along the first direction (e.g., from bottom to top);
searching in the first direction from the first grid marked as first mark;
the searched grid marked as the second mark (e.g., -0) is filled with the first mark until a grid marked as the third mark (e.g., -1) is encountered.
If the row of grids has not been searched for when encountering a grid marked with a third mark (e.g., -1), the above steps continue to be repeated until all "internal" blank grids of the row have been filled. Filling of the next row then begins until filling of all rows is completed, as shown in fig. 4E.
At step 312, the grids are merged according to the labels of each grid after the filling process to obtain the boundary of the target module.
Optionally, merging the grids may comprise two sub-steps, merging the grids and merging the contours.
In some embodiments, merging the grids may further include merging the grids row by row (e.g., merging row by row from bottom to top) along a first direction, and may include:
for each row of grids, find the first grid marked as the first mark (e.g., 1) along the second direction (e.g., from left to right);
searching in the second direction from the first grid marked as first mark;
the searched grids marked as first mark are merged until encountering a grid marked as third mark (e.g., -1), thus forming a large grid of 1 x N.
If the row of grids has not been searched for when encountering a grid marked with a third mark (e.g., -1), the above steps continue to be repeated until all grids marked with the first mark of the row have been merged. Then, the next row of grids starts to be merged until the grid merging of all rows is completed, forming large grids of 1×n1, 1×n2, 1×n3 …, as shown in fig. 4F.
The contours may then be merged. Alternatively, the row-by-row merged grids may be merged into orthogonal polygons along a first direction (e.g., from bottom to top).
In some embodiments, a linked list of orthogonal polygons may be created to store orthogonal polygons that have completed contour merging. In the initial state, a rectangle composed of the row-by-row merged grid in the first row may be stored therein.
As shown in fig. 4F, from the first row, the row-by-row combined grid may be formed into a plurality of orthogonal rectangles, then traversing the rectangle corresponding to the second row of combined grid, combining with the rectangle in the orthogonal polygon linked list of the first row, and replacing the original rectangle in the orthogonal polygon linked list with the polygon obtained after combining. And by analogy, knowing the rectangle formed by traversing all the grids after merging row by row.
Specifically, polygon merging is divided into the following cases:
1) If the current rectangle does not intersect the uppermost edge of all the previous polygons, the rectangle is added to the orthogonal polygon linked list.
2) If the current rectangle intersects an uppermost edge of some of the preceding polygons, the rectangle is merged with these orthogonal polygons into a new orthogonal polygon, as shown in fig. 4G and 4H. The merged orthogonal polygon may then be deleted from the linked list and the new orthogonal polygon added.
3) If the current rectangle intersects the uppermost edges of the previous polygon or polygons, the rectangle is merged with the orthogonal polygons into a new orthogonal polygon and a hole is formed, as shown in fig. 4I. The merged orthogonal polygon may then be deleted from the linked list and the new orthogonal polygon added.
4) After all rectangles of a row are merged, the orthogonal polygons in the original linked list which do not participate in merging are deleted.
The following describes an example of merging the first row and the second row.
Optionally, merging the row-by-row merged grids into orthogonal polygons along a second direction, including:
creating an orthogonal polygon linked list;
storing a rectangle formed by grids combined row by row in a first row in the orthogonal polygon linked list;
traversing a rectangle formed by the grids after row-by-row combination of the second row:
adding the current rectangle to the orthogonal polygon list in response to determining that the current rectangle does not intersect at least one edge of all rectangles in the first row;
in response to determining that the current rectangle intersects an edge of at least one rectangle in the first row, merging the current rectangle and the at least one rectangle into an orthogonal polygon, deleting the merged rectangle from the orthogonal polygon linked list, and adding the orthogonal polygon to the orthogonal polygon linked list;
in response to determining that the current rectangle intersects a plurality of edges of at least one rectangle ahead, merging the current rectangle and the at least one rectangle into an orthogonal polygon, forming a hole, deleting the merged rectangle from the orthogonal polygon linked list, and adding the orthogonal polygon into the orthogonal polygon linked list;
and after all rectangles formed by the grids after the row-by-row combination of the second row are combined, deleting the rectangles which do not participate in the combination in the orthogonal polygon linked list.
The third row merge may then begin until all rows have been merged, as shown in FIG. 4J.
At this time, the orthogonal polygon stored in the orthogonal polygon chain table is the boundary of the target module. Thus, at step 314, the grid marked as the first mark and merged together is taken as the boundary of the target module.
The generation of the module boundary is completed for a single module (target module), at this time, the information of the boundary can be saved, and the boundary can be directly called when the boundary of the module is displayed later, so that the calculation is prevented from being performed again when the boundary is displayed each time, and the processing efficiency is improved.
Then, in some embodiments, another module in the chip design may be selected as the target module and processed to derive its boundaries in accordance with the foregoing steps. And so on until the creation of the boundaries of all the modules of the chip design is completed.
In some embodiments, after obtaining the boundaries of the module, the method 300 may further comprise: and displaying the physical layout comprising the boundaries of the target modules (or all the modules of the chip design), thereby being beneficial to helping a user analyze the position relationship among the modules and further judging the rationality of the layout, including the rationality of the layout by displaying the boundaries of different modules on the layout.
From the above embodiments, it can be seen that the embodiments of the present application provide a layout display method for a hierarchical design module based on a grid, where the method combines a grid method to increase a sampling speed and combines a scan line algorithm to ensure drawing accuracy.
Fig. 5A shows an effect diagram of a module boundary generated using the related art. Fig. 5B shows a schematic view of the effect of the module boundary generated by the method according to the embodiment of the present application.
Comparing fig. 5A and fig. 5B, it can be seen that, compared with the related art, the module boundaries generated by the method provided by the embodiment of the present application are more clearly distributed on the physical layout, and the module boundaries are not substantially overlapped and interpenetrated with each other, which is favorable for helping the user analyze the positional relationship between the modules, and further judging the rationality of the layout plan, including the rationality of the layout.
It should be noted that, the method of the embodiment of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of an embodiment of the present application, the devices interacting with each other to accomplish the method.
It should be noted that the foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method 300 according to any of the embodiments above, corresponding to the method according to any of the embodiments above.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The storage medium of the foregoing embodiments stores computer instructions for causing the computer to perform the method 300 as described in any of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Based on the same inventive concept, the present application also provides a computer program product, corresponding to any of the embodiment methods 300 described above, comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the described method 300. Corresponding to the execution bodies corresponding to the steps in the embodiments of the method 300, the processor executing the corresponding step may belong to the corresponding execution body.
The computer program product of the above embodiment is configured to cause a processor to perform the method 300 of any of the above embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.
Claims (8)
1. A method of forming a module boundary of a physical layout, comprising:
dividing a layout area of the physical layout into a plurality of grids;
determining a plurality of standard units contained in a plurality of modules of the chip design corresponding to the physical layout, wherein the plurality of modules comprise target modules;
inserting the standard cells into the grids of the layout area according to the positions of the standard cells on the physical layout;
assigning a first mark to a grid of standard cells inserted with the target module, assigning a second mark to a grid of standard cells not inserted with any standard cells, and assigning a third mark to a grid of standard cells inserted with other modules;
filling a grid, which is positioned inside the target module and marked as a second mark, with the first mark according to the mark of each grid;
merging the grids according to the mark of each grid after filling;
taking a grid marked as the first mark and combined together as a boundary of the target module;
wherein merging the grids according to the mark of each grid after the filling process includes:
the grid is combined row by row along a first direction, and the method specifically comprises the following steps:
for each row of grids, finding a first grid marked as a first mark along a second direction;
searching in the second direction from the first grid marked as first mark;
merging the searched grids marked as the first mark until encountering a grid marked as the third mark;
merging the grids after the row-by-row merging into an orthogonal polygon along a first direction;
wherein the first direction and the second direction are perpendicular to each other.
2. The method of claim 1, wherein populating the grid marked as a second marker inside the target module with the first marker according to the markers of each grid, comprising:
filling line by line along a first direction of the layout area;
and filling the layout area row by row along a second direction of the layout area.
3. The method of claim 2, wherein filling row-by-row along a first direction of the layout area comprises:
for each row of grids, finding a first grid marked as a first mark along the second direction;
searching in the second direction from the first grid marked as first mark;
filling the searched grids marked as the second marks with the first marks until encountering the grids marked as the third marks.
4. The method of claim 2, wherein filling row-by-row along the second direction of the layout area comprises:
for each row of grids, finding a first grid marked as a first mark along the first direction;
searching in the first direction from the first grid marked as first mark;
filling the searched grids marked as the second marks with the first marks until encountering the grids marked as the third marks.
5. The method of claim 1, wherein merging the row-by-row merged grids into orthogonal polygons along a second direction comprises:
creating an orthogonal polygon linked list;
storing a rectangle formed by grids combined row by row in a first row in the orthogonal polygon linked list;
traversing a rectangle formed by the grids after row-by-row combination of the second row:
adding the current rectangle to the orthogonal polygon list in response to determining that the current rectangle does not intersect at least one edge of all rectangles in the first row;
in response to determining that the current rectangle intersects an edge of at least one rectangle in the first row, merging the current rectangle and the at least one rectangle into an orthogonal polygon, deleting the merged rectangle from the orthogonal polygon linked list, and adding the orthogonal polygon to the orthogonal polygon linked list;
in response to determining that the current rectangle intersects a plurality of edges of at least one rectangle ahead, merging the current rectangle and the at least one rectangle into an orthogonal polygon, forming a hole, deleting the merged rectangle from the orthogonal polygon linked list, and adding the orthogonal polygon into the orthogonal polygon linked list;
and after all rectangles formed by the grids after the row-by-row combination of the second row are combined, deleting the rectangles which do not participate in the combination in the orthogonal polygon linked list.
6. The method of claim 1, wherein after bounding the grid marked as the first mark and merged together as the target module, the method further comprises:
and displaying the physical layout including the boundary of the target module.
7. A computer device comprising one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of any of claims 1-6.
8. A non-transitory computer readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of any of claims 1-6.
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| CN117875261B (en) * | 2024-03-13 | 2024-05-24 | 弈芯科技(杭州)有限公司 | Verification method and device for rectangular inclusion rule in integrated circuit layout verification |
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