CN116911246B - Wiring planning method for chip design and related equipment - Google Patents
Wiring planning method for chip design and related equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3947—Routing global
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T17/00—Three dimensional [3D] modelling, e.g. data description of 3D objects
- G06T17/20—Finite element generation, e.g. wire-frame surface description, tesselation
Abstract
The application provides a wiring planning method and related equipment for chip design, wherein the method comprises the following steps: acquiring a chip design layout; determining all winding tracks of any winding layer in the chip design layout, and assigning a first value to each winding track; determining the position of at least one winding obstacle in any winding layer according to the chip design layout; responsive to the position at least partially covering any one of the winding tracks, adjusting a corresponding assignment for the winding track to a second value; and counting the winding track assigned to the second value, and outputting a counting result to plan the wiring of the chip design according to the counting result.
Description
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a wiring planning method and related devices for chip design.
Background
Electronic design automation (Electronic Design Automation, EDA for short) refers to a design method for completing the processes of functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule inspection, etc.) and the like of a very large scale integrated circuit (VLSI) chip by using Computer Aided Design (CAD) software.
Among these, wiring is an important physical implementation task after the integration of layout and clock tree, and due to the complexity of the wiring process, wiring is generally divided into global wiring and detailed wiring in the implementation process. An important initial step in the global routing phase is the need to calculate the occupancy of the winding track (track) by various obstacles. However, in the related art, the calculation method of the obstacle to the winding resource is only to calculate the winding track occupied by each obstacle respectively, and then accumulate. The processing mode can cause the multi-buckling phenomenon of the winding track in many scenes, so that the cost of subsequent adjustment is increased, and the overall efficiency is reduced.
Disclosure of Invention
In view of the above, the present application provides a wiring planning method and related apparatus for chip design to solve or partially solve the above-mentioned problems.
Based on the above object, the present application provides a wiring planning method for chip design, comprising:
acquiring a chip design layout;
determining all winding tracks of any winding layer in the chip design layout, and assigning a first value to each winding track;
determining the position of at least one winding obstacle in any winding layer according to the chip design layout;
responsive to the position at least partially covering any one of the winding tracks, adjusting a corresponding assignment for the winding track to a second value;
and counting the winding track assigned to the second value, and outputting a counting result to plan the wiring of the chip design according to the counting result.
In a second aspect of the application, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of the first aspect.
In a third aspect of the application, there is provided a non-transitory computer readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of the first aspect.
The wiring planning method and the related equipment for chip design provided by the application are characterized in that the assignment of a first value is firstly carried out on all winding tracks of a winding layer, then whether any winding track is covered or partially covered is determined according to the position of a winding barrier in the winding layer of the layer, the assignment of the winding track which is at least partially covered is adjusted to a second value, and finally the occupation condition of winding resources of the winding layer of the layer is determined through counting the winding track which is assigned to the second value. In this way, no matter the conditions of overlapping or mutual shielding exist between winding obstacles, statistics is carried out only according to the assignment condition of a winding track, even if the assignment of one winding track is adjusted for a plurality of times, the adjustment result is that the assignment is adjusted to be a second value, and the condition of repeated calculation cannot occur, so that the phenomenon of multi-buckling is avoided, the cost of subsequent adjustment is reduced, and the overall efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only embodiments of the present application and that other drawings can be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 illustrates a schematic hardware architecture of an exemplary computer device provided by an embodiment of the present application;
FIG. 2 shows a basic structural schematic of an EDA tool according to an embodiment of the present application;
FIG. 3 illustrates a schematic diagram of the basic execution flow of one compute command of an EDA tool, according to an embodiment of the present application;
fig. 4A is a schematic view of a scenario in which a winding obstacle occupies a winding track in the related art according to an embodiment of the present application;
fig. 4B is a schematic view of a scenario in which another winding obstacle occupies a winding track in the related art according to an embodiment of the present application;
FIG. 5 shows a flow diagram of an exemplary method provided by an embodiment of the present application;
FIG. 6 shows a schematic diagram of a two-dimensional global grid and a three-dimensional global grid provided by an embodiment of the present application;
FIG. 7 illustrates an initial winding track (track) of the transverse winding layer and the longitudinal winding layer provided by an embodiment of the present application;
FIG. 8 is a diagram of an exemplary method for setting a bitmap (bitmap) for a winding layer according to an embodiment of the present application;
FIG. 9 is a diagram illustrating an exemplary method for using a bitmap (bitmap) for blocking statistics according to an embodiment of the present application;
fig. 10 shows a schematic flow chart of a specific occupancy determination procedure according to an exemplary method of the present application according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the present specification will be further described in detail below with reference to the accompanying drawings.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Fig. 1 shows a schematic structural diagram of a computer device 100 according to an embodiment of the present application. The computer device 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the device via a bus 110.
The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.
The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in fig. 1, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) as well as data to be processed. The processor 102 may also access stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile storage or nonvolatile storage. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.
The network interface 106 may be configured to provide communication with other external devices to the computer device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.
Peripheral interface 108 may be configured to connect computer apparatus 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.
Bus 110 may be configured to transfer information between the various components of computer device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.
It should be noted that although the above-described device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the device may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary for implementing the embodiments of the present application, and not all the components shown in the drawings.
Fig. 2 shows a basic structural schematic of an EDA tool 200 according to an embodiment of the application.
As shown in fig. 2, the user portion is above the dashed line; below the dashed line is an EDA tool 200, which EDA tool 200 may be implemented by the apparatus 100 shown in fig. 1. In some embodiments, the EDA tool 200 may be implemented as EDA software. More specifically, the EDA tool 200 may be software that performs Placement (Placement) and Routing (Routing) based on a chip design. Simulation tool 200 can include a Tcl command (or graphical/window interface) module 204, computing modules (e.g., a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc.), and a database system 212. The user 202 may operate the EDA tool 200 by entering relevant commands in a Tcl command (or graphical/window interface) module 204.
Tcl command module 204 functions primarily as message passing or command passing. Tcl command module 204 may read instructions entered by user 202 into simulation tool 200 and may assign and pass to the corresponding computing module to perform specific tasks based on the specific content of the instructions.
The calculation modules may be divided into, for example, a plane calculation module 206, a Route calculation module 208, an Optimization calculation module 210, and the like, according to the calculation tasks. The space calculation module 206 may be configured to calculate a reasonable placement position for all components, the Route calculation module 208 may be configured to calculate a reasonable wire connection manner between components, and the Optimization calculation module 210 may be configured to optimize the placement position and the wire connection manner between components. The computation of these computation modules may be performed, for example, in the processor 102 of fig. 1.
Database system 212 may be used to fully record, store, etc., all information (e.g., location, orientation, size, configuration, wire connection, etc.) of the chip being emulated or designed. Such information may be stored, for example, in memory 104 of fig. 1.
FIG. 3 illustrates a basic execution flow 300 of one compute command of the EDA tool 200, according to an embodiment of the present application. As shown in FIG. 3, at step 302, a user 202 may issue a command (e.g., a do_place command) to the EDA tool 200 through a command interface or Graphical User Interface (GUI) provided by the Tcl command module 204. Tcl command module 204 then parses this command and distributes it to the corresponding computing module (e.g., space computing module 206) at step 304. In step 306, each computing module performs the specific calculations that each needs to perform. During this time, each computing module needs to (at high frequency, repeatedly) retrieve the data in database system 212 to perform the computation, as shown in step 308. After the calculations are completed, each calculation module may write the calculation results to database system 212 and return the calculation results to Tcl command module 204, as shown in step 310. At step 312, the tcl command module 204 returns the calculation result to the user 202 via a command interface or Graphical User Interface (GUI), and the EDA tool 200 ends the processing of a calculation command. At step 314, the user may evaluate based on the calculation and then determine the next plan.
In the related art, the design of digital integrated circuits is an engineering approach from circuit theory to product implementation, and integrated circuit designs are strongly dependent on EDA tools. EDA tools are used as basic tools for chip design, and cover the whole flow of chip design, including functional design, synthesis, verification, physical design, and the like. While physical design is used as a back-end design, an actual layout needs to be implemented, where an important element of physical design is placement & routing.
The main task of the wiring is to interconnect the modules, standard units, input/output interface units and other elements distributed in the chip core according to the logic relationship, so that not only is the interconnection of all logic signals between the modules, standard units, input/output interface units and other elements completed in a percentage manner, but also the interconnection is optimized for meeting various constraint conditions. Because of the complexity of the wiring process, the wiring is generally divided into global wiring and detailed wiring in the implementation process, and the global wiring is used for preparing the detailed wiring and making a specific plan for the detailed wiring. The global wiring has the advantages of high speed, short time and convergence acceleration, and is used for planning the final detailed wiring with long time. If the global wiring finds out a problem, the engineer can solve the adjustment in time without taking a long time to do final wiring and other subsequent work.
In the whole chip, various obstacles such as pins (pin shapes) of various units, internal winding obstacles, top ports (top ports), previously wound wires and winding obstacles generated by engineers occupy the winding track. How to calculate the occupation of the resources rapidly and accurately affects the winding result and the accuracy of the global wiring.
However, when calculating the occupancy of winding resources by an obstacle, it is generally used to see that a single obstacle occupies several winding tracks in the global grid and then accumulate. However, such a calculation method has a problem of multi-button resources. As shown in fig. 4A and 4B, A, B, C and D represent winding obstacles, and the broken line represents a winding track. According to a common statistical manner, the winding tracks occupied by a and B and occupied by C and D are respectively determined, and it can be seen from the figure that a and B occupy 2 winding track resources, C occupies 1 winding track resource, and D occupies 3 winding track resources, so that the accumulation results in the examples of fig. 4A and fig. 4B occupy 4 winding track resources, but from the figure, only 3 winding track resources are actually occupied in both the two figures, which causes the multi-buckling phenomenon of the winding tracks.
Meanwhile, even though the recognition of the above-described cases shown in fig. 4A and 4B is increased by improving an algorithm, such a method currently causes a decrease in overall efficiency and increases time costs.
In view of this, the present application proposes a wiring planning scheme for chip design, which performs assignment of a first value to all winding tracks of a winding layer, then determines whether any winding track is covered or partially covered according to the position of a winding obstacle in the winding layer of the layer, adjusts the assignment of the winding track which is at least partially covered to a second value, and finally determines the occupation condition of winding resources of the winding layer of the layer by counting the winding track whose assignment is the second value. In this way, no matter the conditions of overlapping or mutual shielding exist between winding obstacles, statistics is carried out only according to the assignment condition of a winding track, even if the assignment of one winding track is adjusted for a plurality of times, the adjustment result is that the assignment is adjusted to be a second value, and the condition of repeated calculation cannot occur, so that the phenomenon of multi-buckling is avoided, the cost of subsequent adjustment is reduced, and the overall efficiency is improved.
Fig. 5 shows a flow diagram of an exemplary method 500 provided by an embodiment of the application. The method 500 may be implemented by the computer device 100 of fig. 1 and may be implemented as part of the functionality of the EDA tool 200 of fig. 2. As shown in fig. 5, the method 500 may further include the following steps.
Step 502, obtaining a chip design layout.
Generally, a chip design layout includes each layer of structures for chip processing, such as a specific transistor layout, wiring, routing, via-to-via connection locations, and so on. According to the chip design layout, a chip processing service provider can directly operate and carry out batch processing production of chips. Furthermore, the chip design layout is drawn step by step, and simultaneously, along with various optimizations, the true chip design layout is finally completed. In the early stage of the chip design layout, only the functional information of the hierarchy may be indicated on the chip design layout, for example, a certain layer is a winding layer, a certain layer is an insulating layer, and the like; or only the functional elements are arranged, and the information such as the position, the size and the like of each functional element is marked. And then performing one-step design and optimization by using EDA tools and the like, and finally forming the complete version of the chip design layout. In this step, since the wiring planning procedure is involved, the chip design layout may be a more initial version, on which only earlier data such as chip hierarchical relationships, hierarchical functions, element design positions, etc. are provided. In a specific application scenario, initial data information such as a hierarchical structure, element positions and the like can be obtained through a DEF (Design Exchange File, physical information of a design library) file and/or an LEF (Library Exchange File, physical information of a process library) file of a chip design layout.
Thereafter, in this step, the chip design layout may be local (e.g., dividing the entire design layout into a large number of sub-regions) or may be global.
And 504, determining all winding tracks of any winding layer in the chip design layout, and assigning a first value to each winding track.
In this step, after obtaining the data such as the initial component layout and the hierarchical structure of the chip design layout, the winding layer in the chip design layout can be found out first, and the winding layer is the hierarchical structure for the chip routing and winding. When the wiring planning of the winding layer is performed, the winding tracks are planned in advance according to the design rule, and are generally and uniformly distributed in the winding layer transversely or longitudinally, and when the chip layout is performed, the number of the winding tracks is generally represented by using winding resources (Routing resources), so that the number of the available winding tracks in one winding layer is represented.
In some embodiments, the winding tracks of a layer of winding layers can be directly set, or the global grid can be generated first, and then the global grid is used for setting the winding tracks. As shown in fig. 6, a two-dimensional global grid and a three-dimensional global grid are illustrated. Wherein, global grid (Global Cell): the global wiring stage divides the whole winding layer chip area according to a regular grid to obtain a minimum unit grid. Each winding layer is provided with a two-dimensional global grid, and the grids of all the winding layers are combined to form a three-dimensional global grid. Thereafter, as shown in fig. 7, an initial winding track (track) of the transverse winding layer and the longitudinal winding layer is shown, and a solid line in the transverse or longitudinal direction is the winding track. The proposed track number corresponds to the grid of a global grid according to the chip design rule, and the proposed track number can be set as the maximum number of winding tracks allowed in the grid. Then, since each winding layer generally has a fixed wiring direction or a track direction, i.e. a transverse wiring or a longitudinal wiring, for a winding layer with a transverse track direction, the winding layers can be uniformly arranged according to the total number of winding tracks of a grid of any column (as shown in fig. 7, since the winding tracks are generally represented by straight line segments, the statistics result of the winding tracks of any column is the same); similarly, for the winding layers with the longitudinal track direction, the winding layers can be uniformly distributed according to the total number of winding tracks of any row of grids. That is, in some embodiments, the determining all winding tracks of any one winding layer in the chip design layout includes: global meshing is carried out on any layer of winding layers, the maximum number of winding tracks allowed in each mesh is determined, and the number of winding tracks of any row or any column of mesh is uniformly distributed according to the maximum number of winding tracks, so that all winding tracks of any layer of winding layers are determined. In some embodiments, the uniformly arranging the number of winding tracks of the grid of any row or any column according to the maximum number of winding tracks includes: determining the track direction of any winding layer; responding to the track direction being transverse, uniformly distributing the number of the winding tracks of the grid of any column according to the maximum number of the winding tracks; and responding to the track direction being longitudinal, uniformly distributing the number of the winding tracks of the grid of any row according to the maximum number of the winding tracks.
Then, in this step, each winding track in this winding layer is required to perform the assignment of the first value, that is, perform the initial assignment. For example, it may initially assign each winding track a value of 0, where 0 is the first value.
In some embodiments, each of the wire-wound tracks may be assigned a value by way of marking, tagging, or the like. In other embodiments, for convenience of management, assignment processing may be performed using as small resources as possible, where assignment and management may be performed using bit map (bitmap). As shown in fig. 8, for any winding layer, a bit chart with a corresponding length may be set corresponding to the number of winding tracks, one winding track corresponds to a cell (i.e., a bit cell) in one bit chart, when setting the bit chart, a certain side of the winding layer may be specified as a starting point, and a corresponding relationship between the winding tracks and the bit cell may be sequentially established, i.e., a first winding track corresponds to a first bit cell, a second winding track corresponds to a second bit cell, and so on. In this way, the bit chart is bit-level table data, so that the occupied resources are very small, the storage space can be effectively utilized, and the reading efficiency of the bit chart is effectively improved. That is, in some embodiments, the assigning a first value to each of the winding tracks includes: generating a bitmap table with corresponding length according to the total number of winding tracks of any winding layer; wherein each bit cell in the bit map corresponds to one of the winding tracks; and carrying out assignment of the first value on each bit cell of the bitmap table.
And step 506, determining the position of at least one winding obstacle in any winding layer according to the chip design layout.
In this step, the design of the element, the port position, or some support structure is generally already completed in the chip design layout required for wiring planning. Therefore, the winding obstacle of any winding layer can be determined according to the chip design layout at the moment.
The winding Obstacle (OBS) herein refers to pins (pin shapes) of various units as well as internal winding obstacles (elements or ports integrally passing through the winding layer), top ports (top ports for connection to external devices or structures), previously wound wire mesh, and engineer generated, custom winding obstacles. They are distributed on each winding layer and occupy the winding resources of global wiring on the corresponding winding layer. Meanwhile, a plurality of winding layers are generally arranged in a chip structure, different chip elements or ports are different in arrangement positions and levels, pins of the chip elements or ports can be connected with different winding layers, the pins are generally fixed in structure, the positions of the pins are difficult to change, the pins can be considered as barriers when wiring, and meanwhile, the chip elements or port bodies can penetrate through one or more winding layers, and further the bodies can be barriers of some winding layers.
The specific position, the size and other data of the barriers are generally recorded in the chip design layout, so that the specific positions of the barriers in the winding layer can be determined according to the chip design layout.
And step 508, adjusting a corresponding assignment of the winding track to a second value in response to the position at least partially covering any one of the winding tracks.
In this step, after the winding tracks of any winding layer and the positions of the obstacles are determined, a determination of the correlation between the two, i.e., a determination of whether the obstacles cover or partially cover the winding tracks, is made.
The determination mode can be from each obstacle or from each winding track. In some embodiments, if the coverage determination is made from the obstacle, any obstacle may be selected, and placed on the chart where the winding tracks are located according to the position information, and which winding tracks are blocked by the obstacle is detected, and the obstacle is considered to cover or partially cover the winding tracks. In other embodiments, if it is from a winding track, an obstacle may be placed behind the chart in which the winding track is located, depending on its position, each winding track may be checked to see if it is blocked by the obstacle, and if so, the winding track is considered to be covered or partially covered by the obstacle. That is, in some embodiments, the at least partially covering any of the winding tracks responsive to the position comprises: performing coverage detection on any one of the winding tracks; in response to the presence of at least a partial overlap of the any one winding track with the location of one of the winding obstructions, the any one winding track is deemed to be at least partially covered by the location of the corresponding winding obstruction.
After determining the coverage relation between the winding obstacle and the winding track according to the position of the winding obstacle, the assignment of the covered winding track may be adjusted to a second value, for example, in the foregoing embodiment, the winding track is initially assigned to 0, where the assignment of the covered winding track may be adjusted to 1, where 1 is the second value. In the determining and adjusting process, although one winding track may be covered by a plurality of obstacles, the assignment is adjusted to the second value every time the adjustment is performed, so that even if all the obstacles are located on only one winding track, only the assignment of one winding track is changed finally. As shown in fig. 9, three obstacles A, B, C can be detected, where obstacle a would adjust the assignment of the second and third winding tracks to 1, obstacle B would adjust the assignment of the third to fifth winding tracks to 1, and obstacle C would adjust the assignment of the second to sixth winding tracks to 1, but finally, in combination with these 3 obstacles, only the assignment of the second to sixth winding tracks would be adjusted to 1.
Of course, in some embodiments, in order to save resources as much as possible and improve efficiency, when performing assignment, when determining that the assignment of the winding track blocked by the inspected winding track or the obstacle is already the second value, the inspection or the assignment is directly canceled, so as to further save the computing resources of the inspection or the assignment. That is, in some embodiments, the adjusting the assigned value corresponding to the winding track to the second value includes: and in response to the assignment of the covered winding track having been the second value, canceling the assignment adjustment.
In the embodiment of performing the assignment marking by using the bitmap table, since the assignment process is performed based on the bit cells of the bitmap, the numerical value in the corresponding bit cell of the covered winding track can be directly adjusted to the second value when the second value is adjusted. Here, the adjustment of the second value may be directly performed uniformly regardless of whether the value in the current bit cell is the first value or the second value. That is, in some embodiments, the adjusting the assigned value corresponding to the winding track to the second value includes: and adjusting the numerical value in the bit cell corresponding to the covered winding track to be the second value.
And 510, counting the winding tracks assigned to the second value, and outputting a counting result to plan the wiring of the chip design according to the counting result.
In this step, statistics is performed on the winding tracks assigned to the second value, which winding tracks are occupied are determined, and remaining available resources are calculated. As shown in fig. 9, after counting the covered winding track, the remaining available resources (winding resources) are 2.
Of course, in some embodiments, to facilitate subsequent further routing, the positions of the covered wire-wound tracks, i.e., the positions of the wire-wound tracks assigned the second value, may be counted together when counting. That is, in some embodiments, the counting the winding track assigned the second value includes: and counting the number and the positions of the winding tracks assigned to the second value.
Of course, in the embodiment of performing assignment marking by using the bitmap table in combination with the foregoing embodiment, since each bit cell in the bitmap table corresponds to one winding track, after the bitmap table is acquired, it can be determined which winding track is covered according to the bitmap table, and the position of which winding track is specifically information such as what winding track.
Finally, the statistical result is output, so that the back-end chip wiring unit can conduct wiring wire winding planning of wiring according to the statistical result. Of course, the way in which the statistics are output may not be limited to the back-end chip routing unit, but may also be used to store, display, use, or reprocess the statistics. According to different application scenes and implementation requirements, a specific output mode of the statistical result can be flexibly selected.
For example, for an application scenario in which the method of the present embodiment is executed on a single device, the statistical result may be directly output on a display part (display, projector, etc.) of the current device in a display manner, so that an operator of the current device can directly see the content of the statistical result from the display part.
For another example, for an application scenario of the method of the embodiment executed on a system formed by a plurality of devices, the statistical result may be sent to other preset devices as the receiving party in the system, that is, the synchronization terminal, through any data communication manner (such as wired connection, NFC, bluetooth, wifi, cellular mobile network, etc.), so that the synchronization terminal may perform subsequent processing on the statistical result. Optionally, the synchronization terminal may be a preset server, where the server is generally disposed in the cloud, and is used as a data processing and storage center, and is capable of storing and distributing the statistical result; the receiving party of the distribution is terminal equipment, and the holders or operators of the terminal equipment can be all levels of designers, design managers, producers and the like of the chip.
For another example, for an application scenario executed by the method of the present embodiment on a system formed by a plurality of devices, the statistical result may be directly sent to a preset terminal device through an arbitrary data communication manner, where the terminal device may be one or more of the foregoing paragraph lists.
In a specific embodiment, as shown in fig. 10, a flow chart of a specific winding obstacle occupation winding track resource determination process according to an exemplary method 500 of the present application is shown. Firstly, in the global wiring stage, the global grid is divided on the whole chip area. And then reading the winding resource track pattern of each winding layer to determine the winding track. An initial bitmap (bitmap) is generated according to winding resources in the three-dimensional grid, the size (size) of the bitmap is the number of the initially available winding tracks, and all bit values are 0 (i.e. each bit is initially assigned with a first value), which indicates that the bitmap is not occupied by an obstacle.
And then, sequentially reading various winding barriers, and marking bitmaps in the global grids on the corresponding winding layers. As shown in fig. 9. From the figure, we can see that the bitmap can quickly mark each obstacle, and the accumulation problem of occupying resources is naturally avoided.
Finally, after marking the bitmap of all the winding obstacles on the chip, the remaining available resources in each global grid can be quickly obtained, and the following global wiring planning flow can be carried out.
As can be seen from the foregoing embodiments, in the wiring planning method for chip design provided by the present application, a first value is assigned to all winding tracks of a winding layer, then whether any winding track is covered or partially covered is determined according to a position of a winding obstacle in the winding layer of the layer, the assignment of the winding track that is at least partially covered is adjusted to a second value, and finally, an occupation condition of winding resources of the winding layer of the layer is determined by counting the winding tracks that are assigned to the second value. In this way, no matter the conditions of overlapping or mutual shielding exist between winding obstacles, statistics is carried out only according to the assignment condition of a winding track, even if the assignment of one winding track is adjusted for a plurality of times, the adjustment result is that the assignment is adjusted to be a second value, and the condition of repeated calculation cannot occur, so that the phenomenon of multi-buckling is avoided, the cost of subsequent adjustment is reduced, and the overall efficiency is improved.
It should be noted that, the method of the embodiment of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment of the application can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of an embodiment of the present application, the devices interacting with each other to accomplish the method.
It should be noted that the foregoing describes specific embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method 500 according to any of the embodiments above, corresponding to the method of any of the embodiments above.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The storage medium of the foregoing embodiments stores computer instructions for causing the computer to perform the method 500 described in any of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Based on the same inventive concept, the present application also provides a computer program product, corresponding to any of the embodiment methods 500 described above, comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the described method 500. Corresponding to the execution bodies to which the steps in the embodiments of the method 500 correspond, the processor that executes the corresponding step may belong to the corresponding execution body.
The computer program product of the above embodiment is configured to cause a processor to perform the method 500 of any of the above embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.
Claims (9)
1. A wiring planning method for chip design, comprising:
acquiring a chip design layout;
determining all winding tracks of any winding layer in the chip design layout, and assigning a first value to each winding track;
determining the position of at least one winding obstacle in any winding layer according to the chip design layout;
responsive to the position at least partially covering any one of the winding tracks, adjusting a corresponding assignment for the winding track to a second value;
counting the winding tracks assigned to the second value, and outputting a counting result to plan the wiring of the chip design according to the counting result;
the adjusting the assigned value corresponding to the winding track to the second value includes:
and in response to the assignment of the covered winding track having been the second value, canceling the assignment adjustment.
2. The method of claim 1, wherein determining all routing tracks of any one routing layer in the chip design layout comprises:
global meshing is carried out on any layer of winding layers, the maximum number of winding tracks allowed in each mesh is determined, and the number of winding tracks of any row or any column of mesh is uniformly distributed according to the maximum number of winding tracks, so that all winding tracks of any layer of winding layers are determined.
3. The method according to claim 2, wherein the uniformly arranging the number of winding tracks of the grid of any row or any column according to the maximum number of winding tracks comprises:
determining the track direction of any winding layer;
responding to the track direction being transverse, uniformly distributing the number of the winding tracks of the grid of any column according to the maximum number of the winding tracks;
and responding to the track direction being longitudinal, uniformly distributing the number of the winding tracks of the grid of any row according to the maximum number of the winding tracks.
4. The method of claim 1, wherein said assigning a first value to each of said winding tracks comprises:
generating a bitmap table with corresponding length according to the total number of winding tracks of any winding layer; wherein each bit cell in the bit map corresponds to one of the winding tracks;
and carrying out assignment of the first value on each bit cell of the bitmap table.
5. The method of claim 4, wherein adjusting the assigned value for the winding track to the second value comprises:
and adjusting the numerical value in the bit cell corresponding to the covered winding track to be the second value.
6. The method of claim 1, wherein said at least partially covering any one of said winding tracks responsive to said position comprises:
performing coverage detection on any one of the winding tracks;
in response to any one of the winding tracks at least partially overlapping the location of one of the winding obstacles, any one of the winding tracks is considered to be at least partially covered by the location of the corresponding winding obstacle.
7. The method of claim 1, wherein said counting the winding trajectory assigned the second value comprises:
and counting the number and the positions of the winding tracks assigned to the second value.
8. A computer device comprising one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of any of claims 1-7.
9. A non-transitory computer readable storage medium containing a computer program, which when executed by one or more processors causes the processors to perform the method of any of claims 1 to 7.
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