CN117688895B

CN117688895B - Circuit diagram generating method, computer device and storage medium

Info

Publication number: CN117688895B
Application number: CN202410156710.7A
Authority: CN
Inventors: 朱昊; 刘安; 傅泽淮
Original assignee: Xinxingji Technology Co ltd
Current assignee: Xinxingji Technology Co ltd
Priority date: 2024-02-04
Filing date: 2024-02-04
Publication date: 2024-04-23
Anticipated expiration: 2044-02-04
Also published as: CN117688895A

Abstract

The application provides a circuit diagram generation method, computer equipment and a storage medium, wherein the method comprises the following steps: reading initial layout planning data; determining at least one module sequence containing at least one module according to the initial layout planning data, generating a cover frame corresponding to any module, and determining the occupation range of the at least one module sequence according to the cover frame; arranging the module sequences according to the occupied range, and arranging at least one module sequence on an initial drawing according to the arrangement sequence and a preset rule to obtain an intermediate drawing; dividing the middle drawing according to the cover frame to generate a plurality of wiring spaces, determining the wiring space to be passed by any one of the wires between the modules according to a heuristic search algorithm, and optimizing the positions of the wires in the wiring space according to the connection attribute of the wires to generate a final drawing.

Description

Circuit diagram generating method, computer device and storage medium

Technical Field

The present application relates to the field of chip layout planning technologies, and in particular, to a circuit diagram generating method, a computer device, and a storage medium.

Background

Electronic design automation (Electronic Design Automation, EDA for short) refers to a design method that uses Computer Aided Design (CAD) software to complete the processes of functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large scale integrated circuit (VLSI) chips.

In EDA tools, the schematic diagram of the circuit is the most intuitive display mode for engineers and is an important component of mature EDA tools. With advances in technology, circuit schematics are automatically generated (ASG, automatic Schematic Generation) to become a necessary technology for EDA tools. However, current ASG systems have difficulty handling circuit blocks of varying sizes and shapes, and can result in a large number of unusable blank areas in the schematic circuit diagram.

Disclosure of Invention

In view of the above, the present application provides a circuit diagram generating method, a computer device and a storage medium to solve or partially solve the above-mentioned problems.

Based on the above object, the first aspect of the present application provides a circuit diagram generating method, including:

reading initial layout planning data;

Determining at least one module sequence comprising at least one module according to the initial layout planning data, generating a coverage frame corresponding to any module, and determining the occupation range of the at least one module sequence according to the coverage frame;

Arranging the module sequences according to the occupation range, and arranging at least one module sequence on an initial drawing according to an arrangement sequence and a preset rule to obtain an intermediate drawing;

Dividing the intermediate drawing according to the covering frame to generate a plurality of wiring spaces, determining the wiring space to be passed by any one of the wires between the modules according to a heuristic search algorithm, and optimizing the positions of the wires in the wiring space according to the connection attribute of the wires to generate a final drawing.

In a second aspect of the application, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of the first aspect.

In a third aspect of the application, there is provided a non-transitory computer readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of the first aspect.

According to the circuit diagram generation method, the computer equipment and the storage medium, the module sequences are generated according to the connection relation among the modules, the occupation range of each module sequence is determined, the arrangement positions among the module sequences are adjusted according to the connection relation among the module sequences, and the like, so that gaps among the module sequences are reduced, and convenience is brought to wiring connection, and therefore the intermediate drawing is obtained. And determining the wiring space for wiring in the middle drawing, calculating the optimal path of the wiring according to a heuristic search algorithm, determining the wiring space to be passed by each wiring, and finally performing local optimization of the wiring to finally complete the circuit diagram.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only embodiments of the present application and that other drawings can be obtained according to the drawings without inventive effort for those skilled in the art.

Fig. 1 shows a schematic hardware structure of an exemplary computer device according to an embodiment of the present application.

Fig. 2A shows a basic structural schematic of an EDA tool according to an embodiment of the application.

FIG. 2B illustrates a schematic diagram of the basic execution flow of one compute command of an EDA tool, according to an embodiment of the present application.

Fig. 3 shows a flow diagram of an exemplary method provided by an embodiment of the application.

Fig. 4 is a schematic diagram showing a module connection relationship and a module size according to an embodiment of the present application.

Fig. 5 shows a schematic diagram of determining an occupancy range according to an embodiment of the present application.

Fig. 6 shows a schematic diagram of the adjustment of a module sequence provided by an embodiment of the present application.

Fig. 7 shows a schematic diagram of generating a routing space according to an embodiment of the present application.

Fig. 8 is a schematic diagram showing the effect of calculating a routing space through which a routing is performed by using a heuristic search algorithm according to an embodiment of the present application.

Fig. 9 shows a schematic diagram of an effect of optimizing a trace in a trace space according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the present specification will be further described in detail below with reference to the accompanying drawings.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements, articles, or method steps preceding the word are included in the listed elements, articles, or method steps following the word, and equivalents thereof, without precluding other elements, articles, or method steps. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Fig. 1 shows a schematic structural diagram of a computer device 100 according to an embodiment of the present application. The computer device 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the device via a bus 110.

The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application SPECIFIC INTEGRATED Circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in fig. 1, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) as well as data to be processed. The processor 102 may also access stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile storage or nonvolatile storage. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communication with other external devices to the computer device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.

Peripheral interface 108 may be configured to connect computer apparatus 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.

Bus 110 may be configured to transfer information between the various components of computer device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.

It should be noted that although the above-described device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the device may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary for implementing the embodiments of the present application, and not all the components shown in the drawings.

Fig. 2A shows a basic structural schematic of an EDA tool 200 according to an embodiment of the application.

As shown in fig. 2A, the user portion is above the dashed line; below the dashed line is an EDA tool 200, which EDA tool 200 may be implemented by the apparatus 100 shown in fig. 1. In some embodiments, the EDA tool 200 may be implemented as EDA software. More specifically, the EDA tool 200 may be software that performs Placement (Placement) and Routing (Routing) based on a chip design. Simulation tool 200 can include a Tcl command (or graphical/window interface) module 204, computing modules (e.g., a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc.), and a database system 212. The user 202 may operate the EDA tool 200 by entering relevant commands in a Tcl command (or graphical/window interface) module 204.

Tcl command module 204 functions primarily as message passing or command passing. Tcl command module 204 may read instructions entered by user 202 into simulation tool 200 and may assign and pass to the corresponding computing module to perform specific tasks based on the specific content of the instructions.

The calculation modules may be divided into, for example, a plane calculation module 206, a Route calculation module 208, an Optimization calculation module 210, and the like, according to the calculation tasks. The space calculation module 206 may be configured to calculate a reasonable placement position for all components, the Route calculation module 208 may be configured to calculate a reasonable wire connection manner between components, and the Optimization calculation module 210 may be configured to optimize the placement position and the wire connection manner between components. The computation of these computation modules may be performed, for example, in the processor 102 of fig. 1.

Database system 212 may be used to fully record, store, etc., all information (e.g., location, orientation, size, configuration, wire connection, etc.) of the chip being emulated or designed. Such information may be stored, for example, in memory 104 of fig. 1.

FIG. 2B illustrates a basic execution flow 300 of one compute command of the EDA tool 200, according to an embodiment of the application. As shown in FIG. 2B, at step 302, user 202 may issue a command (e.g., a do_place command) to the EDA tool 200 through a command interface or Graphical User Interface (GUI) provided by the Tcl command module 204. Tcl command module 204 then parses this command and distributes it to the corresponding computing module (e.g., space computing module 206) at step 304. In step 306, each computing module performs the specific calculations that each needs to perform. During this time, each computing module needs to (at high frequency, repeatedly) retrieve the data in database system 212 to perform the computation, as shown in step 308. After the calculations are completed, each calculation module may write the calculation results to database system 212 and return the calculation results to Tcl command module 204, as shown in step 310. At step 312, the tcl command module 204 returns the calculation result to the user 202 via a command interface or Graphical User Interface (GUI), and the EDA tool 200 ends the processing of a calculation command. At step 314, the user may evaluate based on the calculation and then determine the next plan.

Layout planning (floorplan), typically, places hard cores (hard macros) into the design and meets the subsequent standard cell (STANDARD CELLS) layout requirements. Generalized layout planning also includes designing aspect ratios of Die (Die), placing I/O pads, pure physical unit (Welltap, endcap) insertion, power grid planning, etc.

As an alternative embodiment, the process shown in FIG. 2B may be used to complete the initial layout plan, resulting in initial layout plan data for the chip design. The key to ASG systems, as described in the background section, is the ability to automatically generate a practical and aesthetically pleasing circuit diagram. To enhance the user's understanding of complex schematic circuit diagrams, the circuit diagrams need to satisfy the following criteria: (1) regular, symmetrical, functionally readable; (2) maintain and clearly show the flow direction of the signal; (3) The connection between the devices is shorter, and the total length of the connection is reduced as much as possible; (4) The number of bifurcations, intersections, and turns in the wiring is reduced. In a schematic diagram, devices of various shapes and sizes (i.e., modules or circuit modules) are involved, and how to reasonably allocate space to them is the basis of the schematic diagram layout. Most ASG systems manage schematic space through a fixed scale based grid system. The usual approach is that each device occupies one grid, which has the advantage of simplicity of calculation, since the schematic diagram space is limited to a grid set of limited size. However, the grid cannot handle modules of different sizes and shapes. Still other systems manage space by constructing a sequence (string) of modules, which is a string of modules connected together, with the output pin (output pin) of a previous module connected to the input pin (input pin) of a next module. The modules are surrounded by a bounding box which defines the space in which the sequence of modules is placed, but at the same time this leads to a large number of unusable blank areas in the schematic diagram.

In view of this, the embodiment of the application provides a circuit diagram generating scheme, which generates module sequences according to the connection relation among the modules, determines the occupation range of each module sequence, adjusts the placement positions among the module sequences according to the connection relation among the module sequences, and the like, reduces the gaps among the module sequences and provides convenience for wiring connection, so as to obtain an intermediate drawing. And determining the wiring space for wiring in the middle drawing, calculating the optimal path of the wiring according to a heuristic search algorithm, determining the wiring space to be passed by each wiring, and finally performing local optimization of the wiring to finally complete the circuit diagram.

Fig. 3 shows a flow diagram of an exemplary method 400 provided by an embodiment of the application. The method 400 may be implemented by the computer device 100 of fig. 1 and may be implemented as part of the functionality of the EDA tool 200 of fig. 2A. As shown in fig. 3, the method 400 may further include the following steps.

Step 402, the initial layout planning data is read.

In this step, the initial layout plan data may be layout plan data after the connection relationship between the respective modules is determined. In these layout plan data, data such as the size and shape of each module is recorded. The module is a generic term for each functional unit constituting the circuit, and may be at least one of a functional block (Instance) or a Port (Port), specifically, a hard core (hard macros) or a Register (Register) or a latch (Flip-Flop), and the like. Each module is typically provided with corresponding execution code, and the longer the execution code or the more content, the larger the corresponding module will be. Here, since the corresponding functions of the general modules are already designed and the corresponding code bodies or frames are already constructed when the circuit diagram design is performed, the size of each module can be determined, and the corresponding shapes thereof may be different according to different functions and can be determined with reference to design specifications or industry standards.

Thereafter, in some embodiments, the manner of acquisition may be by active entry by an operator, by direct acquisition from an upstream executing program or terminal through a corresponding interface, and so forth.

Step 404, determining at least one module sequence including at least one module according to the initial layout planning data, generating a coverage frame corresponding to any module, and determining an occupation range of the at least one module sequence according to the coverage frame.

In this step, the module sequence is a sequence including at least one module connected to each other (an individual module may also be a module sequence), and since connection relations between modules are already recorded in the initial layout planning data, at least one different module sequence may be extracted according to the connection relations.

In some embodiments, a sequence of modules with different connection relationships may be generated according to specific requirements, for example, a sequence of modules with linear connection may be generated, a sequence of modules with parallel connection relationships in which one module connects multiple modules may be generated, and so on. In order to facilitate space management, the module sequences can be formed in a linear connection mode, so that the connected module sequences can be more conveniently subjected to position adjustment among the module sequences, and space utilization is facilitated. In a specific circuit design embodiment, a sequence of modules (string) is formed by input-output relationships between a plurality of modules. Each sequence of modules may be viewed as a separate unit for handling coupling relationships between non-placed modules. These sequences of modules need to be placed in the corresponding tile space (i.e., the space occupied by the footprint, which is generally rectangular and thus may be referred to as tile space), and eventually position-merged. The non-placed modules are placed one by one according to their connection relationship, and the longest connection circuit is taken as a module sequence. If there are modules that are input-output relationships to each other, they are called cross-coupling points, in which case the modules and the sequence of connected modules will be recursively connected into the circuit step by step as a sub-module sequence (sub-string). In addition, each sequence of modules and the modules it contains will be placed as a whole in an empty grid. Therefore, the modules can be ensured not to overlap each other in the placing process, and the whole circuit diagram can be more attractive. Through the design method, the coupling relation between the modules can be effectively processed, and meanwhile, the reasonable and attractive layout of the circuit diagram is ensured. As shown in fig. 4, after determining the connection relationship between the modules according to the initial layout planning data, the longest linear module sequence, i.e. the module sequence 1 in fig. 4, may be selected according to the connection relationship, and then other module sequences connected to the module sequence 1, i.e. the module sequence 2 and the module sequence 3, are selected.

That is, according to the connection relationship between the modules determined by the initial layout planning data, a longest module group that is linearly connected may be selected first as a module sequence. And then selecting the longest group of modules from the rest modules, and taking the group of modules which have connection relation with the former module sequence as a second module sequence. And then selecting the longest group of modules from the rest of modules, wherein the group of modules which have a connection relation with any one of the two previous module sequences is used as a third module sequence, and the like until all the modules are selected. That is, in some embodiments, the determining at least one module sequence including at least one module from the initial layout planning data includes: determining a connection relation between each module according to the initial layout planning data, selecting a group of modules with longest linear connection links according to the connection relation, and generating a module sequence; and selecting a group of modules which have a connection relation with the determined module sequence and have the longest linear connection link from the rest modules according to the connection relation, and circulating the group of modules as one module sequence until all the modules are selected. The determined module sequence may be one module sequence or a plurality of module sequences.

After that, after a module sequence is selected, the occupation range of each module sequence needs to be determined, and in order to determine the occupation range of the module sequence, the size of each module in the module sequence is determined first. In some embodiments, the corresponding module may be represented by a cover frame corresponding to each module, where the cover frame may be a cover frame corresponding to the shape and size of the module itself, or may be a frame structure that includes or can represent the corresponding module, such as an external frame, etc.

In some embodiments, the size and shape of each module may be determined directly from the data of the initial layout plan data record; the external frame of each module can be determined for the convenience of statistics and unified calculation, and each module is represented by a rectangular external frame. As shown in fig. 4, most of the modules are rectangular modules, and the external frame body of the modules generally coincides with the size of the modules. However, the ctmTdsLR _1_2339 module and the or232 module are shaped modules, and the two modules can be represented by external frames of the two modules. That is, in some embodiments, the generating a coverage box corresponding to any one of the modules includes: and determining the size and shape of any module according to the initial layout planning data, generating an external frame body of any module, and taking the external frame body as the cover frame.

In some embodiments, to provide a certain error range and improve the fault tolerance, the overlay frame may be formed by adding a set threshold value to the size of the external frame. For example, a frame with 2*3 circumscribed frames, a cover frame of 3×4 or a cover frame of 4*4 may be formed after the threshold is added. That is, in some embodiments, the taking the external frame as the cover frame includes: and adding a preset threshold value based on the size of the external frame body to generate the covering frame.

After the overlay frame is generated, the location of the overlay frame needs to be determined, and after the location of the overlay frame of all modules in a sequence of modules is determined, the corresponding occupancy range can be determined. Because the module sequence is generated by the selected linearly connected modules, the module pins of the two modules connected with each other in the module sequence can be directly determined for the convenience and simplification of wiring design, and the two pins are placed on the same straight line or the same height, so that the generated wiring can be a straight line without turning, and the wiring design is convenient. Taking fig. 4 as an example, for the module sequence 1, the output pin and the corresponding input pin of each module may be set at the same height, so as to determine the position of each module in the height direction. In the longitudinal direction, the spacing can then be determined from the minimum spacing required in the chip design or the spacing value set by the designer, etc., since there is generally not much restriction on the series of modules connected linearly in this direction. Finally, after the placement is completed, the occupation range of the module sequence can be determined according to the edge line of the module at the edge in each direction. As shown in fig. 5, after the covering frame is placed, the edge line position of the occupation range can be determined for the module sequence 1 according to the edge line of the corresponding direction of the module at the outermost edge in the up-down, left-right direction, so that a rectangular frame body can be generated, namely the occupation range. That is, in some embodiments, the determining the occupancy range of the at least one module sequence according to the coverage frame includes: for any module sequence, determining module pins for connecting modules according to the initial layout planning data, and setting the mutually connected module pins at the same height according to the connection relation; and responding to all modules in any module sequence to complete height adjustment, determining the edge positions of the occupation ranges of the module sequence according to the positions of the modules positioned at the extreme edge, and generating the occupation ranges of the rectangle.

In some embodiments, to provide a certain error range, and improve the fault tolerance, the occupation range may be formed by adding a set threshold value on the basis of the edge line position of the edge-most module. For example, the minimum distance of the occupation range from the cover frame can be set to 2nm. Or a minimum distance in the length direction of 2nm and a minimum distance in the width direction of 3nm, etc. That is, in some embodiments, the determining the edge position of the occupancy range of the module sequence according to the position of the module located at the most edge includes: and adding a preset threshold value based on the position of the most marginal module, and determining the edge position of the occupied range.

And step 406, arranging the module sequences according to the occupation range, and placing at least one module sequence on an initial drawing according to the arrangement sequence and a preset rule to obtain an intermediate drawing.

In this step, after the occupation range of each module sequence is determined, the arrangement of the size or length of the occupation range can be performed.

Then, the occupation range (module sequence) with the longest length can be selected for placement firstly, and then the placement is sequentially carried out from long to short, so that the sequence with the large occupation range can be placed firstly, and the small module is placed afterwards, so that the small module sequence can select the gap position of the large module sequence to complete placement, and the space utilization rate is improved. Also, in some embodiments, there may be a large number of branches in one circuit for one layer of chip circuitry, so that for the sequence of modules in this embodiment, one sequence of modules may be connected to a module in another sequence of modules, corresponding to one branch of this sequence of modules. In order to facilitate the design of the wiring between the module sequences in the subsequent design, the module sequences with connection relation with the placed module sequences can be selected when the module sequences are placed, the placed module sequences can be one or more, the selected module sequences only need to be connected with one of the module sequences, and the module sequences with long lengths are selected as soon as possible. Then, as the module sequence to be placed and the placed module sequence have a connection relationship, the connection position between the module sequence to be placed and the module sequence to be placed can be further determined, namely, the module sequence to be placed and the module sequence to be placed are mutually connected through which pin of which module. It should be noted that, in this embodiment, the module sequences are all selected in a linear connection manner, so, as shown in fig. 4 or fig. 5, the left and right of a general module sequence will not be connected to other module sequences, if there are modules, the module sequences should also be integrated into the linear connection of the module sequences, so that the general module sequences and the module sequences are all connected up and down, further, according to the connection positions, the point positions of the module sequences connected to each other can be determined, and the point positions can be pins of any module in the module sequences, so that the position of the module sequence to be placed in the length direction can be determined according to the point positions. And then determining whether the module sequence to be placed is positioned above or below the placed module sequence according to the principle of shortest connecting line between pins, so that the module sequence to be placed can be firstly arranged at an initial position or virtually arranged at an initial position. As shown in fig. 6, the a pin of ctmTdsLR _1_2339 module of the module sequence 1 is connected to the B pin of ff83 module of the module sequence 2, and the module sequence 2 may be disposed at the upper left side of the a pin of the module sequence 1 (in the dashed line position of the module sequence 2 in the drawing) according to the relative positional relationship. And then, generating a connection guide according to the pins of the two module sequences, such as a connection wire generated by the pin A and the pin B. And then according to the connection guide, the position of the module sequence to be placed is adjusted, for example, according to the connection line of the connection guide, the module sequence 2 is slowly pulled from the initial position to a position close to the module sequence 1 along the connection line. As illustrated in fig. 6, the module sequence 2 can be pulled along the connecting guide wire to the position of the module sequence 2'. Of course, for why the module sequence 2 is left upper rather than right upper, there is also a design rule influence (belonging to a preset rule) about the lead routing, i.e. when the lead is a transverse lead, the extended routing needs to be transversely extended by a certain distance to be turned; the longitudinal direction is the same. Thus, the module sequence 2 can be arranged at the upper left according to the trend of pins, the upper-lower relation and the like. That is, in some embodiments, the placing the at least one module sequence on the initial drawing according to the arrangement order and the preset rule includes: arranging the module sequences according to the length of the occupied range; determining a set module sequence, and selecting a module sequence with a connection relation with the set module sequence as a module sequence to be set based on the arrangement sequence; determining a connection position between the module sequence to be placed and the placed module sequence, performing initial position setting on the module sequence to be placed according to the connection position, generating connection guidance between the module sequence to be placed and the placed module sequence according to the connection position, and adjusting the position of the module sequence to be placed according to the connection guidance so that the position of the module sequence to be placed is close to the placed module sequence. Of course, the fitting or approaching in this embodiment is based on the occupation ranges of the module sequences, i.e. the occupation ranges of the two module sequences are fitted.

In some embodiments, if the module sequence to be placed is the first module sequence, i.e. the longest module sequence, since there is no other module sequence in the original drawing, it may be placed at any position substantially in the original drawing, but for convenience of calculation and operation of an operator, it may be set at an origin position in the original drawing, where the origin position is generally an original point of the original drawing. Meanwhile, if the module sequence to be placed has no connection relation with the currently placed module sequence, the module sequence may be a new link, so that the module sequence can be placed at will, but in order to be regular and prevent mutual influence, the module sequence can be placed at other preset points or at positions determined according to preset rules. That is, in some embodiments, the method further comprises: determining whether the module sequence to be placed is the first module sequence to be placed or whether the module sequence to be placed has no corresponding connection relation with the placed module sequence; if yes, the module sequence to be placed is arranged at a preset point position corresponding to the initial drawing.

In a specific embodiment, as shown in fig. 6, the sequence of modules that have completed the placement operation need to determine the direction and location of placement based on the connection relationship with other modules. For the new module sequence, the moving axis direction and length are determined according to the connection number so as to be matched with the module sequence with the layout placement completed. As shown in fig. 6, the anchor point B (i.e., the B pin position of the connection) in the module sequence 2 and the anchor point a (i.e., the a pin position of the connection) in the module sequence 1 are determined based on the connection relation, and the angle of the splice, the module sequence 2 to be inserted is controlled to move along the connection guide line to the anchor point a until the module sequence 1 is attached (i.e., the module sequence 2' position is reached). The method for determining the moving direction and the moving length according to the connection number is helpful for reasonably arranging the circuit diagrams as a whole. In this way, it is ensured that the new chain and the already placed chain are engaged with each other, thereby achieving an optimized layout of the circuit diagram.

Finally, after the adjustment of the module sequence is completed, an intermediate drawing is generated, and the positions of the modules in the drawing are basically determined.

Step 408, dividing the intermediate drawing according to the coverage frame, generating a plurality of routing spaces, determining the routing space to be passed by any one routing between the modules according to a heuristic search algorithm, and optimizing the position of the routing in the routing space according to the connection attribute of the routing, so as to generate a final drawing.

In this step, after the intermediate drawing is generated, the wiring between the modules is required to be designed. First, a spatial range in which the routing can be arranged needs to be determined, and here, the intermediate drawing may be divided to generate a plurality of routing spaces in which routing arrangement or routing can be performed. In some embodiments, modules in the middle drawing may be removed first, regular patterns are generated for the remaining area, and each pattern may be used as a routing space. In other embodiments, the extension may be directly performed along the side line of the module on the basis of the module until the extension line touches other modules or edges of the drawing, so that the extension lines that are staggered horizontally and longitudinally may form rectangular spaces, which may be wiring spaces. As shown in fig. 7, the extending may be performed along each side of each module, and the rectangular areas surrounded by the staggered extending lines are the routing space, where the rectangular areas may be the smallest rectangular units, i.e. no other rectangle or line segment is included therein. That is, in some embodiments, the dividing the intermediate drawing according to the coverage frame generates a plurality of routing spaces, including: generating a dividing line by extending outwards along the extending direction of the edge of any covering frame until the dividing line contacts the edge of other covering frames or the boundary of the initial drawing; and responding to detection of a closed space surrounded by a plurality of dividing lines or a closed space surrounded by a plurality of dividing lines and at least one boundary, and taking the closed space as the wiring space.

In some embodiments, the routing space of the schematic diagram is formed by overlapping two spaces, namely a horizontal winding space and a vertical winding space, which are perpendicular to each other. Rectangular tiles are sequentially inserted into the schematic diagram space by taking the modules as units, and the schematic diagram space is horizontally or vertically divided, as shown in fig. 7, wherein the solid line area where the modules are positioned is equivalent to an obstacle in the wiring process, and the area with broken lines represents a blank space, so that the wiring in the horizontal direction or the vertical direction is allowed.

Then, it is necessary to determine which routing spaces each routing needs to pass through for routing connections. The calculation of the shortest distance between points or between points can be performed here by means of a heuristic search algorithm. In some embodiments the calculation may be performed using an a-heuristic search algorithm.

In a specific embodiment, the process of determining the routing space of the routing can be divided into two stages. The first stage is a search stage, using an a-heuristic search algorithm and determining the best route by parallel search. Each output or input pin of each trace has an independent search process, and other paths that build part of the path to connect to the same trace form a complete path. The second stage is an updating stage, wherein the updating process is optimized through congestion information stored in the tile space, and the congestion degree of the schematic diagram routing is reduced. The method combines an A-algorithm and parallel search, and can efficiently and accurately process global wiring tasks. Of course, in a simpler circuit or other specific scenario, the second stage may determine if it is necessary to do so, depending on the situation.

In the search phase, the routing process of each wire (net) is independent of each other, since global routing congestion conditions do not need to be considered. And thus can be accelerated by means of parallel searching. The trace connects two or more module pins, as shown in fig. 8, assuming that it is necessary to reach from the X pin of module 1 to the Y pin of module 2. The searching process is to start from each pin, find a path which appears at intervals of horizontal and vertical, and reach the other pin. For the pin X, the initial state has only 1 necessary path, and the path only includes one horizontal routing space, that is, the routing space where the pin X is located. In the next search, each trace space will calculate with its center as a reference point, in the next calculation of the pin X, the points that can be reached in the next steps, such as point a, point b, point c, point d, etc., are determined laterally (these points are midpoints of the trace space, of course, any point in the trace space may represent the corresponding trace space), the optimal inflection point position for reaching the pin Y can be calculated by using an algorithm (point b is calculated as the optimal point in the figure), and then, since the trace direction has changed to the vertical direction, the calculation is continued from the perpendicular trace space, and so on. Meanwhile, as calculation is respectively carried out from the pin X and the pin Y, when the two pins meet, the path retrieval is considered to be completed between the two pins. That is, in particular embodiments, to facilitate wiring trace by users of the schematic, it is desirable that the individual input pin (input/load pin) to output pin (output/load pin) connections in the net be as short as possible. Therefore, in the searching process, each input or output pin (load pin) targets a corresponding pin (driver pin) to search for an optimal path. The corresponding pin dynamically retrieves the input or output pin closest to the current path point and retrieves the optimal path.

Then, in the update phase, after the first side determines the space of the traces through which all the traces pass (the first side calculates without considering the influence of the newly formed traces), the newly generated traces can be considered to perform one-pass review calculation again because the traces are formed. At this time, since each trace is not actually generated, only the trace space to be passed by each trace is determined, and at this time, a corresponding virtual trace can be generated, so that the determination of the trace space to be passed by the trace can be performed again. Of course, some preset conditions, such as congestion information, which is expressed as the minimum size of the channel required for one trace, need to be considered here. In an embodiment, the width or length of a trace space is fixed, and when the number of traces in the trace space is too large, the size of the channel to which each trace is allocated is very small (generally, the average allocation of the size of the trace space is equal), and when the size is smaller than the minimum size, the trace space is considered to be relatively congested, and needs to be adjusted. That is, in some embodiments, after the determining the trace space to be traversed by any trace between the modules according to a heuristic search algorithm, the method further comprises: and responding to the determination of the wire space to be passed by all the wires, generating a virtual wire corresponding to each wire, and determining the wire space to be passed by any wire according to a heuristic search algorithm again by taking the virtual wire as a known condition.

After determining the space through which each wire passes, it is also necessary to allocate, for any wire or any wire space, a specific location in the wire space where the wires are located, with the aim of generally reducing the intersections between wires. And the routing needs to be optimized on the basis of the corresponding connection attribute. The method comprises the steps of counting the wires parallel to one wire and the positions of the output pins and the input pins of the wires, reducing the crossing condition under the parallel condition according to a preset wire algorithm, and iterating in a circulating way until the crossing condition is reduced to the minimum. In one embodiment, when there are multiple wires in parallel in one wire space, the wire space is uniformly distributed into multiple channels. Wherein traces adjacent to the target pin are preferentially allocated to the vias nearest to their pins. As shown in fig. 9, in the vertical routing space with two wires, the wires closest to the output pin of TSINV _2586_42 are distributed in the left channel of the routing space, while the wires closer to xor606 are distributed in the right channel, and this channel distribution mode can effectively reduce the crossing of wires. That is, in some embodiments, the optimizing the position of the trace in the trace space according to the connection attribute of the trace includes: and determining the crossing condition of the wires in the wire space according to the connection attribute of the wires and the wire space to be passed by each wire, and optimizing the wires according to a preset algorithm so as to reduce the crossing of the wires in the wire space.

Finally, after the wiring is set, the drawing of the circuit diagram is completed. The generated circuit diagram may be output to a back-end process unit. Of course, it is also possible that the output is not limited to the back-end process unit, but it may also be used to store, display, use or rework the circuit diagram. The specific output mode of the circuit diagram can be flexibly selected according to different application scenes and implementation requirements.

For example, for an application scenario in which the method of the present embodiment is executed on a single device, the circuit diagram may be directly output in a display manner on a display section (display, projector, etc.) of the current device, so that an operator of the current device can directly see the content of the circuit diagram from the display section.

For another example, for an application scenario of the method of the present embodiment executed on a system formed by a plurality of devices, the circuit diagram may be sent to other preset devices as a receiving party in the system, that is, the synchronization terminal, through any data communication manner (such as wired connection, NFC, bluetooth, wifi, cellular mobile network, etc.), so that the synchronization terminal may perform subsequent processing on the synchronization terminal. Optionally, the synchronization terminal may be a preset server, where the server is generally disposed in a cloud, and is used as a data processing and storage center, and is capable of storing and distributing the circuit diagram; the receiving party of the distribution is terminal equipment, and the holders or operators of the terminal equipment can be all levels of designers, design managers, producers and the like of the chip.

For another example, when the method of the embodiment is applied to an application scenario executed on a system formed by a plurality of devices, the circuit diagram may be directly sent to a preset terminal device through any data communication manner, and the terminal device may be one or more of the foregoing paragraph lists.

According to the circuit diagram generation method provided by the embodiment of the application, the module sequences are generated according to the connection relation among the modules, the occupation range of each module sequence is determined, the arrangement positions among the module sequences are adjusted according to the connection relation among the module sequences, and the like, so that gaps among the module sequences are reduced, and convenience is brought to wiring connection, and therefore, the intermediate drawing is obtained. And determining the wiring space for wiring in the middle drawing, calculating the optimal path of the wiring according to a heuristic search algorithm, determining the wiring space to be passed by each wiring, and finally performing local optimization of the wiring to finally complete the circuit diagram.

It should be noted that, the method of the embodiment of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment of the application can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of an embodiment of the present application, the devices interacting with each other to accomplish the method.

It should be noted that the foregoing describes specific embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method 400 according to any of the embodiments above, corresponding to the method of any of the embodiments above.

The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

The storage medium of the foregoing embodiments stores computer instructions for causing the computer to perform the method 400 described in any of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.

Based on the same inventive concept, the present application also provides a computer program product, corresponding to any of the embodiment methods 400 described above, comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the described method 400. Corresponding to the execution bodies to which the steps in the embodiments of the method 400 correspond, the processor that executes the corresponding step may belong to the corresponding execution body.

The computer program product of the above embodiment is configured to cause a processor to perform the method 400 of any of the above embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.

Claims

1. A circuit diagram generation method, comprising:

reading initial layout planning data;

dividing the intermediate drawing according to the covering frame to generate a plurality of wiring spaces, determining the wiring space to be passed by any one of the wires between the modules according to a heuristic search algorithm, and optimizing the positions of the wires in the wiring space according to the connection attribute of the wires to generate a final drawing;

The placing the at least one module sequence on the initial drawing according to the arrangement sequence and the preset rule comprises the following steps:

Arranging the module sequences according to the length of the occupied range;

determining a set module sequence, and selecting a module sequence with a connection relation with the set module sequence as a module sequence to be set based on the arrangement sequence;

Determining a connection position between the module sequence to be placed and the placed module sequence, performing initial position setting on the module sequence to be placed according to the connection position, generating connection guidance between the module sequence to be placed and the placed module sequence according to the connection position, and adjusting the position of the module sequence to be placed according to the connection guidance so that the position of the module sequence to be placed is close to the placed module sequence.

2. The method of claim 1, wherein said determining at least one module sequence comprising at least one module from said initial layout planning data comprises:

determining a connection relation between each module according to the initial layout planning data, selecting a group of modules with longest linear connection links according to the connection relation, and generating a module sequence;

And selecting a group of modules which have a connection relation with the determined module sequence and have the longest linear connection link from the rest modules according to the connection relation, and circulating the group of modules as one module sequence until all the modules are selected.

3. The method of claim 2, wherein said determining an occupancy range of the at least one sequence of modules from the coverage box comprises:

For any module sequence, determining module pins for connecting modules according to the initial layout planning data, and setting the mutually connected module pins at the same height according to the connection relation;

And responding to all modules in any module sequence to complete height adjustment, determining the edge positions of the occupation ranges of the module sequence according to the positions of the modules positioned at the extreme edge, and generating the occupation ranges of the rectangle.

4. A method according to claim 3, wherein said determining the edge position of the occupancy range of the sequence of modules from the position of the module at the very edge comprises:

And adding a preset threshold value based on the position of the most marginal module, and determining the edge position of the occupied range.

5. The method of claim 1, wherein generating a coverage box corresponding to any one of the modules comprises:

And determining the size and shape of any module according to the initial layout planning data, generating an external frame body of any module, and taking the external frame body as the cover frame.

6. The method of claim 5, wherein the disposing the circumscribing frame as the overlay frame comprises:

And adding a preset threshold value based on the size of the external frame body to generate the covering frame.

7. The method according to claim 1, wherein the method further comprises:

determining whether the module sequence to be placed is the first module sequence to be placed or whether the module sequence to be placed has no corresponding connection relation with the placed module sequence;

if yes, the module sequence to be placed is arranged at a preset point position corresponding to the initial drawing.

8. The method of claim 1, wherein the dividing the intermediate drawing according to the overlay frame to generate a plurality of routing spaces includes:

generating a dividing line by extending outwards along the extending direction of the edge of any covering frame until the dividing line contacts the edge of other covering frames or the boundary of the initial drawing;

and responding to detection of a closed space surrounded by a plurality of dividing lines or a closed space surrounded by a plurality of dividing lines and at least one boundary, and taking the closed space as the wiring space.

9. The method of claim 1, wherein after the determining the trace space to be traversed by any trace between the modules according to a heuristic search algorithm, the method further comprises:

And responding to the determination of the wire space to be passed by all the wires, generating a virtual wire corresponding to each wire, and determining the wire space to be passed by any wire according to a heuristic search algorithm again by taking the virtual wire as a known condition.

10. The method of claim 1, wherein optimizing the position of the trace in the trace space according to the connection properties of the trace comprises:

And determining the crossing condition of the wires in the wire space according to the connection attribute of the wires and the wire space to be passed by each wire, and optimizing the wires according to a preset algorithm so as to reduce the crossing of the wires in the wire space.

11. A computer device comprising one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of any of claims 1-10.

12. A non-transitory computer readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of any of claims 1 to 10.