CN112763890B - Implementation method of test circuit for adaptive voltage and frequency regulation of chip - Google Patents

Abstract

An implementation method of a test circuit for adaptive voltage and frequency regulation of a chip. The implementation method comprises the following steps: obtaining a netlist corresponding to at least one critical path for realizing a chip; correspondingly finding a first critical path from a working area of the chip according to the netlist corresponding to the first critical path, and acquiring a first critical path coordinate corresponding to the first critical path; establishing a placing boundary of a first testing path in a testing area of the chip, which is different from the working area, according to the first critical path coordinate; and the positions of all units included in the first testing path are distributed in the testing area according to the placing boundary of the first testing path, so that the physical realization of the first critical path is completed in the testing area. The implementation method provided by the embodiment of the disclosure can improve the efficiency of implementing the test circuit in the chip.

Description

Implementation method of test circuit for self-adaptive voltage and frequency regulation of chip

Technical Field

Embodiments of the present disclosure relate to an implementation method of a test circuit for adaptive voltage and frequency adjustment of a chip, an implementation apparatus of a test circuit for adaptive voltage and frequency adjustment of a chip, an adaptive voltage and frequency adjustment apparatus for a chip, an adaptive voltage and frequency adjustment device for a chip, and a storage medium.

Background

The cmos (complementary Metal Oxide semiconductor) process brings great improvements in performance and power consumption for chip manufacturing, but as the size of transistors is gradually reduced, the way of improving the performance of chips by reducing the size of transistors is approaching the limit, and the development cost is greatly increased. In order to balance the performance and power consumption of the chip to the best effect, more and more manufacturers are using adaptive voltage and frequency adjustment methods to dynamically adjust the operating voltage of the chip.

Disclosure of Invention

At least one embodiment of the present disclosure provides an implementation method of a test circuit for adaptive voltage and frequency adjustment of a chip, the test circuit including at least one test path, the at least one test path including a first test path, the implementation method including: obtaining a netlist corresponding to at least one critical path for implementing the chip, where the at least one critical path includes a first critical path, and the first critical path includes a first critical start point unit, a first critical end point unit, and at least one first critical intermediate unit located between the first critical start point unit and the first critical end point unit; correspondingly finding the first critical path from a working area of the chip according to the netlist corresponding to the first critical path, and obtaining first critical path coordinates corresponding to the first critical path, wherein the first critical path coordinates comprise coordinates of the first critical start unit, the first critical end unit and the at least one first critical intermediate unit in the working area; establishing a placing boundary of the first test path in a test area, different from the working area, of the chip according to the first critical path coordinate, wherein the first test path comprises a first test starting point unit, a first test end point unit and at least one first test intermediate unit positioned between the first test starting point unit and the first test end point unit; and the positions of all units included in the first testing path are distributed in the testing area according to the placing boundary of the first testing path, so that the physical realization of the first critical path is completed in the testing area.

For example, in an implementation method provided by at least one embodiment of the present disclosure, creating a placing boundary of the first test path in a test area of the chip different from the working area according to the first critical path coordinate includes: calculating and obtaining the sum of the distances between every two adjacent units in the first critical path according to the first critical path coordinates, and recording the sum as a first distance; and creating a placing boundary of the first test path, so that the distance between the first test starting point unit and the first test end point unit is the first distance.

For example, in an implementation method provided in at least one embodiment of the present disclosure, the laying out, in the test area, the positions of the units included in the first test path according to the placement boundary of the first test path includes: and automatically laying out the positions of all units included in the first test path in the test area according to the placement boundary of the first test path by adopting an automatic layout and wiring tool.

For example, in an implementation method provided in at least one embodiment of the present disclosure, laying out, in the test area, positions of each cell included in the first test path according to a placement boundary of the first test path, further includes: after the automatic layout operation is completed, the positions of the units included in the first test path are adjusted, so that the relative position relationship of the units included in the first test path is closer to the relative position relationship of the units included in the first critical path than before the adjustment, and then the positions of the units included in the first test path are fixed.

For example, in an implementation method provided in at least one embodiment of the present disclosure, the at least one critical path further includes a second critical path, the second critical path includes a second critical starting point unit, a second critical ending point unit, and at least one second critical intermediate unit located between the second critical starting point unit and the second critical ending point unit, and the at least one test path further includes a second test path, and the implementation method further includes: correspondingly finding the second critical path from the working area of the chip according to the netlist corresponding to the second critical path, and obtaining second critical path coordinates corresponding to the second critical path, wherein the second critical path coordinates comprise coordinates of the second critical start unit, the second critical end unit and the at least one second critical middle unit in the working area; creating a placing boundary of the second test path in the test area according to the second critical path coordinate, wherein the second test path comprises a second test starting point unit, a second test end point unit and at least one second test intermediate unit positioned between the second test starting point unit and the second test end point unit; and laying out the positions of all units included in the second test path in the test area according to the placement boundary of the second test path, thereby completing the physical realization of the second critical path in the test area; a line from the first test start point unit to the first test end point unit is referred to as a first line, a line from the second test start point unit to the second test end point unit is referred to as a second line, and the first line crosses the second line.

For example, in an implementation method provided in at least one embodiment of the present disclosure, after the operation of laying out the positions of the units included in the first test path according to the placement boundary of the first test path in the test area is completed, the implementation method further includes: obtaining a time sequence constraint file corresponding to the at least one critical path; and winding the metal wires in the test circuit according to the time sequence constraint file.

For example, in an implementation method provided in at least one embodiment of the present disclosure, before obtaining a netlist corresponding to at least one critical path for implementing the chip, the implementation method further includes: and selecting the at least one critical path from the chip according to the requirement.

For example, in an implementation method provided in at least one embodiment of the present disclosure, the first test starting point unit and the first critical starting point unit use the same type of register, and the first test ending point unit and the first critical ending point unit use the same type of register.

For example, in an implementation method provided in at least one embodiment of the present disclosure, the working area is an area required by the chip to complete its own function, the test area is an area other than the working area in the chip, and the test area is used for implementing the test circuit.

For example, in an implementation method provided in at least one embodiment of the present disclosure, each cell included in the first critical path and the first test path is a gate level cell.

At least one embodiment of the present disclosure further provides an adaptive voltage and frequency adjusting method for a chip, including: the method comprises the steps of finishing physical realization of at least one critical path of the chip in the test area by adopting any realization method provided by the embodiment of the disclosure to form a test circuit; carrying out time delay test on the test circuit to obtain the working frequency of the chip; and adjusting the working voltage of the chip according to the working frequency of the chip.

At least one embodiment of the present disclosure further provides an implementation apparatus for a test circuit for adaptive voltage and frequency adjustment of a chip, where the test circuit includes at least one test path, the at least one test path includes a first test path, and the implementation apparatus includes: a first obtaining module configured to obtain a netlist corresponding to at least one critical path for implementing the chip, where the at least one critical path includes a first critical path, and the first critical path includes a first critical start point unit, a first critical end point unit, and at least one first critical intermediate unit located between the first critical start point unit and the first critical end point unit; a second obtaining module, configured to correspondingly find the first critical path from a working area of the chip according to the netlist corresponding to the first critical path, and obtain first critical path coordinates corresponding to the first critical path, where the first critical path coordinates include coordinates of the first critical start unit, the first critical end unit, and the at least one first critical intermediate unit in the working area; a creation module configured to create a placing boundary of the first test path in a test area of the chip different from the working area according to the first critical path coordinate, the first test path including a first test start point unit, a first test end point unit, and at least one first test intermediate unit located between the first test start point unit and the first test end point unit; and the layout module is configured to layout the positions of the units included in the first test path according to the placing boundary of the first test path in the test area, so as to complete the physical implementation of the first critical path in the test area.

For example, in an implementation apparatus provided in at least one embodiment of the present disclosure, the creating module includes: the calculation module is configured to calculate and obtain the sum of the distances between every two adjacent units in the first critical path according to the first critical path coordinates, and the sum is recorded as a first distance; and a creating sub-module configured to create a placing boundary of the first test path so that a distance between the first test start point unit and the first test end point unit is the first distance.

At least one embodiment of the present disclosure further provides an adaptive voltage and frequency adjusting apparatus for a chip, including: an implementation module configured to implement a physical implementation of the at least one critical path of the chip in the test area to form the test circuit using any implementation method provided by an embodiment of the present disclosure; the test module is configured to perform delay test on the test circuit to obtain the working frequency of the chip; and the adjusting module is configured to adjust the working voltage of the chip according to the working frequency of the chip.

At least one embodiment of the present disclosure also provides an adaptive voltage and frequency adjusting apparatus for a chip, including: a processor; a memory including one or more computer program modules; the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for carrying out any of the methods provided by embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, may implement any of the methods provided by embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a flow diagram of a chip design;

fig. 2 is a flowchart of an implementation method of a test circuit for adaptive voltage and frequency adjustment of a chip according to at least one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a chip in at least one embodiment of the present disclosure;

FIG. 4 is a detailed schematic diagram of a first critical path in at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a first test path in at least one embodiment of the present disclosure;

fig. 6 is a flowchart of step S103 of an implementation method in fig. 2 according to at least one embodiment of the present disclosure;

FIG. 7 is a detailed schematic diagram of a first test path in at least one embodiment of the present disclosure;

FIG. 8 is a flow chart of another method for implementing a test circuit for adaptive voltage and frequency scaling of a chip according to at least one embodiment of the present disclosure;

FIG. 9 is a schematic diagram of another chip in at least one embodiment of the present disclosure;

FIG. 10 is a detailed schematic diagram of a second critical path in at least one embodiment of the present disclosure;

FIG. 11 is a detailed schematic diagram of a second test path in at least one embodiment of the present disclosure;

FIG. 12 is a layout diagram of a first test path and a second test path in at least one embodiment of the present disclosure;

FIG. 13 is a flowchart of yet another method for implementing a test circuit for adaptive voltage and frequency regulation of a chip according to at least one embodiment of the present disclosure;

fig. 14 is a flowchart of an adaptive voltage and frequency adjustment method for a chip according to at least one embodiment of the disclosure;

FIG. 15 is a schematic block diagram of an apparatus for implementing a test circuit for adaptive voltage and frequency adjustment of a chip according to at least one embodiment of the present disclosure;

fig. 16 is a schematic block diagram of a creation module provided by at least one embodiment of the present disclosure;

fig. 17 is a schematic block diagram of an adaptive voltage and frequency adjusting apparatus for a chip according to at least one embodiment of the present disclosure;

fig. 18 is a schematic block diagram of an adaptive voltage and frequency adjustment apparatus for a chip provided by at least one embodiment of the present disclosure;

fig. 19 is a schematic block diagram of an adaptive voltage and frequency scaling apparatus for a chip according to at least one embodiment of the present disclosure; and

fig. 20 is a schematic diagram of a storage medium according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

Usually, the integrated circuit design (chip design) is implemented based on electronic design automation tools (EDA), that is, each step of the integrated circuit design is performed by a chip designer on a computer using various EDA tools. The integrated circuit design process is divided into two stages of front-end design and back-end design, wherein the front-end design comprises the steps of system Level design, Register Transfer Level (RTL) design, RTL simulation, hardware prototype verification, circuit synthesis and the like, and the back-end design comprises the steps of layout design, physical verification, back simulation and the like.

Fig. 1 is a schematic diagram of a chip design process. As shown in fig. 1, the chip design flow includes steps S01 to S11.

Step S01: and (4) defining the architecture. The architecture definition includes a system description and a Behavioral level (Behavioral) description. The entire System is typically modeled using high-level computer languages (e.g., C and System C languages specifically designed for integrated circuit System design), where the functionality of each module is considered to be described to reflect the behavioral functionality of that module.

Step S02: and (4) designing the RTL. RTL designs use a hardware description language (a language capable of describing logic devices, such as Verilog HDL language) to describe the combination logic devices and sequential logic devices based on the transfer between registers. For example, a complex system may be divided into subsystems and then processed separately.

Step S03: and debugging RTL simulation. And debugging the RTL level simulation waveform in order to ensure the correct function of the RTL design.

Step S04: and judging whether a functional error occurs in the debugging process of the RTL simulation waveform.

Step S05: and (4) physical realization. In the physical implementation process, the RTL design is physically designed, including logic synthesis, layout and wiring and the like. The final gate-level netlist is obtained after the physical design.

Step S06: and (5) carrying out simulation debugging on the gate-level netlist.

Step S07: and judging whether a functional error or a time sequence error occurs in the debugging process of the simulation waveform of the gate-level netlist.

Step S08: prototype design (FPGA/Emulation). And (3) putting the RTL design on an FPGA (Field Programmable Gate Array) or an Emulator for prototype design verification. For example, the RTL design is put into the FPGA for prototype design verification, and the FPGA may be programmed to load a plurality of independent basic components (e.g., transistors, resistors, inductors, capacitors, etc.), and these components are connected to each other to form a required actual hardware circuit, thereby verifying whether the intended function of the design can be achieved.

Step S09: and (4) performing prototype design simulation debugging.

Step S10: and judging whether a function error occurs in the prototype design simulation debugging process.

Step S11: and (4) flow sheet. And the tape-out process comprises the steps of delivering the chip design file to an integrated circuit manufacturing factory for plate making and production after the prototype design simulation and the gate-level netlist simulation are passed. For example, a back-end physical implementation tool (e.g., Place & route (pr) tool) generates a GDSII file using the gate-level netlist as input, the GDSII file being used for chip manufacturing.

Because the chips have process errors in the manufacturing process, even the chips manufactured in the same batch have unique characteristics, so that the plurality of chips can reach the same working frequency, and the working voltage required by some chips can be lower than that of other chips; or, some chips can reach higher operating frequency under the same operating voltage condition, and some chips may not work normally. Therefore, in order to compensate for the process error in the chip manufacturing process and achieve the best balance between the chip performance and the power consumption, for example, an Adaptive Voltage and Frequency Scaling (AVFS) method may be used to dynamically adjust the operating Voltage of the chip.

The self-adaptive voltage and frequency regulation method aims to dynamically regulate the working voltage of a chip through a hardware mechanism on the chip, for example, the temperature and the working frequency of a node are measured in real time when the chip works, and then the working voltage is regulated in real time according to the measurement result, so that the chip works in the optimal state; the method reduces unnecessary power consumption cost by reducing unnecessary high-range working voltage, and the effect is substantially reduced due to the influence of process errors of the chip in the manufacturing process.

For example, one method is to implement a test circuit in a partial region of the chip, where the test circuit can physically implement some critical paths in different modules of the chip, and then test the test circuit when the chip is operating so as to obtain a working frequency corresponding to the chip, thereby implementing the adaptive voltage and frequency adjustment method.

For example, the test circuit may include a plurality of test paths, and the plurality of test paths respectively correspond to some critical paths in different modules of the chip. In an implementation method of a test circuit, for example, for a critical path a, a designer manually places a plurality of units in a partial area of a chip to implement a test path a corresponding to the critical path a; for another example, for the critical path B, the designer manually puts a plurality of cells in a partial area of the chip to realize a test path B corresponding to the critical path B. The method needs designers to manually place a plurality of units of the test path, and the efficiency is low; in addition, the implementation methods of a plurality of test paths corresponding to a plurality of critical paths are not uniform and have differences, so that the test result of the test circuit may have deviation; finally, the method may occupy the original hardware resources of the chip, and affect the performance of the chip.

At least one embodiment of the present disclosure provides an implementation method of a test circuit for adaptive voltage and frequency adjustment of a chip, where the test circuit includes at least one test path, and the at least one test path includes a first test path, and the implementation method includes: obtaining a netlist corresponding to at least one critical path for realizing a chip, wherein the at least one critical path comprises a first critical path, and the first critical path comprises a first critical starting point unit, a first critical ending point unit and at least one first critical intermediate unit positioned between the first critical starting point unit and the first critical ending point unit; correspondingly finding a first key path from the working area of the chip according to the netlist corresponding to the first key path, and obtaining first key path coordinates corresponding to the first key path, wherein the first key path coordinates comprise coordinates of a first key starting point unit, a first key end point unit and at least one first key middle unit in the working area; establishing a placing boundary of a first test path in a test area, different from a working area, of the chip according to the first critical path coordinate, wherein the first test path comprises a first test starting point unit, a first test end point unit and at least one first test intermediate unit positioned between the first test starting point unit and the first test end point unit; and the positions of all units included in the first testing path are distributed in the testing area according to the placing boundary of the first testing path, so that the physical realization of the first critical path is completed in the testing area.

Embodiments of the present disclosure also provide an adaptive voltage and frequency adjusting method for a chip, an implementation apparatus of a test circuit for adaptive voltage and frequency adjustment of a chip, an adaptive voltage and frequency adjusting apparatus for a chip, an adaptive voltage and frequency adjusting device for a chip, and a storage medium.

The method, the device, the equipment and the storage medium provided by the embodiment of the disclosure do not occupy the original hardware resources of the chip when the circuit is tested in the chip, do not influence the performance of the chip, and can improve the efficiency; furthermore, a plurality of test paths in the test circuit can be realized by adopting a uniform method, so that the deviation of the subsequent test result of the test circuit is reduced or eliminated, and the quality of the test result is ensured.

At least one embodiment of the present disclosure provides an implementation method 10 for a test circuit for Adaptive Voltage and Frequency regulation of a chip, where the implementation method 10 may be used to implement the test circuit in the chip, so as to lay a foundation for an Adaptive Voltage and Frequency regulation (AVFS) method to be performed subsequently. For example, the implementation method 10 may be implemented in a chip design stage (e.g., in the step S05), and the test circuit may be actually physically implemented subsequently along with the completion of chip flow.

For example, the test circuit comprises at least one test path, and the at least one test path comprises a first test path, as shown in fig. 2, and the implementation method comprises the following operation steps.

S101: the method comprises the steps of obtaining a netlist corresponding to at least one critical path for realizing a chip, wherein the at least one critical path comprises a first critical path, and the first critical path comprises a first critical starting point unit, a first critical ending point unit and at least one first critical intermediate unit positioned between the first critical starting point unit and the first critical ending point unit.

S102: and correspondingly finding a first critical path from the working area of the chip according to the netlist corresponding to the first critical path, and obtaining first critical path coordinates corresponding to the first critical path, wherein the first critical path coordinates comprise coordinates of a first critical start unit, a first critical end unit and at least one first critical intermediate unit in the working area.

S103: and establishing a placing boundary of a first test path in a test area, different from the working area, of the chip according to the first critical path coordinate, wherein the first test path comprises a first test starting point unit, a first test end point unit and at least one first test intermediate unit positioned between the first test starting point unit and the first test end point unit.

S104: and the positions of all units included in the first test path are distributed in the test area according to the placing boundary of the first test path, so that the physical realization of the first critical path is completed in the test area.

For example, as shown in fig. 3, the chip 100 includes an operating region WR and a test region TR different from the operating region WR. For example, the working region WR is a region required by the chip 100 to complete its own function, for example, a plurality of modules are disposed in the working region WR, each module has one or more units (e.g., functional units) disposed therein, and metal traces between the units are disposed, and the modules cooperate with each other to achieve their own functions. The plurality of cells and the metal traces between the plurality of cells in the working region WR form a plurality of paths. And the test region TR, which is a region of the chip 100 other than the operating region WR for implementing a test circuit. For example, a region where the routing resources are relatively vacant may be selected as the test region TR in a region other than the operating region WR of the chip.

Since there are many paths in the working region WR of the chip 100, which is not practical if all paths are implemented in the test region TR, which is equivalent to one chip being duplicated, at least one critical path in the working region WR of the chip 100 is typically physically implemented, so that a corresponding test circuit is implemented in the test region TR, for example, the test circuit includes at least one test path, which corresponds to at least one critical path one by one.

For example, as shown in fig. 3, the at least one critical path includes a first critical path CP1, and correspondingly, the at least one test path includes a first test path TP1, and the foregoing implementation method 10 is first described below by taking an example of implementing the first critical path CP1 as the first test path TP 1.

It should be noted that fig. 3 only schematically illustrates the first critical path CP1 and the first test path TP1, which is not limited in this respect, and the chip 100 may further include more critical paths and more test paths. In addition, the sizes of the working region WR, the test region TR, the first critical path CP1, and the first test path TP1 shown in fig. 3 are merely schematic and do not represent true scales.

In step S101, a netlist corresponding to at least one critical path for implementing the chip 100 is obtained, for example, a netlist corresponding to the first critical path CP1 is obtained. For example, fig. 4 is a detailed schematic diagram of one example of the first critical path CP1 shown in fig. 3. As shown in fig. 4, the first critical path CP1 includes a first critical start point cell CS1, a first critical end point cell CE1, and at least one first critical intermediate cell CM1 located between the first critical start point cell CS1 and the first critical end point cell CE 1. For example, the netlist corresponding to the first critical path CP1 includes the cells included in the first critical path CP1 and the logic relationship between the cells.

It should be noted that fig. 4 shows three first key intermediate units CM1, but the number of the first key intermediate units CM1 is not limited in the embodiment of the present disclosure, and may be, for example, 1, 2, 4, or more. For example, the cells in the first critical path CP1 are connected to each other by metal traces ML. For example, the first critical start point unit CS1 and the first critical end point unit CE1 may be registers including an input terminal D, an output terminal Q, and a clock signal terminal CK.

For example, in some embodiments, the netlist corresponding to the at least one critical path of the chip may be pre-stored in the storage medium, and the netlist corresponding to the at least one critical path may be obtained by directly accessing the storage medium when necessary.

For example, in some embodiments, before the step S101, the implementation method 10 further includes: at least one critical path is selected from the chip 100 as desired. For example, after at least one critical path is selected, a netlist corresponding to the at least one critical path may be stored in a storage medium.

In step S102, according to the netlist corresponding to the first critical path obtained in step S101, the first critical path CP1 is correspondingly found from the working region WR of the chip 100, and first critical path coordinates corresponding to the first critical path CP1 are obtained, where the first critical path coordinates include coordinates of the first critical starting point unit CS1, the first critical ending point unit CE1, and the at least one first critical middle unit CM1 in the working region WR.

Then, in step S103, a placing boundary (bound) of the first test path TP1 is created in the test region TR of the chip 10 different from the working region WR according to the first critical path coordinates. For example, as shown in fig. 5, the first test path TP1 includes a first test start unit TS1, a first test end unit TE1, and at least one first test intermediate unit TM1 located between the first test start unit TS1 and the first test end unit TE 1. It should be noted that fig. 5 shows three first test intermediate units TM1, but the number of the first test intermediate units TM1 is not limited in the embodiments of the present disclosure, and may be, for example, 1, 2, 4 or more. Fig. 5 is a schematic diagram of only the TP1 of the first test path, and for example, a dashed line with an arrow in fig. 5 indicates that the first test path TP1 starts from the first test start unit TS1, passes through the three first test middle units TM1, and reaches the first test end unit TE 1.

For example, as shown in fig. 5, the placing boundary of the first test path TP1 includes a placing boundary 111 corresponding to the first test start point unit TS1 and a placing boundary 112 corresponding to the first test end point unit TE 1. For example, the placement boundary 111 is used to determine the placement position of the first test start unit TS1, and the placement boundary 112 is used to determine the placement position of the first test end unit TE 1.

For example, in some embodiments, as shown in fig. 6, the above step S103 includes the following operation steps.

Step S1031: the sum of the distances between each adjacent two cells in the first critical path CP1 is obtained from the first critical path coordinate calculation and is denoted as a first distance.

Step S1032: a placing boundary of the first test path TP1 is created such that a distance between the first test start point unit TS1 and the first test end point unit TE1 is a first distance.

As shown in fig. 4, the first critical path coordinates, i.e., the coordinates of each cell included in the first critical path CP1, are obtained through step S102. Then, in step S1031, the sum of the distances between each adjacent two cells may be calculated according to the coordinates of the respective cells included in the first critical path CP1, so as to obtain a first distance.

Then, in step S1032, as shown in fig. 5, a placing boundary of the first test path TP1 is created, for example, placing boundaries 111 and 112 corresponding to the first test start point unit TS1 and the first test end point unit TE1 are created respectively, and the distance between the first test start point unit TS1 and the first test end point unit TE1 is made to be a first distance. This is done in order to make the distance between the first test start cell TS1 and the first test end cell TE1 substantially meet certain requirements, thereby laying the foundation for the following layout.

In step S104, the positions of the respective cells included in the first test path TP1 are laid out according to the placing boundaries of the first test path TP1 in the test region TR, thereby completing the physical implementation of the first critical path CP1 in the test region TR. For example, fig. 7 is a detailed schematic diagram of the first test path TP1 shown in fig. 5. For example, as shown in fig. 5 and 7, the first test start cell TS1 may be placed according to the placement boundary 111, the first test end cell TE1 may be placed according to the placement boundary 112, and then the plurality of first test intermediate cells TM1 between the first test start cell TS1 and the first test end cell TE1 may be placed, so that the layout of the cells included in the first test path TP1 may be completed. For example, metal traces ML between the cells may also be provided in subsequent operations to complete the connections between the cells.

It should be noted that, in the embodiment of the present disclosure, implementing a critical path in a working area of a chip in a test area of the chip is equivalent to "copying" the critical path in a test area of the chip to obtain a test path corresponding to the critical path, but the test path obtained by the "copying" is not completely consistent with the original critical path. For example, the implementation step may be performed in a design stage of a chip, and a chip including the test path may actually physically implement the test path after the chip passes through a tape-out.

For example, in some embodiments, in order to make the first test path TP1 better physically implement the first critical path CP1, the first test start point unit TS1 and the first critical start point unit CS1 may be made to employ the same type of register, and the first test end point unit TE1 and the first critical end point unit CE1 may be made to employ the same type of register.

For example, in some embodiments, each cell included in the first critical path CP1 and the first test path TP1 is a gate-level cell, i.e., the above-described implementation method 10 is performed at a logic level of a gate level. The following embodiments are the same and will not be described in detail.

The implementation method 10 provided by the embodiment of the present disclosure implements a test circuit in a test area of a chip, and does not occupy the original hardware resources of the chip, i.e., does not affect the performance of the chip; in addition, by implementing the implementation method 10, it is not necessary to manually place a plurality of units to implement the test paths corresponding to the critical paths, but a uniform method is used to implement at least one test path in the test circuit, so that the deviation of the subsequent test result of the test circuit can be reduced or eliminated, and the quality of the test result can be ensured.

In some embodiments, the above step S104 includes the following operation steps.

Step S1041: the positions of the respective cells included in the first test path TP1 are automatically laid out in the test region TR according to the laying boundary of the first test path TP1 using an automatic layout tool.

For example, as shown in fig. 5 and 7, the automatic layout and routing tool may place the first test start cell TS1 according to the placement boundary 111, place the first test end cell TE1 according to the placement boundary 112, and then automatically place the plurality of first test intermediate cells TM1 between the first test start cell TS1 and the first test end cell TE1, thereby completing the automatic layout of the positions of the respective cells included in the first test path TP 1.

For example, the automatic placement and routing tool may be a tool in the chip design software, for example, the automatic placement and routing tool may be a tool created by a designer according to design requirements, or a tool with versatility included in the chip design software.

In the implementation method 10 provided in some embodiments of the present disclosure, the automatic placement of the locations of the cells included in the first test path TP1 by using an automatic placement and routing tool may improve the efficiency of the implementation method 10.

For example, in other embodiments, the step S104 further includes the following steps.

Step S1042: after the operation of the automatic layout is completed, the positions of the respective cells included in the first test path TP1 are adjusted so that the relative positional relationship of the respective cells included in the first test path TP1 is closer to the relative positional relationship of the respective cells included in the first critical path CP1 than before the adjustment, and then the positions of the respective cells included in the first test path TP1 are fixed.

For example, after the automatic layout of the cells included in the first test path TP1 is completed, in step S1041, the relative positions of the cells included in the first test path TP1 may be adjusted, for example, fine-tuned, in step S1042 so that the relative positional relationship of the cells included in the first test path TP1 is closer to the relative positional relationship of the cells included in the first critical path CP1, that is, the first test path TP1 is made more similar to the "copied" first critical path CP1, and then the positions of the cells included in the first test path TP1 are fixed. The positions of the cells included in the first test path TP1 are fixed to avoid the influence of other subsequent operations on the first test path TP 1.

In the implementation method 10 provided in some embodiments of the present disclosure, by adjusting the relative positions of the units included in the first test path TP1 and fixing the positions of the units, the implemented first test path TP1 may be more similar to the corresponding first critical path CP1, so that the accuracy of the subsequent test result of the test circuit may be improved, and the quality of the test result may be ensured.

In the implementation method 10 provided in the foregoing embodiments, the first critical path CP1 and the first test path TP1 are taken as examples and described, for example, in the implementation method 10 provided in at least one embodiment, as shown in fig. 9, fig. 10, fig. 11, and fig. 12, the at least one critical path may further include one or more other critical paths, for example, a second critical path CP2 is included, the second critical path CP2 includes a second critical start point unit CS2, a second critical end point unit CE2, and at least one second critical intermediate unit CM2 located between the second critical start point unit CS2 and the second critical end point unit CE2, and the at least one test path further includes a second test path TP 2. For example, fig. 10 is a detailed schematic diagram of an example of the second critical path CP2 shown in fig. 9, fig. 11 is a detailed schematic diagram of the second test path TP2 shown in fig. 9, and fig. 12 is a schematic diagram of a layout of the first test path TP1 and the second test path TP 2. As shown in fig. 8, the implementation method 10 further includes the following operation steps.

Step S105: according to the netlist corresponding to the second critical path CP2, correspondingly finding a second critical path CP2 from the working region WR of the chip 100, and obtaining second critical path coordinates corresponding to the second critical path CP2, where the second critical path coordinates include coordinates of a second critical start point unit CS2, a second critical end point unit CE2, and at least one second critical middle unit CM2 in the working region.

Step S106: a pose boundary of the second test path TP2 is created in the test area TR according to the second critical path coordinates, the second test path TP2 including a second test start unit TS2, a second test end unit TE2, and at least one second test middle unit TM2 located between the second test start unit TS2 and the second test end unit TE 2. For example, as shown in fig. 11, the placing boundary of the second test path TP2 includes the placing boundary 211 corresponding to the second test start point unit TS2 and the placing boundary 212 corresponding to the second test end point unit TE 2.

Step S107: the positions of the respective cells comprised by the second test path TP2 are laid out in the test area TR according to the lying boundaries of the second test path TP2, thereby completing the physical realization of the second critical path CP2 in the test area TR.

The operations of steps S105, S106, and S107 are similar to those of steps S102, S103, and S104, respectively, and are not described herein again. For example, step S105 and step S102 may be performed simultaneously, step S106 and step S103 may be performed simultaneously, and step S107 and step S104 may be performed simultaneously.

For example, as shown in fig. 12, a connection line from the first test start cell TS1 to the first test end cell TE1 is referred to as a first connection line CL1, a connection line from the second test start cell TS2 to the second test end cell TE2 is referred to as a second connection line CL2, and the first connection line CL1 crosses the second connection line CL 2.

In the implementation method 10 provided by some embodiments of the present disclosure, when the respective cells included in the first test path TP1 and the second test path TP2 are laid out, the first connecting line CL1 and the second connecting line CL2 intersect, so that the layout of the first test path TP1 and the second test path TP2 implemented in the test region TR can be made more compact, and thus the layout space occupied by the test circuit can be reduced.

It should be noted here that fig. 12 is only a schematic diagram of a layout, and the intersection of the first connection line CL1 and the second connection line CL2 in fig. 12 only represents the relative position relationship of the cells in the first test path TP1 and the second test path TP2 when the cells are laid out, but does not represent the cells included in the first test path TP1 and the metal trace ML shown in fig. 7 directly contacting the cells included in the second test path TP2 shown in fig. 10 and the metal trace ML, and the first test path TP1 and the second test path TP2 implemented by implementing the method 10 do not overlap in physical space, for example, different cells and metal traces ML may be arranged in different layers of a chip.

In the implementation method 10 provided in some embodiments of the present disclosure, as shown in fig. 13, after the step S104 or the step S107 is completed, the implementation method 10 may further include the following operation steps.

Step S108: and obtaining a time sequence constraint file corresponding to at least one critical path.

Step S109: and winding the metal wires in the test circuit according to the time sequence constraint file.

In step S108, for example, a timing constraint file corresponding to the first critical path CP1 is obtained, for example, the timing constraint file defines timing conditions that the first critical path CP1 needs to satisfy when transmitting signals, for example, conditions that the delay of the first critical path CP1 needs to satisfy when transmitting signals.

Then, in step S109, for example, the metal wire of the first test path TP1 in the test circuit is routed according to the timing constraint file obtained in step S108, and the timing constraint file may affect the total length of the routing. For example, as shown in fig. 7, metal traces ML between cells included in first test path TP1 are routed, for example, these metal traces ML may pass through different metal layers of the chip when being routed.

Similarly, the second critical path CP2 and the corresponding second test path TP2 can be operated in the same manner as described above, so that the routing of the metal trace ML in the second test path TP2 is completed as shown in fig. 11. If other critical paths and corresponding test paths are included, the operations of step S108 and step S109 can be adopted to complete the routing operation for all metal traces in the test circuit, and details are not repeated here.

For example, the above operations S101-S109 are all performed during the chip design stage. For example, after the above operation steps are completed, a test circuit is implemented in the test area of the chip, and then the test circuit can be actually and physically implemented after the chip is taped.

At least one embodiment of the present disclosure also provides an adaptive voltage and frequency adjustment method 20 for a chip, as shown in fig. 14, the method 20 includes the following operation steps.

Step S210: physical implementation of at least one critical path of the chip 100 is accomplished in the test region TR using any of the implementation methods 10 provided by the embodiments of the present disclosure to form a test circuit.

Step S220: the test circuit is subjected to a delay test to obtain the operating frequency of the chip 100.

Step S230: the operating voltage of the chip 100 is adjusted according to the operating frequency of the chip 100.

For example, when the chip 100 is in operation, in step S220, performing a delay test on the test circuit includes performing a delay test on all test paths included in the test circuit to obtain delay data of each test path, and then processing all delay data by using a certain algorithm to obtain an operating frequency of the chip 100.

Then, in step S230, the operating voltage of the chip 100 is adjusted according to the operating frequency of the chip 100 obtained in step S220, for example, the operating voltage of the chip 100 may also be adjusted in combination with the operating frequency of the chip 100 and the node temperature. For example, if the operating frequency of the chip 100 has exceeded demand, the operating voltage of the chip 100 may be reduced; if the operating frequency of the chip 100 does not meet the requirement, the operating voltage of the chip 100 may be increased. In addition, if the node temperature of the chip 100 exceeds the set threshold, the operating voltage of the chip 100 can be reduced to avoid the chip 100 from being damaged due to the over-high temperature of the chip 100.

The adaptive voltage and frequency adjusting method 20 for a chip provided by the embodiment of the disclosure can dynamically adjust the working voltage of the chip when the chip works, so that the balance between the performance and the power consumption of the chip can achieve the best effect.

At least one embodiment of the present disclosure further provides an implementation apparatus 300 for a test circuit for adaptive voltage and frequency adjustment of a chip, where the test circuit includes at least one test path, and the at least one test path includes a first test path, as shown in fig. 15, and the implementation apparatus 300 includes a first obtaining module 310, a second obtaining module 320, a creating module 330, and a layout module 340.

For example, the first obtaining module 310 is configured to obtain a netlist corresponding to at least one critical path for implementing a chip, where the at least one critical path includes a first critical path including a first critical start point unit, a first critical end point unit, and at least one first critical middle unit located between the first critical start point unit and the first critical end point unit. Namely, the first obtaining module 310 is configured to execute the above step S101.

The second obtaining module 320 is configured to correspondingly find a first critical path from the working area of the chip according to the netlist corresponding to the first critical path, and obtain first critical path coordinates corresponding to the first critical path, where the first critical path coordinates include coordinates of a first critical start unit, a first critical end unit, and at least one first critical middle unit in the working area. I.e. the second obtaining module 320 is configured to perform the above step S102.

The creating module 330 is configured to create a placing boundary of a first test path in a test area of the chip different from the working area according to the first critical path coordinates, the first test path including a first test start unit, a first test end unit, and at least one first test intermediate unit located between the first test start unit and the first test end unit. I.e. the creation module 330 is configured to perform step S103 described above.

The layout module 340 is configured to layout, in the test area, the positions of the respective cells included in the first test path according to the placement boundary of the first test path, so as to complete the physical implementation of the first critical path in the test area. I.e. the creation module 340 is configured to perform step S104 described above.

In at least one embodiment, as shown in FIG. 16, the creation module 330 includes a calculation module 331 and a creation sub-module 332.

The calculation module 331 is configured to calculate and obtain a sum of distances between every two adjacent cells in the first critical path according to the first critical path coordinates, and to note the first distance. I.e. the calculation module 331 is configured to perform the above step S1031.

The creation sub-module 332 is configured to create a placing boundary of the first test path such that a distance between the first test start point unit and the first test end point unit is a first distance. I.e., the creation submodule 332 is configured to perform the above-described step S1032.

At least one embodiment of the present disclosure also provides an adaptive voltage and frequency adjusting apparatus 400 for a chip, for example, as shown in fig. 17, the apparatus 400 includes an implementation module 410, a test module 420, and an adjusting module 430.

For example, the implementation module 410 is configured to implement the physical implementation of the at least one critical path of the chip in the test area to form the test circuit using any of the implementation methods 10 provided by the embodiments of the present disclosure.

The test module 420 is configured to perform a delay test on the test circuit to obtain an operating frequency of the chip.

The adjusting module 430 is configured to adjust an operating voltage of the chip according to an operating frequency of the chip.

Since details of the operation of the apparatuses 300 and 400 have been introduced in the above description of the implementation of the method 10 and the method 20, the details are not repeated here for brevity, and the related details can refer to the above description of fig. 2 to 14.

It should be noted that each of the modules in the apparatuses shown in fig. 15 to 17 may be respectively configured as software, hardware, firmware or any combination of the above for performing a specific function. For example, the modules may correspond to an application specific integrated circuit, to pure software code, or to a combination of software and hardware. By way of example, and not limitation, the devices described with reference to fig. 15-17 may be a PC computer, tablet device, personal digital assistant, smartphone, web application, or other device capable of executing program instructions.

In addition, although the apparatuses 300 and 400 are described above as being divided into modules for respectively performing the corresponding processes, it is apparent to those skilled in the art that the processes performed by the respective modules may be performed without any specific division of the modules in the apparatuses or without explicit delimitation between the modules. Furthermore, the apparatus described above with reference to fig. 15-17 is not limited to include the above-described modules, but some other modules (e.g., a storage module, a data processing module, etc.) may also be added as needed, or the above modules may also be combined.

At least one embodiment of the present disclosure also provides an adaptive voltage and frequency scaling apparatus for a chip, the adaptive voltage and frequency scaling apparatus comprising a processor and a memory; the memory includes one or more computer program modules; one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including implementing methods 10 and 20 provided for implementing the embodiments of the present disclosure described above.

Fig. 18 is a schematic block diagram of an adaptive voltage and frequency adjusting apparatus according to at least one embodiment of the present disclosure. As shown in fig. 18, the adaptive voltage and frequency adjusting apparatus 500 includes a processor 510 and a memory 520. Memory 520 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules). Processor 510 is configured to execute non-transitory computer readable instructions, which when executed by processor 510 may perform one or more of the steps described above to implement methods 10 and 20. The memory 520 and the processor 510 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, processor 510 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP) or other form of processing unit having data processing capabilities and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be an X86 or ARM architecture, or the like. The processor 510 may be a general purpose processor or a special purpose processor that may control other components in the adaptive voltage and frequency scaling device 500 to perform desired functions.

For example, memory 520 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 510 to implement various functions of device 500. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description about the implementation method 10 and the method 20 for specific functions and technical effects of the adaptive voltage and frequency adjusting apparatus 500, and details are not described herein again.

Fig. 19 is a schematic block diagram of another adaptive voltage and frequency scaling apparatus provided in some embodiments of the present disclosure. The adaptive voltage and frequency scaling apparatus 800 is, for example, suitable for use in implementing the methods 10 and 20 provided by the embodiments of the present disclosure. It should be noted that the adaptive voltage and frequency adjusting apparatus 800 shown in fig. 19 is only an example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 19, the adaptive voltage and frequency adjusting apparatus 800 may include a processing device (e.g., a central processing unit, a graphic processor, etc.) 810 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)820 or a program loaded from a storage device 880 into a Random Access Memory (RAM) 830. In the RAM 830, various programs and data necessary for the operation of the adaptive voltage and frequency adjusting apparatus 800 are also stored. The processing device 810, the ROM 820, and the RAM 830 are connected to each other by a bus 840. An input/output (I/O) interface 850 is also connected to bus 840.

Generally, the following devices may be connected to the I/O interface 850: input devices 860 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 870 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, or the like; storage 880 including, for example, magnetic tape, hard disk, and so forth; and a communication device 890. The communication device 890 may allow the adaptive voltage and frequency adjusting apparatus 800 to communicate with other electronic devices wirelessly or by wire to exchange data. While fig. 19 illustrates the adaptive voltage and frequency scaling apparatus 800 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided, and that the adaptive voltage and frequency scaling apparatus 800 may alternatively be implemented or provided with more or fewer means.

For example, the implementation method 10 and the method 20 provided by the embodiments of the present disclosure may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the implementation of the method 10 as well as the method 20. In such an embodiment, the computer program may be downloaded and installed from a network through communications device 890, or installed from storage device 880, or installed from ROM 820. When the computer program is executed by the processing device 810, the implementation method 10 and the method 20 provided by the embodiment of the disclosure may be executed.

At least one embodiment of the present disclosure also provides a storage medium for storing non-transitory computer-readable instructions, which when executed by a computer, can implement any of the implementation methods 10 and 20 provided by the embodiments of the present disclosure.

Fig. 20 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 20, the storage medium 600 is used to store non-transitory computer readable instructions 610. For example, the non-transitory computer readable instructions 610, when executed by a computer, may perform one or more steps according to the implementation method 10 and method 20 described above.

For example, the storage medium 600 may be applied to the adaptive voltage and frequency adjusting apparatus 500 described above. For example, the storage medium 600 may be the memory 520 in the adaptive voltage and frequency adjusting apparatus 500 shown in fig. 18. For example, the relevant description about the storage medium 600 may refer to the corresponding description of the memory 520 in the adaptive voltage and frequency adjusting apparatus 500 shown in fig. 18, and will not be described herein again.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (16)

1. A method of implementing a test circuit for adaptive voltage and frequency regulation of a chip, wherein the test circuit includes at least one test path, the at least one test path including a first test path, the method comprising:

obtaining a netlist corresponding to at least one critical path for realizing the chip, wherein the at least one critical path comprises a first critical path, and the first critical path comprises a first critical starting point unit, a first critical ending point unit and at least one first critical intermediate unit positioned between the first critical starting point unit and the first critical ending point unit;

correspondingly finding the first critical path from a working area of the chip according to the netlist corresponding to the first critical path, and obtaining first critical path coordinates corresponding to the first critical path, wherein the first critical path coordinates comprise coordinates of the first critical start unit, the first critical end unit and the at least one first critical intermediate unit in the working area;

establishing a placing boundary of the first test path in a test area, different from the working area, of the chip according to the first critical path coordinate, wherein the first test path comprises a first test starting point unit, a first test end point unit and at least one first test intermediate unit positioned between the first test starting point unit and the first test end point unit; and

and the positions of all units included in the first test path are distributed in the test area according to the placing boundary of the first test path, so that the physical realization of the first critical path is completed in the test area.

2. The implementation method of claim 1, wherein creating a parking boundary of the first test path in a test area of the chip different from the working area according to the first critical path coordinates comprises:

calculating and obtaining the sum of the distances between every two adjacent units in the first critical path according to the first critical path coordinates, and recording the sum as a first distance; and

and creating a placing boundary of the first test path, so that the distance between the first test starting point unit and the first test end point unit is the first distance.

3. The implementation method of claim 1, wherein the laying out, in the test area, the positions of the cells included in the first test path according to the placing boundary of the first test path includes:

and automatically laying out the positions of all units included in the first test path in the test area according to the placement boundary of the first test path by adopting an automatic layout and wiring tool.

4. The implementation method of claim 3, wherein the layout of the positions of the cells included in the first test path in the test area according to the placement boundary of the first test path further comprises:

after the automatic layout operation is completed, adjusting the positions of the units included in the first test path so that the relative positional relationship of the units included in the first test path is closer to the relative positional relationship of the units included in the first critical path than before the adjustment, and then fixing the positions of the units included in the first test path.

5. The implementation method of any one of claims 1-4, wherein the at least one critical path further comprises a second critical path, the second critical path comprises a second critical starting point unit, a second critical ending point unit, and at least one second critical intermediate unit located between the second critical starting point unit and the second critical ending point unit, the at least one test path further comprises a second test path, the implementation method further comprising:

correspondingly finding the second critical path from the working area of the chip according to the netlist corresponding to the second critical path, and obtaining second critical path coordinates corresponding to the second critical path, wherein the second critical path coordinates comprise coordinates of the second critical start unit, the second critical end unit and the at least one second critical middle unit in the working area;

creating a placing boundary of the second test path in the test area according to the second critical path coordinate, wherein the second test path comprises a second test starting point unit, a second test end point unit and at least one second test intermediate unit positioned between the second test starting point unit and the second test end point unit; and

the positions of all units included in the second testing path are distributed in the testing area according to the placing boundary of the second testing path, so that the physical realization of the second critical path is completed in the testing area;

wherein a line from the first test start point unit to the first test end point unit is referred to as a first line, a line from the second test start point unit to the second test end point unit is referred to as a second line, and the first line crosses the second line.

6. The implementation method of any one of claims 1 to 4, wherein after the operation of laying out the positions of the cells included in the first test path according to the placement boundary of the first test path in the test area is completed, the implementation method further includes:

obtaining a time sequence constraint file corresponding to the at least one critical path; and

and winding the metal wires in the test circuit according to the time sequence constraint file.

7. The implementation method of any one of claims 1 to 4, wherein before obtaining the netlist corresponding to the at least one critical path for implementing the chip, the implementation method further comprises:

and selecting the at least one critical path from the chip according to the requirement.

8. The implementation method of any one of claims 1 to 4, wherein the first test start point unit and the first critical start point unit employ the same type of register and the first test end point unit and the first critical end point unit employ the same type of register.

9. The method according to any one of claims 1 to 4, wherein the working area is an area required by the chip to perform its own function, and the test area is an area other than the working area in the chip, and is used for implementing the test circuit.

10. The implementation method of any one of claims 1-4, wherein each cell included in the first critical path and the first test path is a gate level cell.

11. An adaptive voltage and frequency regulation method for a chip, comprising:

-performing a physical realization of said at least one critical path of said chip in said test area using the realization method of any of claims 1-10 to form said test circuit;

carrying out time delay test on the test circuit to obtain the working frequency of the chip; and

and adjusting the working voltage of the chip according to the working frequency of the chip.

12. An apparatus for implementing a test circuit for adaptive voltage and frequency regulation of a chip, wherein the test circuit includes at least one test path including a first test path, the apparatus comprising:

a first obtaining module configured to obtain a netlist corresponding to at least one critical path for implementing the chip, where the at least one critical path includes a first critical path, and the first critical path includes a first critical start point unit, a first critical end point unit, and at least one first critical intermediate unit located between the first critical start point unit and the first critical end point unit;

a second obtaining module, configured to correspondingly find the first critical path from a working area of the chip according to the netlist corresponding to the first critical path, and obtain first critical path coordinates corresponding to the first critical path, where the first critical path coordinates include coordinates of the first critical start unit, the first critical end unit, and the at least one first critical intermediate unit in the working area;

a creating module configured to create a placing boundary of the first test path in a test area of the chip different from the working area according to the first critical path coordinate, wherein the first test path includes a first test starting point unit, a first test ending point unit and at least one first test intermediate unit located between the first test starting point unit and the first test ending point unit; and

and the layout module is configured to layout the positions of the units included in the first test path in the test area according to the placing boundary of the first test path, so that the physical implementation of the first critical path is completed in the test area.

13. The implementation apparatus of claim 12, wherein the creation module comprises:

a calculation module configured to calculate and obtain a sum of distances between every two adjacent units in the first critical path according to the first critical path coordinates, and record the sum as a first distance; and

a creating sub-module configured to create a placing boundary of the first test path so that a distance between the first test start point unit and the first test end point unit is the first distance.

14. An adaptive voltage and frequency scaling apparatus for a chip, comprising:

an implementation module configured to implement the physical implementation of the at least one critical path of the chip in the test area to form the test circuit using the implementation method of any one of claims 1 to 10;

the test module is configured to perform delay test on the test circuit to obtain the working frequency of the chip; and

the adjusting module is configured to adjust the working voltage of the chip according to the working frequency of the chip.

15. An adaptive voltage and frequency scaling apparatus for a chip, comprising:

a processor;

a memory including one or more computer program modules;

wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising an implementation method for implementing the test circuit for adaptive voltage and frequency scaling of a chip of any of claims 1-10 or for implementing the method for adaptive voltage and frequency scaling of a chip of claim 11.

16. A storage medium for storing non-transitory computer-readable instructions which, when executed by a computer, may implement the method of implementing the test circuit for adaptive voltage and frequency regulation of a chip of any one of claims 1 to 10, or the method of implementing the adaptive voltage and frequency regulation of a chip of claim 11.

Images