CN106156375A - A kind of memorizer compiler joining method and memorizer - Google Patents

Abstract

This application discloses a kind of memorizer compiler joining method, comprise determining that signal is driven into the number n of the Fin of the driving MOS that the delay time of distalmost end memory element drives with the columns n of memory element and wordline by wordline_WLDBetween functional relationship；N array storage unit is divided into i section, at n_WLDSpan in be calculated the time delay tn/i of n/i array storage unit；When described time delay tn/i is less than the first preset value, obtain above-mentioned n corresponding for time delay tn/i_WLD, it is designated as n_meet；That inserts a buffer, wordline driving and each buffer between every two sections of memory element is driven to n_meetIndividual Fin；Assembled domain, it is seen that the wordline driving of memory element using said method to obtain is optimal value with the number of the Fin of buffer, therefore enhances the area utilization of memorizer, reduces area loss.

Description

A kind of memorizer compiler joining method and memorizer

Technical field

The application relates to memory technology field, more particularly, it relates to a kind of memorizer compiler splicing Method and memorizer.

Background technology

Existing memorizer compiler in the design process, is generally divided into each functional module memorizer (leaf cell), depending on the circuit size in functional module is according to the worst case of array.Then program is used According to configuration parameter, splicing each functional module, the most multiple functional modules are combined into a memorizer. In this process, the large-size device in memorizer is in accordance with setting under the worst case of array, The line number of array and the change of columns can not be followed the trail of, therefore, use technical scheme of the prior art to generate Area (Performance, power, area the are called for short PPA) waste of memorizer, also can increase simultaneously Power consumption of memory.

Summary of the invention

In view of this, the application provides a kind of memorizer compiler joining method, is used for solving prior art The problem of the area loss of middle memorizer.

To achieve these goals, it is proposed that scheme as follows:

A kind of memorizer compiler joining method, including:

Determine that signal is driven into the delay time of distalmost end memory element and the columns n of memory element by wordline And the number n of the Fin of the driving MOS of wordline driving_WLDBetween functional relationship, wherein said n_WLD It it is a dispersion number；

Described n array storage unit is divided into default section, at n_WLDSpan in, according to described letter Number relation calculates the minimum delay time of every section of memory element, when described minimum delay time is pre-less than first If during value, obtain the n that described minimum delay time is corresponding_WLD, it is designated as preferred value, described preferred value It is wordline in described memorizer and drives the driving MOS's of the buffer between every two sections of memory element Fin number；

Assembled Fin is that the wordline of preferred value drives and the domain of buffer.

Preferably, above-mentioned memorizer compiler joining method, also include:

When described minimum delay time is not less than the first preset value, the equal segmentation of described n array storage unit Number adds 1, until at n_WLDSpan in, the minimum delay time of every section of memory element be less than first Preset value.

Preferably, in above-mentioned memorizer compiler joining method, described signal is driven into by memory word line The delay time of distalmost end memory element and the columns n of memory element and wordline drive the Fin's of MOS Number n_WLDBetween functional relationship, for:

$t0=a*b+\frac{n}{n_{\mathrm{WLD}}}a*C_{C\_\mathrm{WL}}+\frac{(n+1)n}{2}{R}_{C\_\mathrm{WL}}{C}_{C\_\mathrm{WL}}=f(n_{\mathrm{WLD}},n);$

Wherein, t0 is that signal is driven into the delay time of distalmost end memory element, R by memory word line_{C_WL} For the resistance value of memory element bit line, C_{C_WL}For the capacitance of memory element bit line, a and b is constant.

Preferably, in above-mentioned memorizer compiler joining method, also include:

Line number m of described memorizer compiler is tracked, particularly as follows:

Calculate the resistance R of the pull-up PMOS of memorizer_{C_PU}With the resistance R writing driving_WRDAnd m The resistance R of line storage unit_{C_BL}The ratio T of sum, wherein, described；Described n_WRD For writing the number of the Fin of the NMOS of driving, c is fixed value；

At n_WRDSpan in, calculate the driving of writing making described ratio T more than the second preset value The number of the minimum Fin of NMOS, is designated as n_WRD1；

Assembled Fin is n_WRD1The domain writing driving.

Preferably, in above-mentioned memorizer compiler joining method, also include:

Use sequential control circuit that line number m and the columns n of described memorizer compiler are tracked, tool Body is:

Determine the time delay t1 of sequential control circuit of memorizer and functional module number p of inverter drive with And the number n of the Fin of phase inverter_DriverBetween functional relationship, wherein said n_DriverIt it is a dispersion number；

Ask at described n_DriverSpan in so that Fin's when described time delay t1 meets timing requirements Minimal amount, is designated as n_Driver1；

Assembled Fin is n_Driver1Sequential control circuit domain.

Preferably, in above-mentioned memorizer compiler joining method, the time delay t1 of described sequential control circuit with Functional module number p of inverter drive and the number n of the Fin of phase inverter_DriverBetween functional relationship be $t1=d*e+\frac{p}{n_{\mathrm{Driver}}}d*C_{\mathrm{leafcell}}+\frac{(p+1)p}{2}{R}_{\mathrm{leafcell}}{C}_{\mathrm{leafcell}},$ Wherein, described d, e are fixed value, described C_leafcell By the electric capacity of the functional module that phase inverter is driven, described R_leafcellThe functional module driven by phase inverter Connection resistances.

A kind of memorizer, described memorizer is spelled for using above-mentioned any one memorizer compiler joining method The memorizer of dress.

From above-mentioned technical scheme it can be seen that memorizer compiler joining method disclosed in the present application, By the columns n of described memorizer compiler is tracked so that the WL Driver of memory element and The number of the Fin of Buffer is optimal value so that the size of described WL Driver and Buffer is optimum, Therefore enhance the area utilization of memorizer, reduce area loss.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below, Accompanying drawing in description is only embodiments of the invention, for those of ordinary skill in the art, not On the premise of paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.

Fig. 1 is the structure chart of existing 3D transistor；

Fig. 2 is the long line model of the WL Driver in memorizer compiler disclosed in the embodiment of the present application；

Fig. 3 is the disclosed stream to the method that the columns of memorizer compiler is tracked of the embodiment of the present application Cheng Tu；

Fig. 4 is the long wire model figure writing driving Write Driver worst case of memorizer compiler；

Fig. 5 is the disclosed method flow being tracked line number m of memorizer compiler of the embodiment of the present application Figure；

Fig. 6 is the structure chart of the sequential tracking circuit of memorizer；

Fig. 7 is the long line illustraton of model that sequential follows the trail of the large scale phase inverter in circuit；

Fig. 8 is that the embodiment of the present application is disclosed uses the sequential control circuit row to described memorizer compiler The flow chart that number m and columns n are tracked.

Detailed description of the invention

The circuit size being directed in memory function module of the prior art is according to the worst case of array Depending on, thus cause the problem of the area loss of memorizer, this application discloses a kind of memorizer compiler Joining method and memorizer.

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing Go out the every other embodiment obtained under creative work premise, broadly fall into the scope of protection of the invention.

Under fin field-effect transistor (Fin Field-Effect Transistor, FinFET) technique, MOS The channel length of device is fixed, and width can only the value of quantification.Therefore user can customize MOS device Size, MOS device can be carried out computer control.The most original memorizer compiler skill Art can be optimized reform under FinFET technique.

As it is shown in figure 1, the FinFET in Fig. 1 is 3D transistor (metal-oxide-semiconductor), see in Fig. 1 The channel length of 3D transistor is fixed value, width can only quantized value, the most described metal-oxide-semiconductor Size is determined by total number of Fin: Fin_Sum=Fin_1Finger* Finger, metal-oxide-semiconductor be sized at one discrete Function, thus can facilitate and process with computer, control domain arrangement, carry out assembled MOS Pipe.Wordline in memorizer compiler drive (WL Driver), write driving (Write Driver), time Sequence is followed the trail of in circuit (Tracking Path) and is provided with large-size device, and described WL Driver is used for driving The wordline of memory element in storage array, described Write Driver is used for driving memory element in storage array Bit line, described Tracking Path is for controlling the sequential of memorizer, and applicant finds to utilize by research The characteristic of FinFET size discrete, can make the size of large-size device carry out line number and columns Follow the trail of, so that the area loss reducing memorizer is possibly realized.

Fig. 2 is the long line model of the WL Driver in memorizer compiler disclosed in the embodiment of the present application. Wherein, R shown in Fig. 2_WLDThe resistance of MOS, C is driven for WL Driver_WLDMOS is driven for WL Driver Electric capacity, R_{C_WL}For the resistance of memory element bit line, C_{C_WL}For the electric capacity of memory element bit line, WL Driver Driving altogether n array storage unit, described t0 is the signal time delay by the memory element of WL Driver to distalmost end Time, described t0=f (n_WLD, n), wherein, described n_WLDThe catalogue number of the Fin of MOS is driven for WL Driver, And described n_WLDIt it is a dispersion number.

Based on described signal by the delay time t0 of the memory element of WL Driver to distalmost end and described WL Driver drives the catalogue number n of the Fin of MOS_WLDAnd the functional relationship between the columns n of memory element, this Shen Please disclose a kind of memorizer compiler joining method, by the columns of memorizer compiler is tracked, Reach to optimize the purpose of the PPA of memorizer compiler.

Fig. 3 is the disclosed method being tracked the columns of memorizer compiler of the embodiment of the present application.

Seeing Fig. 1, the method includes:

The columns n of described memorizer compiler is tracked, particularly as follows:

Step S301: determine that signal is driven into delay time t0 and the storage of distalmost end memory element by wordline The number n of the Fin of the driving MOS that the columns n of unit and wordline drive_WLDBetween functional relationship；

Step S302: described n array storage unit is divided into i section, i=1；

Step S303: at n_WLDSpan in, be calculated the minimum time delay of n/i array storage unit Time tn/i；

Step S304: judge that whether described minimum delay time tn/i is less than the first preset value t_target, if Perform step S306, if it does not, perform step S305, described first preset value t_targetSize according to use Depending on the demand of family:

Step S305: make i=i+1, continues executing with step S303；

At n_WLDSpan in, continue to be calculated the minimum delay time tn/i of n/i array storage unit, Until judging that described minimum delay time tn/i is less than described first preset value t_target；

Step S306: if described minimum delay time tn/i is less than the first preset value t_target, obtain and make institute State the number (n that wordline corresponding when minimum delay time tn/i is minima drives the Fin of MOS_WLD), It is designated as n_meet；

Step S307: insert a buffer Buffer between every two sections of memory element, wordline drives and every The Fin number of the driving of individual described buffer Buffer is n_meet；

Step S308: assembled Fin is n_meetWordline drive and the domain of buffer.

Shown in Fig. 3, first n_WLDIn the number of Fin permits span, obtain n memory element Minimum time delay, if less than target (the first preset value) t_target, then ask in span and meet constraint The minimum Fin value of condition；If greater than the first preset value t_target, then be averaged segmentation, asks every section Minimum time delay, and by every section of minimum time delay and the first preset value t_targetCompare, if less than the first preset value t_target, then seek the minimum Fin value meeting constraints, otherwise continue segmentation and go down until meeting goal constraint (every section of minimum time delay is less than the first preset value t for condition_targetTill).Choose the most always and meet condition Segments and the value of Fin, select the result of optimum always, and therefore every section of time delay overall altogether then exists Meeting also is minimum under constraints.

Wherein, said method can be referred to as greedy algorithm, permissible for this iteration selecting greed Solving with analog simulation, under limited, the discrete value of Fin, Dynamic simulation obtains prolonging of correspondence Time, the time delay obtained is compared with the first preset value, if being less than first and arranging, then terminates imitative Very, then time delay is carried out computing；If more than the first preset value, then described n array storage unit being carried out Segmentation, continues under discrete value, and emulation obtains every section of time delay corresponding to memory element, and follow-up changes Generation by that analogy, when time delay corresponding to every section of memory element is less than the first preset value till.The most every Insert between two sections of memory element and determine WL Driver and Buffer with the value of buffer Buffer, Fin Size.Different columns (n) obtains segments and value n of Fin of correspondence_meet, pass through computer Generating the domain of corresponding WL Driver and Buffer, such memorizer compiler just can follow the trail of columns Change so that the PPA of the WL Driver of each memorizer can be optimum.

See disclosed in the above embodiments of the present application, the columns n of described memorizer compiler is tracked Method, the number of the Fin of WL Driver and Buffer of memory element is optimal value so that The size of described WL Driver and Buffer is optimum, thus enhances the area utilization of memorizer, subtracts Little area loss.

It is understood that see Fig. 2, described it is driven into prolonging of distalmost end memory element by memory word line Time the columns n of time t0 and memory element and wordline drive the number n of Fin of MOS_WLDBetween Functional relationship, for:

$\begin{array}{c}t0=R_{\mathrm{WLD}}{C}_{\mathrm{WLD}}+(R_{\mathrm{WLD}}+R_{C\_\mathrm{WL}})C_{C\_\mathrm{WL}}+(R_{\mathrm{WLD}}+2R_{C\_\mathrm{WL}})C_{C\_\mathrm{WL}}+...+(R_{\mathrm{WLD}}+n{R}_{C\_\mathrm{WL}})C_{C\_\mathrm{WL}}\\ =R_{\mathrm{WLD}}{C}_{\mathrm{WLD}}+n{R}_{\mathrm{WLD}}{C}_{C\_\mathrm{WL}}+\frac{(n+1)n}{2}{R}_{C\_\mathrm{WL}}{C}_{C\_\mathrm{WL}}\end{array}$

If whereinC_WLD=bn_WLD, described a, b are constant, then:

$t0=a*b+\frac{n}{n_{\mathrm{WLD}}}a*C_{C\_\mathrm{WL}}+\frac{(n+1)n}{2}{R}_{C\_\mathrm{WL}}{C}_{C\_\mathrm{WL}}=f(n_{\mathrm{WLD}},n);$

Wherein R_{C_WL}For the resistance value of memory element bit line, C_{C_WL}Capacitance for memory element bit line；

Therefore, described t0 Yu n and n can be tried to achieve_WLDBetween functional relation be: $t0=a*b+\frac{n}{n_{\mathrm{WLD}}}a*C_{C\_\mathrm{WL}}+\frac{(n+1)n}{2}{R}_{C\_\mathrm{WL}}{C}_{C\_\mathrm{WL}}=f(n_{\mathrm{WLD}},n).$

Fig. 4 is the long wire model figure writing driving Write Driver worst case of memorizer compiler.Wherein, Shown R_{C_PU}For the resistance of the pull-up PMOS of memory element, R_{C_BL}For the resistance of memory element BL, C_{C_BL}For the electric capacity of memory element bit line BL (bit line), R_WRDFor writing driving (Write Driver) Resistance, m is the line number of memory element.When needs write upset memory element, the ratio of resistance needs Meet condition:

Wherein said λ_flipIt it is the second preset value.

Wherein, if the number of the Fin of the NMOS of described Write Driver is n_WRD, then, describedDescribed c is constant, and the most above-mentioned formula can be deformed into:

Fig. 5 is the disclosed method stream being tracked line number m of memorizer compiler of the embodiment of the present application Cheng Tu.

It is understood that for the PPA optimizing memorizer further, described memorizer is compiled above-mentioned Translate on the basis of the columns n of device is tracked, it is also possible to line number m of memorizer compiler is tracked, Seeing Fig. 4 and Fig. 5, its detailed process is:

Step S501: calculate the resistance R of the pull-up PMOS of memorizer_{C_PU}Hinder with the resistance writing driving Value R_WRDResistance R with m line storage unit_{C_BL}The ratio T of sum；

Step S502: at n_WRDSpan in, calculate and make described ratio T more than the second preset value The number of minimum Fin of the NMOS writing driving, be designated as n_WRD1；

Step S503: assembled Fin is n_WRD1The domain writing driving.

Visible, it is analyzed by arranging the concrete structure that described memorizer editing machine is write driving, Resistance R to the pull-up PMOS of described memorizer_{C_PU}With the resistance R writing driving_WRDWith m row The resistance R of memory element_{C_BL}The ratio T of sum, meanwhile, analyzes the resistance writing driving described in obtaining Resistance R_WRDNumber n with the Fin of the NMOS of described Write Driver_WRDBetween relation, thus logical Cross to bring into and obtain, number n of the Fin of the NMOS of described Write Driver_WRDAnd between described ratio T Relation, i.e. can be obtained so that minimum n when described ratio T meets pre-conditioned by analytical calculation_WRD's Value, thus reach the purpose that line number m of reservoir compiler is tracked so that described Write Driver Size be optimum, thus further enhancing the area utilization of memorizer, reduce area loss.

Fig. 6 is the structure chart of the sequential tracking circuit of memorizer.Wherein, Cell memory function mould in figure Block, described WL FMS is the timing triggers of WL signal, and described SA FSM is SAEN signal Timing triggers.

Seeing Fig. 6, described sequential follows the trail of circuit operationally, when shown CK end gets clock signal During rising edge, trigger WLEN and be set to ' 1 ' so that shown DWL is also set to ' 1 ' unlatching phase inverter, RBL starts electric discharge, finally makes WL_END become ' 1 ' replacement WL FSM, corresponding WLEN Putting ' 0 ', DWL puts ' 0 ', and RBL reverts to ' 1 ', and WL_END puts ' 0 ', terminates WL Sequential follow the trail of；When WL_END is set to ' 1 ', the sequential opening SA is followed the trail of, and SAEN puts ' 1 ', SA_END puts ' 1 ' replacement SA FSM and makes SAEN be ' 0 ', and then SA_END also becomes ' 0 ', The sequential terminating SA is followed the trail of.Driving one long line of inverter drive of WLEN, its signal lag is subject to The impact of the line number (m) of storage array in memorizer；Drive one long line of inverter drive of RBL, Time delay is affected by the line number (m) of storage array in memorizer equally；The inverter drive driving SAEN is long Line, time delay is affected by the columns (n) of storage array in memorizer；Drive the phase inverter of SA_END Driving long line, time delay is affected by storing columns (n) in memorizer equally.And above-mentioned these phase inverters It is large-size device, affects the overall sequential of memorizer.The sequential of existing memorizer compiler is followed the trail of The worst case of array is only designed by circuit, so causes array sequential in the case of other to be followed the trail of also It not optimal so that it is not optimum that sequential follows the trail of the PPA of circuit, adds the area of memorizer Waste.

Fig. 7 is the long line model that sequential follows the trail of the large scale phase inverter in circuit.

Being directed to sequential in memorizer and following the trail of the PPA of circuit is not optimum problem, applicant establish as Long line model shown in Fig. 7, wherein, shown R_DriverFor driving the MOS resistance of phase inverter, shown C_DriverFor driving the mos capacitance of phase inverter, described R_leafcellFor the connection resistances of memory function module, Described C_leafcellFor the electric capacity of memory function module, the memorizer that described p is connected by driving phase inverter The number of functional module, described time delay t1 is by by driving phase inverter to the farthest merit driving phase inverter to be connected The delay time of energy module.

Can be obtained by computational analysis, described time delay:

$\begin{array}{c}t1=R_{\mathrm{Driver}}{C}_{\mathrm{Driver}}+(R_{\mathrm{Driver}}+R_{\mathrm{leafcell}})C_{\mathrm{leafcell}}+(R_{\mathrm{Driver}}+2R_{\mathrm{leafcell}})C_{\mathrm{leafcell}}+...+(R_{\mathrm{Driver}}+p{R}_{\mathrm{leafcell}})C_{\mathrm{leafcell}}\\ =R_{\mathrm{Driver}}{C}_{\mathrm{Driver}}+p{R}_{\mathrm{Driver}}{C}_{\mathrm{leafcell}}+\frac{(p+1)p}{2}{R}_{\mathrm{leafcell}}{C}_{\mathrm{leafcell}}\end{array}$

If driving the number of the Fin of MOS in above-mentioned long line is n_Driver, then describedC_Driver=e*n_Driver, described d, e are constant.The most above-mentioned formula can be deformed into: $t1=d*e+\frac{p}{n_{\mathrm{Driver}}}d*C_{\mathrm{leafcell}}+\frac{(p+1)p}{2}{R}_{\mathrm{leafcell}}{C}_{\mathrm{leafcell}}=f(n_{\mathrm{Driver}},p);$

By above-mentioned formula, described at n_DriverSpan in, try to achieve the minimum meeting delay requirement The size of driving MOS, and be assembled into corresponding domain, so that what above-mentioned long line drove PPA optimizes, and this solution procedure can solve with analog simulation: at discrete n_DriverSize In span, the time delay t value of simulated measurement correspondingly-sized, compare timing requirements, the condition of being met obtains The n of minimum dimension_Driver, and assembled corresponding domain.Therefore follow the trail of sequential and follow the trail of line number and the columns of circuit Change, the sequential of each memorizer of generation is followed the trail of circuit from being in harmony, thus is reduced memorizer Area loss.

Concrete, see Fig. 8, the above embodiments of the present application use sequential control circuit to described memorizer The method that line number m of compiler and columns n are tracked, concretely:

Step S801: determine the time delay t1 of the sequential control circuit of memorizer and the function mould of inverter drive The number n of the Fin of block number p and phase inverter_DriverBetween functional relationship, wherein said n_DriverIt is one Dispersion number；

Step S802: ask at described n_DriverSpan in so that described time delay t1 for meet preset bar The minimal amount of Fin during part, is designated as n_Driver1, i.e. make described t1 less than the minimum of Fin during predetermined value Number；

Step S803: assembled Fin is n_Driver1Sequential control circuit domain.

It is understood that corresponding to method disclosed in the above embodiments of the present application, disclosed herein as well is A kind of memorizer using any one method above-mentioned to make.

A kind of memorizer, it is characterised in that described memorizer is for using the claims 1-5 any one The memorizer that memorizer compiler joining method is assembled.

It is understood that memorizer disclosed in the embodiment of the present application can use the WL in memorizer The columns of memorizer is tracked and/or uses Writer Driver to chase after the line number of memorizer by Driver Line number and columns are all tracked by track and/or employing sequential control circuit, therefore, it is possible to in memorizer Large-size device is tracked customization, so that the overall PPA of each memorizer is optimum.

In this specification, each embodiment uses the mode gone forward one by one to describe, and each embodiment stresses Being the difference with other embodiments, between each embodiment, identical similar portion sees mutually.

Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses The present invention.Multiple amendment to these embodiments will be aobvious and easy for those skilled in the art See, generic principles defined herein can without departing from the spirit or scope of the present invention, Realize in other embodiments.Therefore, the present invention is not intended to be limited to the embodiments shown herein, And it is to fit to the widest scope consistent with principles disclosed herein and features of novelty.

Claims (7)

1. a memorizer compiler joining method, it is characterised in that including:

Determine that signal is driven into the delay time of distalmost end memory element and the columns n of memory element by wordline And the number n of the Fin of the driving MOS of wordline driving_WLDBetween functional relationship, described n_WLDFor One dispersion number；

Described n array storage unit is divided into default section, at n_WLDSpan in, according to described letter Number relation calculates the minimum delay time of every section of memory element, when described minimum delay time is pre-less than first If during value, obtain the n that described minimum delay time is corresponding_WLD, it is designated as preferred value, described preferred value It is wordline in described memorizer and drives the driving MOS's of the buffer between every two sections of memory element Fin number；

Assembled Fin is that the wordline of preferred value drives and the domain of buffer.

Memorizer compiler joining method the most according to claim 1, it is characterised in that also include:

When described minimum delay time is not less than the first preset value, the equal segmentation of described n array storage unit Number adds 1, until at n_WLDSpan in, the minimum delay time of every section of memory element be less than first Preset value.

Memorizer compiler joining method the most according to claim 1, it is characterised in that described letter Number by memory word line be driven into the delay time of distalmost end memory element and the columns n of memory element and Wordline drives the number n of the Fin of MOS_WLDBetween functional relationship, for:

$t0=a*b+\frac{n}{n_{\mathrm{WLD}}}a*C_{C\_\mathrm{WL}}+\frac{(n+1)n}{2}{R}_{C\_\mathrm{WL}}{C}_{C\_\mathrm{WL}}=f(n_{\mathrm{WLD}},n);$

Wherein, t0 is that signal is driven into the delay time of distalmost end memory element, R by memory word line_{C_WL} For the resistance value of memory element bit line, C_{C_WL}For the capacitance of memory element bit line, a and b is constant.

Memorizer compiler joining method the most according to claim 1, it is characterised in that also include:

Line number m of described memorizer compiler is tracked, particularly as follows:

Calculate the resistance R of the pull-up PMOS of memorizer_{C_PU}With the resistance R writing driving_WRDAnd m The resistance R of line storage unit_{C_BL}The ratio T of sum, wherein, described；Described n_WRD For writing the number of the Fin of the NMOS of driving, c is fixed value；

At n_WRDSpan in, calculate the driving of writing making described ratio T more than the second preset value The number of the minimum Fin of NMOS, is designated as n_WRD1；

Assembled Fin is n_WRD1The domain writing driving.

Memorizer compiler joining method the most according to claim 1, it is characterised in that also include:

Use sequential control circuit that line number m and the columns n of described memorizer compiler are tracked, tool Body is:

Determine the time delay t1 of sequential control circuit of memorizer and functional module number p of inverter drive with And the number n of the Fin of phase inverter_DriverBetween functional relationship, wherein said n_DriverIt it is a dispersion number；

Ask at described n_DriverSpan in so that the minimum of Fin during described time delay t1 timing requirements Number, is designated as n_Driver1；

Assembled Fin is n_Driver1Sequential control circuit domain.

Memorizer compiler joining method the most according to claim 5, it is characterised in that time described The time delay t1 of sequence control circuit and functional module number p of inverter drive and the number of the Fin of phase inverter Mesh n_DriverBetween functional relationship be $t1=d*e+\frac{p}{n_{\mathrm{Driver}}}d*C_{\mathrm{leafcell}}+\frac{(p+1)p}{2}{R}_{\mathrm{leafcell}}{C}_{\mathrm{leadcell}},$ Wherein, described D, e are fixed value, described C_leafcellBy the electric capacity of the functional module that phase inverter is driven, described R_leafcellFor instead The connection resistances of the functional module that phase device is driven.

7. a memorizer, it is characterised in that described memorizer is for using the claims 1-6 any The memorizer that one memorizer compiler joining method is assembled.