CN103106294B - A kind of domain programmed method for static RAM compiler - Google Patents
A kind of domain programmed method for static RAM compiler Download PDFInfo
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Abstract
The invention provides a kind of domain programmed method for static RAM compiler, comprising: the position of needs of programming in domain makes marks, the content of text of mark or figure contain the information generated required for domain according to certain rule; Existing mark in compiler identification domain, and the information recording the programming needs such as its coordinate, content of text, dimension of picture; Compiler, according to the information extracted, by searching or calculate the position finding needs to operate, and carries out domain operation in this position.The information that domain programming needs, to be labeled as carrier in domain, is directly embedded in domain by the present invention while not affecting normal layout design, does not need domain by the time to add after completing again, can shorten the time of layout design; The information that automatic extraction domain programming needs, saves manpower and time; During domain programming, program operates according to mark, does not need to relate to concrete layout information, makes compiler have greater flexibility and portability.
Description
[technical field]
The present invention relates to static RAM design field, particularly a kind of domain programmed method for static RAM compiler.
[background technology]
Static RAM (SRAM) is a kind of common random access memory, is widely used in integrated circuit fields.Wherein be applicable to the static RAM IP(intellecture property of integrated circuit SOC (system on a chip) (SoC:SystemonChip): IntelligentProperty) be most widely used at present, become one of most basic IP of integrated circuit technology line.SRAMIP generally pays user with the form of compiler and uses, and user can generate the SRAM of specified vol, shape and performance according to the demand compiler of oneself.
SRAM compiler can generate the several data file comprising domain.It is module splicing that compiler generates the ultimate principle of domain, is spliced to form high-level module from elementary cell, and then splices these modules until finally form a complete domain.Traditional SRAM compiler, can by the layout information needed for program in the process of splicing with this domain of programming realization, and such as coordinate, size etc., directly write in program, causes once domain is changed, and needs to remodify and program compiler.In addition the layout information needed for program is obtained by designer's manual measurement after completing layout design in the SRAM compiler that some are traditional, needs more time and manpower, causes the design cycle longer.
[summary of the invention]
The object of the invention is to propose a kind of domain programmed method for static RAM compiler, while guarantee does not affect layout design, accomplish being separated of layout design and program design, shortened the design cycle, and make compiler have greater flexibility and portability.
For achieving the above object, the present invention adopts following technical scheme:
For a domain programmed method for static RAM compiler, comprise the following steps:
The first step, in elementary cell layout design process, the information insertion needed when compiler being spliced domain is in elementary cell domain; Described information adds in domain in the form of a flag;
Existing mark in second step, compiler identification elementary cell domain, the information needed during to extract splicing domain;
3rd step, compiler, according to the information extracted, by searching or calculate the position finding needs to operate, and carry out domain operation in this position.
The present invention further improves and is: described mark comprises figure and text label.
Mark is positioned at and does not affect on some auxiliary layers of normal layout design.
The present invention further improves and is: described information comprises layout contour, punching mark and port label;
Layout contour is a pictorial symbolization, and its rule is: use an auxiliary layer (such as BORDER layer) to draw the profile of a rectangle as elementary cell domain.The position of this rectangle is determined by the position of the domain of elementary cell.In order to for simplicity, make this rectangle lower left corner be positioned at (0,0) some during elementary cell layout design, then the coordinate in the upper right corner is exactly the layout size of this elementary cell;
Punching mark is a text label, and its rule is: use an auxiliary layer (such as TXT layer) to do a text label needing the center of punching; The coordinate of this label is exactly the position needing punching; The content of text of this label contains the information of punching needs, and can be used for identifying different punching marks.
Port label is combined by a figure and a text label, and its rule is: first use an auxiliary layer (such as TXT layer) to do a text label in the position of port; The coordinate of this label is exactly the position of port; Secondly use this auxiliary layer to draw the shape of a rectangle as port, before the profile of rectangle includes mark the position of text label, the width of rectangle equals the width of this port metal wire.
The present invention further improves and is: the content of text of the label of punching mark comprises three parts and separated by underscore " _ ", Part I " VIA " represents that this is a punching mark, Part II represents that the type that needs punch, Part III are that the title of label is for distinguishing punching marks different in same elementary cell domain;
The content of text of the label of port label comprises three parts and is separated by underscore " ", Part I " PIN " represents that this is a port label, Part II represents the metal level type needing port, and Part III is that the title of port is for distinguishing port label different in same elementary cell domain.
The present invention further improves and is: after completing elementary cell layout design, exported as a GDSII file; Compiler directly reads in GDSII file, the figure and text mark that meet rule described in the first step is found in each elementary cell domain by scanning, and relevant information is extracted from GDSII file: find and belong to BORDER layer and lower left corner coordinate is (0,0) rectangle, records the title of the coordinate in its upper right corner and the elementary cell at place; Find and belong to TXT layer and the text label that starts with " VIA " or " PIN " of content of text, the title of the elementary cell at its coordinate, content of text and place is recorded; Find the rectangle belonging to TXT layer, if this rectangle includes one belong to TXT layer and the coordinate of text label that starts with " PIN " of content of text, then by the lower left corner of rectangle and the coordinate in the upper right corner, the content of text of included text label and the title of place elementary cell are recorded.
The present invention further improves and is: described elementary cell domain comprises: storage unit module, word-line decoder module, data input/output module and control module.
The present invention further improves and is: the process adding mark in the domain of elementary cell can be carried out with the design process of domain simultaneously.Make marks according to the needs of programming when layout design, the text label of mark or figure contain the information generated required for domain according to certain rule.Text label is arranged in domain specific layer or has the text meeting certain rule.The information that text label can comprise comprises coordinate and content of text, and wherein the message composition that programming needs can be entered according to certain rule by content of text.Pictorial symbolization is arranged in a specific layer of domain.The information that figure can comprise comprises coordinate, size, border and layer;
The present invention further improves and is: existing mark in compiler identification domain, and records the information of the programming needs such as its coordinate, content of text, dimension of picture.Compiler identifies the figure be positioned on specific pattern layer and its coordinate, size, border and map data mining platform is extracted.Compiler identifies being positioned on specific pattern layer or having the label meeting certain regular content of text and its coordinate and content of text is extracted.
The present invention further improves and is: compiler, according to the label information extracted, by searching or calculate the position finding needs to operate, and carries out domain operation in this position.Position in domain accurately can represent with coordinate.Compiler can obtain its coordinate, as the position of domain operation by searching certain mark; Compiler also on the basis of known coordinate, can be of a size of side-play amount according to the position relationship between known module with pictorial symbolization, calculates the position of required domain operation.
Relative to prior art, the present invention has the following advantages:
The present invention proposes a kind of domain programmed method for static RAM compiler, to be labeled as carrier in domain, while not affecting normal layout design, the information that domain programming needs is directly embedded in domain, do not need domain by the time to add again after completing, the time of layout design can be shortened; Extracted the information of domain programming needs by the method for the automatic identification marking of compiler, save manpower and time; Operating according to mark in program when carrying out domain programming, not needing to relate to concrete layout information, accomplished being separated of layout design and program design, made compiler have greater flexibility and portability.
[accompanying drawing explanation]
Fig. 1 is process flow diagram of the invention process.
Fig. 2 is the example generating domain according to a SRAM compiler of the invention process.
Fig. 3 is the partial schematic diagram after adding mark in basic territory unit CTRL.
Fig. 4 is the partial schematic diagram after adding mark in basic territory unit DEC1.
Fig. 5 is the profile schematic diagram of basic territory unit IO1 and ROW1.
Fig. 6 is the schematic diagram calculating stitching position in domain splicing according to dimension of picture.
Fig. 7 is the schematic diagram selecting punch position in domain splicing according to text label.
Fig. 8 is according to the schematic diagram that figure and text mark are programmed to port TM in domain splicing.
[embodiment]
Below in conjunction with accompanying drawing, embodiments of the present invention are described further.
Refer to shown in Fig. 1, Fig. 1 is process flow diagram of the invention process.
Mark is added in domain in elementary cell layout design process by slip-stick artist by the first step.For convenience's sake, specify that the lower left corner coordinate of all elementary cell domains is all positioned at (0,0) point.What need interpolation is marked with three kinds: layout contour, punching, port.
Layout contour is a pictorial symbolization, its rule is: use BORDER layer (auxiliary layer in layout design) to draw the profile of a rectangle as elementary cell domain, this rectangle lower left corner is positioned at (0,0) point, then the coordinate in the upper right corner is exactly the layout size of this elementary cell;
Punching mark is a text label, and its rule is: use TXT layer (auxiliary layer in layout design) to do a text label needing the center of punching.The coordinate of this label is exactly the position needing punching.The content of text of this label comprises three parts and is separated by underscore " _ ", Part I " VIA " represents that this is a punching mark, Part II represents that the type (being namely connected to other one deck from the punching of certain one deck) that needs punch, Part III are that the title of label is for distinguishing punching marks different in same elementary cell domain.
Port label is combined by a figure and a text label, and its rule is: first use TXT layer to do a text label in the position of port.The coordinate of this label is exactly the position of port.The content of text of this label comprises three parts and is separated by underscore " _ ", Part I " PIN " represents that this is a port label, Part II represents the metal level type (i.e. certain layer of metal) needing port, and Part III is that the title of port is for distinguishing port label different in same elementary cell domain.Secondly use TXT layer to draw the shape of a rectangle as port, before the profile of rectangle includes mark the position of text label, the width of rectangle equals the width of this port metal wire.
Second step by existing mark in compiler identification elementary cell domain, and records the information of its coordinate, content of text, dimension of picture programming needs.A GDSII file is exported as after completing elementary cell layout design.GDSII file is the binary stream file of a standard format, compiler directly reads in GDSII file, the figure and text mark that meet rule described in the first step is found in each elementary cell domain by scanning, and relevant information is extracted from GDSII file: find and belong to BORDER layer and lower left corner coordinate is (0,0) rectangle, records the title of the coordinate in its upper right corner and the elementary cell at place; Find and belong to TXT layer and the text label that starts with " VIA " or " PIN " of content of text, the title of the elementary cell at its coordinate, content of text and place is recorded; Find the rectangle belonging to TXT layer, if this rectangle includes one belong to TXT layer and the coordinate of text label that starts with " PIN " of content of text, then by the lower left corner of rectangle and the coordinate in the upper right corner, the content of text of included text label and the title of place elementary cell are recorded.
3rd step compiler, according to the information extracted, by searching or calculate the position finding needs to operate, and carries out domain operation in this position.Wherein calculate and refer to conventional coordinate transform, as translation, mirror image, rotation etc.Layout contour is used for the concatenation of domain, and punching mark for carrying out punch operation on domain, and port label for adding the operation of port on domain.Each mark uniquely can be determined (title that layout contour even only needs place elementary cell) by the title of the title of its place elementary cell and mark, therefore when programming, only need the title of assigned tags place elementary cell in a program and the title of mark itself, the layout information that the record that compiler just generates by searching second step finds concrete operations to need is with complete operation.Owing to not comprising concrete layout information in compiler program, therefore once domain is revised, only need the reform first step and second step.
Refer to shown in Fig. 2, Fig. 2 is the example generating domain according to a SRAM compiler of the invention process.Elementary cell one has 4: storage unit module ROW1, word-line decoder module DEC1, data input/output module IO1 and control module CTRL.The width of each storage unit module ROW1 is identical with the width of data input/output module IO1, correspond to a data.The height of each storage unit module ROW1 is identical with the height of word-line decoder module DEC1, this root wordline (WL) corresponding.The width of word-line decoder module DEC1 is identical with the width of control module CTRL.Compiler, according to the difference of data bit width and wordline number, complete domain is spliced in the basis of described 4 elementary cells.For data bit width is 4 shown in Fig. 2, wordline number is the situation of 4.
Refer to shown in Fig. 3, Fig. 3 is the partial schematic diagram after adding mark in basic territory unit CTRL.The input port such as address, order, clock of SRAM is all positioned at control module CTRL place, and the TM in Fig. 3 is exactly an input port.First use BORDER layer to draw a rectangle as profile, the coordinate (0,0) in its lower left corner, the coordinate (A, B) in the upper right corner, then its domain is wide is A, and height is B.Secondly TXT layer is used to do text label " PIN_M2_TM " and rectangle at port TM at outgoing position place, represent that port TM is connected with outside by the metal wire belonging to M2 layer (second layer metal), place is marked by rectangle in position, the width means of rectangle tell the width of M2 line.Finally TXT layer is used to be text label " VIA_M2M1_TM_VDD " and " VIA_M2M1_TM_VSS " respectively at the M2 line of port TM with the center crossed of the power supply vdd line and ground VSS line that are positioned at M1 layer (first layer metal), represent that described two positions may need to carry out punch operation, concrete coordinate is the coordinate of respective labels, and punching type is that M2 layer is to M1 layer.Be called that the mark punching of " TM_VDD " will make TM port be connected to power supply in name, be namely fixed as ' 1 '; Be called that the mark punching of " TM_VSS " will make TM port be connected to ground in name, be namely fixed as ' 0 '.Except TM, all the other ports all can do similar process.
Refer to shown in Fig. 4, Fig. 4 is the partial schematic diagram after adding mark in basic territory unit DEC1.This elementary cell is a code translator.First use BORDER layer to draw a rectangle as profile, the coordinate (0,0) in its lower left corner, the coordinate (C, D) in the upper right corner, then its domain is wide is C, and height is D.Secondly compiler needs when splicing all to be positioned at M2 layer from signal wire A, AN, B, BN(of coming from control module CTRL, and AN is the designature of A, and BN is the designature of B) in select two two inputs (I1 and I2) being connected to code translator.First input I1 crosses at M1 layer and A, the AN being positioned at M2 layer, uses TXT layer to be text label " VIA_M2M1_A " and " VIA_M2M1_AN " respectively in the center of described intersection; Second input I2 crosses at M1 layer and B, the BN being positioned at M2 layer, uses TXT layer to be text label " VIA_M2M1_B " and " VIA_M2M1_BN " respectively in the center of described intersection; Just punch position accurately can be found by above-described four punching compilers.
Refer to shown in Fig. 5, Fig. 5 is the profile schematic diagram of basic territory unit IO1 and ROW1.Punching mark and port label do not show in Figure 5, and the layout contour that illustrate only for concatenation marks.The profile of storage unit module ROW1 is the rectangle being positioned at BORDER layer, lower left corner coordinate (0,0), upper right corner coordinate (E, D).The profile of data input/output module IO1 is the rectangle being positioned at BORDER layer, lower left corner coordinate (0,0), upper right corner coordinate (F, B).
Refer to shown in Fig. 6, Fig. 6 is the schematic diagram calculating stitching position in domain splicing according to dimension of picture.Compiler is exactly splicing as shown in Figure 6 realized by program.Due to the existence of layout contour mark, when concatenation, program only needs to know the position relationship between module and existing module newly added, and concrete coordinate is then according to this relation with extract label information and calculate.
Splicing generation module ROW4: at (0,0) some placement ROW1, second ROW1 is positioned at directly over first ROW1, then the placement coordinate of known second ROW1 of program computation should be (0, D).By that analogy, the coordinate of the 3rd and the 4th ROW1 should be respectively (0,2D), (0,3D).The lower left corner coordinate of the ROW4 module after completing is (0,0) upper right corner coordinate is (C, 4D).
Splicing generation module COL: at (0,0) some placement IO1, ROW4 is positioned at directly over IO1, then the placement coordinate of the known ROW4 of program computation should be (0, B).The lower left corner coordinate of the COL module after completing is (0,0) upper right corner coordinate is (C, B+4D).
Splicing generation module DEC4: at (0,0) some placement DEC1, second DEC1 is positioned at directly over first DEC1, then the placement coordinate of known second DEC1 of program computation should be (0, D).By that analogy, the coordinate of the 3rd and the 4th DEC1 should be respectively (0,2D), (0,3D).The lower left corner coordinate of the DEC4 module after completing is (0,0) upper right corner coordinate is (A, 4D).
Splicing generation module MID: at (0,0) some placement CTRL, DEC4 is positioned at directly over CTRL, then the placement coordinate of the known DEC4 of program computation should be (0, B).The lower left corner coordinate of the MID module after completing is (0,0) upper right corner coordinate is (A, B+4D).
Splicing generates complete domain: at (0,0) some placement COL, second COL is positioned at the front-right of first COL, then the placement coordinate of known second COL of program computation should be (C, 0).By that analogy, from second COL, from a left side be MID, the 3rd COL and the 4th COL successively backward.Their placement coordinate is (2C, 0), (2C+A, 0) and (3C+A, 0) respectively.The lower left corner coordinate of the complete domain after completing is (0,0) upper right corner coordinate is (4C+A, B+4D).
Refer to shown in Fig. 7, Fig. 7 is the schematic diagram selecting punch position in domain splicing according to text label.When splicing generation module DEC4, it is different that the input (I1 with I2) of 4 DEC1 module needs is connected: first DEC1 produces WL0, and its input end I1 is connected to AN, and input end I2 is connected to BN; Second DEC1 produces WL1, and its input end I1 is connected to AN, and input end I2 is connected to B; 3rd DEC1 produces WL2, and its input end I1 is connected to A, and input end I2 is connected to BN; 4th DEC1 produces WL3, and its input end I1 is connected to A, and input end I2 is connected to B.This different linker can by realizing in the punching of different mark.As in Fig. 7, the 3rd DEC1 carries out punch operation.Due to the existence of punching mark, program only needs to know that " VIA_M2M1_A " and " VIA_M2M1_BN " mark at the 3rd DEC1 is punched.When generating domain, program calculates according to the set-point coordinate (0,2D) of the 3rd DEC1 and the coordinate of above two described marks that extracts, needs the coordinate of punch position in DEC4 module, then at this coordinate place according to content of text, create the M2 layer connecting hole to M1 layer.
Refer to shown in Fig. 8, Fig. 8 is according to the schematic diagram that figure and text mark are programmed to port TM in domain splicing.Need to process all of the port after the splicing completing complete domain.Shown in Fig. 8, be possible two kinds of Different treatments: the TM of port TM be that an input port or TM fixedly connect power supply or ground.According to different conditions, program can select wherein a kind of processing mode automatically: when TM fixedly connects power supply, and program needs to punch in " VIA_M2M1_TM_VDD " mark; When TM solid ground, program needs to punch in " VIA_M2M1_TM_VSS " mark; When TM is an input port, program needs make label " TM " at " PIN_M2_TM " place and create port designation.When generating domain, it is (2C that program can calculate the set-point coordinate of CTRL in complete domain according to the position of CTRL module in MID module and the set-point coordinate of MID module in complete domain, 0), then be marked at the coordinate of CTRL according to the above extracting as reference point, calculate these further and be marked at position in complete domain, and carry out corresponding operating.
Claims (5)
1., for a domain programmed method for static RAM compiler, it is characterized in that, comprise the following steps:
The first step, in elementary cell layout design process, the information insertion needed when compiler being spliced domain is in elementary cell domain; Described information adds in domain in the form of a flag;
Existing mark in second step, compiler identification elementary cell domain, the information needed during to extract splicing domain;
3rd step, compiler, according to the information extracted, by searching or calculate the position finding needs to operate, and carry out domain operation in this position;
Described mark comprises figure and text label, and is positioned at and does not affect on some auxiliary layers of normal layout design;
Described information comprises layout contour, punching mark and port label;
Layout contour is a pictorial symbolization, and its rule is: use an auxiliary layer to draw the profile of a rectangle as elementary cell domain; This rectangle position is determined by the position of the domain of elementary cell;
Punching mark is a text label, and its rule is: use an auxiliary layer to do a text label needing the center of punching; The coordinate of this label is exactly the position needing punching; The content of text of this label contains the information of punching needs, and can be used for identifying different punching marks;
Port label is combined by a figure and a text label, and its rule is: first use an auxiliary layer to do a text label in the position of port; The coordinate of this label is exactly the position of port; Secondly use this auxiliary layer to draw the shape of a rectangle as port, before the profile of rectangle includes mark the position of text label, the width of rectangle equals the width of this port metal wire.
2. a kind of domain programmed method for static RAM compiler according to claim 1, it is characterized in that, the content of text of the label of punching mark comprises three parts and is separated by underscore " _ ", Part I " VIA " represents that this is a punching mark, Part II represents that the type that needs punch, Part III are that the title of label is for distinguishing punching marks different in same elementary cell domain;
The content of text of the label of port label comprises three parts and is separated by underscore " _ ", Part I " PIN " represents that this is a port label, Part II represents the metal level type needing port, and Part III is that the title of port is for distinguishing port label different in same elementary cell domain.
3. a kind of domain programmed method for static RAM compiler according to claim 1 and 2, is characterized in that, exported as a GDSII file after completing elementary cell layout design; Compiler directly reads in GDSII file, the figure and text label that meet rule in the first step is found in each elementary cell domain by scanning, and relevant information is extracted from GDSII file: find and belong to BORDER layer and lower left corner coordinate is (0,0) rectangle, records the title of the coordinate in its upper right corner and the elementary cell at place; Find and belong to TXT layer and the text label that starts with " VIA " or " PIN " of content of text, the title of the elementary cell at its coordinate, content of text and place is recorded; Find the rectangle belonging to TXT layer, if this rectangle includes one belong to TXT layer and the coordinate of text label that starts with " PIN " of content of text, then by the lower left corner of rectangle and the coordinate in the upper right corner, the content of text of included text label and the title of place elementary cell are recorded.
4. a kind of domain programmed method for static RAM compiler according to claim 1, is characterized in that:
The auxiliary layer that layout contour uses is BORDER layer; Make this rectangle lower left corner be positioned at (0,0) some during elementary cell layout design, then the coordinate in the upper right corner is exactly the layout size of this elementary cell;
The auxiliary layer that punching mark uses is TXT layer;
The auxiliary layer that port label uses is TXT layer.
5. a kind of domain programmed method for static RAM compiler according to claim 1, it is characterized in that, described elementary cell domain comprises: storage unit module, word-line decoder module, data input/output module and control module.
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| CN105740487B (en) * | 2014-12-09 | 2019-08-23 | 中芯国际集成电路制造(上海)有限公司 | Domain and schematic diagram consistency verification method based on Process design kit |
| CN105824679A (en) * | 2015-01-07 | 2016-08-03 | 展讯通信（上海）有限公司 | Memory compiler layout programming system and method |
| CN106156375B (en) * | 2015-03-24 | 2019-01-04 | 展讯通信（上海）有限公司 | A kind of memory compiler joining method and memory |
| CN106844809A (en) * | 2015-12-04 | 2017-06-13 | 展讯通信（上海）有限公司 | A kind of method and device for obtaining memory macro unit size |
| CN106855894B (en) * | 2015-12-09 | 2020-04-14 | 展讯通信（上海）有限公司 | Method and device for acquiring position information of storage unit in memory |
| CN106855893B (en) * | 2015-12-09 | 2020-04-14 | 展讯通信（上海）有限公司 | Method and device for acquiring power supply main line of memory layout |
| CN105912782B (en) * | 2016-04-12 | 2019-01-25 | 西安紫光国芯半导体有限公司 | A method of automatically generating bit wide using compiler can configure bus domain |
| CN108446412B (en) * | 2017-02-16 | 2023-01-24 | 龙芯中科技术股份有限公司 | Memory compiling method and device and generated memory |
| CN112001136A (en) * | 2020-08-20 | 2020-11-27 | 天津蓝海微科技有限公司 | Software implementation method for automatically generating memory layout and netlist |
| CN112100975A (en) * | 2020-09-28 | 2020-12-18 | 珠海市一微半导体有限公司 | Automatic metal layer connection method for layout design |
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