CN106855893B - Method and device for acquiring power supply main line of memory layout - Google Patents
Method and device for acquiring power supply main line of memory layout Download PDFInfo
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- CN106855893B CN106855893B CN201510907233.4A CN201510907233A CN106855893B CN 106855893 B CN106855893 B CN 106855893B CN 201510907233 A CN201510907233 A CN 201510907233A CN 106855893 B CN106855893 B CN 106855893B
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Abstract
The invention provides a method and a device for acquiring a power main line of a layout of a memory. The method comprises the following steps: adding a power supply main line mark on each layout basic unit, wherein the power supply main line mark comprises a mark rectangle and a power supply identifier; splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, wherein a power main line mark on each layout basic unit is used as a power main line mark of the top layer unit; and calculating and drawing a power supply main line according to the power supply main line mark of the top-layer unit. The invention can solve the technical problem that the power main line of the basic unit of the memory is tightly coupled with the programming method.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a method and a device for acquiring a power supply main line of a layout of a memory.
Background
As the number of memories used in System-on-Chip (SoC) increases with the continuous advancement of semiconductor manufacturing processes and integrated circuit design capabilities, it becomes very difficult to design these memories completely in a fully customized manner since various memories of different sizes or structures are required in the same design. Memory compilers are widely used as efficient tools to generate memory of different sizes and functions.
For the power supply setting of the memory, during the power supply planning of the SoC, a single-layer power line connected to a macro cell of the memory needs to have a determined direction, so a layout and an LEF file generated by a memory compiler need to provide a complete power main line with a determined direction for a power supply planning tool to connect, and the memory compiler generally provides a rectangular power main line metal layer. At present, in the prior art, a power supply main line is formed by a memory compiler through manually drawing the power supply main line in a memory basic unit in advance, and then programming the power supply main line into a memory macro unit in a splicing manner.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art: the power supply main line of the basic unit of the memory is tightly coupled with the programming method. Because the power supply main line of the basic cell of the memory is tightly coupled with the programming method, the drawn and shaped power supply main line in the basic cell of the memory cannot adapt to the change of the programming mode; different layout programming of the memory compiler can have different unit splicing modes, so that the workload of manually drawing a power main line in a memory basic unit is larger; when the LEF file is fetched, all basic units including the power main line need to be scanned, which is slow, and thus the efficiency of the memory compiler is low.
Disclosure of Invention
The method and the device for acquiring the power main line of the layout of the memory can solve the technical problem that the power main line of a basic unit of the memory is tightly coupled with a programming method.
In a first aspect, the present invention provides a method for acquiring a power main line of a memory layout, where the method includes:
adding a power supply main line mark on each layout basic unit, wherein the power supply main line mark comprises a mark rectangle and a power supply identifier;
splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, wherein a power main line mark on each layout basic unit is used as a power main line mark of the top layer unit;
and calculating and drawing a power supply main line according to the power supply main line mark of the top-layer unit.
Optionally, when the marked rectangles with the same power source identifier intersect, the calculating and drawing the power source main line according to the power source main line mark in the top-level cell includes:
when a power supply main line in the horizontal direction is drawn, covering and merging a plurality of marked rectangles with the same power supply identification in the horizontal direction, and taking the covered and merged rectangles as metal layer rectangles of the power supply main line in the horizontal direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the horizontal direction.
Optionally, when the marked rectangles with the same power source identifier intersect, the calculating and drawing the power source main line according to the power source main line mark in the top-level cell includes:
when drawing a power supply main line in the vertical direction, firstly rotating the top layer unit by 90 degrees anticlockwise, covering and merging a plurality of marked rectangles with the same power supply identification in the horizontal direction, then rotating the top layer unit by 90 degrees clockwise, and taking the covered and merged rectangles as metal layer rectangles of the power supply main line in the vertical direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the vertical direction.
Optionally, before the overlapping and merging of the plurality of marked rectangles with the same power source identifier in the horizontal direction, the method further includes:
the marker rectangle on the top level cell is extended to the macrocell width.
Optionally, the overlaying and merging the plurality of marked rectangles with the same power source identifier in the horizontal direction includes:
covering and combining the intersected marked rectangles with the same power supply identification to form a covered rectangle;
if the covering rectangle is intersected with other marking rectangles with the same power supply identification, covering and combining the covering rectangle and the other marking rectangles to form a new covering rectangle;
and if the coverage rectangles with the same power supply identification are intersected, covering and merging the intersected coverage rectangles to form a new coverage rectangle.
Optionally, when the marked rectangles with the same power source identifier do not intersect, the calculating and drawing the power source main line according to the power source main line mark in the top-level cell includes:
and taking each marking rectangle as a metal layer rectangle of the power supply main line corresponding to the power supply identifier.
Optionally, before the taking each marked rectangle as the metal layer rectangle of the power main line corresponding to the power identifier, the method further includes:
the marker rectangle on the top level cell is extended to the macrocell width.
Optionally, the layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming.
In a second aspect, the present invention provides an apparatus for acquiring a power main line of a memory layout, where the apparatus includes:
the adding unit is used for adding a power supply main line mark on each layout basic unit, and the power supply main line mark comprises a mark rectangle and a power supply identifier;
the splicing unit is used for splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, and the power supply main line mark on each layout basic unit is used as the power supply main line mark of the top layer unit;
and the calculation drawing unit is used for calculating and drawing the power supply main line according to the power supply main line mark of the top layer unit.
Optionally, the calculation drawing unit is configured to, when marker rectangles with the same power source identifier intersect with each other, perform coverage merging on a plurality of marker rectangles with the same power source identifier in the horizontal direction when drawing a power source main line in the horizontal direction, and use the merged coverage rectangles as metal layer rectangles of the power source main line in the horizontal direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the horizontal direction.
Optionally, the calculation drawing unit is configured to, when mark rectangles with the same power source identifier intersect with each other, rotate the top-level unit counterclockwise by 90 degrees first when drawing a power source main line in a vertical direction, cover and merge a plurality of mark rectangles with the same power source identifier in a horizontal direction, rotate the top-level unit clockwise by 90 degrees, and use the covered and merged rectangles as metal layer rectangles of the power source main line in the vertical direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the vertical direction.
Optionally, the apparatus further includes a first extension unit, configured to, before the calculation drawing unit performs coverage merging on the plurality of mark rectangles with the same power source identifier in the horizontal direction, extend the mark rectangle on the top-level cell to the macrocell width.
Optionally, the calculation drawing unit is configured to perform coverage merging on the marker rectangles with the same power source identifier and intersecting with each other to form a coverage rectangle; when the covering rectangle is intersected with other marking rectangles with the same power supply identification, covering and combining the covering rectangle and the other marking rectangles to form a new covering rectangle; and when the coverage rectangles with the same power source identification are intersected, performing coverage combination on the intersected coverage rectangles to form a new coverage rectangle.
Optionally, the calculation drawing unit is configured to, when marker rectangles with the same power source identifier do not intersect, use each marker rectangle as a metal layer rectangle of a power source main line corresponding to the power source identifier.
Optionally, the apparatus further includes a second expansion unit, configured to expand, by the computation drawing unit, the marker rectangle on the top-level cell to the macrocell width before the metal layer rectangle that takes each marker rectangle as the power supply main line corresponding to the power supply identifier.
Optionally, the layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming.
According to the method and the device for acquiring the power supply main line of the memory layout, provided by the embodiment of the invention, the drawing of the power supply main line of the layout and the programming of the layout are independently started (decoupled), so that the development of a memory compiler is more flexible; the power supply main line is drawn only in the top unit, and a fixed power supply main line does not need to be drawn in the basic unit of the memory, so that the workload of a memory compiler is reduced; meanwhile, when the LEF file is extracted, the calculation of the power main line metal layer rectangle is only carried out in the top unit, so that the speed of extracting the LEF file is improved.
Drawings
Fig. 1 is a schematic structural diagram of a power main line of a layout of a memory according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for obtaining a power main line of a layout of a memory according to an embodiment of the present invention;
fig. 3a is a schematic structural diagram of a layout basic unit to which a power main line mark is added according to an embodiment of the present invention;
FIG. 3b is a schematic structural diagram of a top level unit formed by splicing basic layout units according to an embodiment of the present invention;
FIG. 3c is a schematic structural diagram of the power main line metal layer rectangles spliced by the power main line marks of the top-level unit according to the embodiment of the present invention;
FIG. 4a is a schematic diagram of a structure of a plurality of marked rectangles in the marked rectangle overlay merging according to an embodiment of the present invention;
FIG. 4b is a schematic structural diagram of the overlay merging of the marked rectangles, wherein the marked rectangles intersect and merge to form a covered rectangle according to an embodiment of the present invention;
FIG. 4c is a schematic structural diagram of the overlay rectangle intersecting the mark rectangle to form a new overlay rectangle in the overlay merging of the mark rectangles according to the embodiment of the present invention;
FIG. 4d is a schematic diagram of a structure of a rectangle with covered and combined rectangles as a power main line metal layer rectangle in rectangular cover combination according to an embodiment of the present invention
FIG. 5 is a schematic diagram of a power main line extended to a power width according to another embodiment of the present invention;
FIG. 6a is a schematic structural diagram of a layout basic unit with a power main line tag added in another embodiment of the present invention;
FIG. 6b is a schematic diagram illustrating a structure of a power main line tag extending to a width of a macro cell according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of an apparatus for obtaining a power main line of a macro cell of a memory according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A memory compiler refers to a set of libraries and toolkits for generating a series of parameterizations of a memory macrocell design file, and generally includes modules for layout programming, netlist programming, EDA view generation, and the like. The layout programming refers to the operations of selecting, splicing, drawing and the like on layout primitives by using a programming method, and the process outputs a memory layout and an LEF file. Memory layout is a method of representing the components of each hierarchy of metal, oxide, semiconductor, etc. of an integrated circuit as planar geometric primitives. The LEF file represents an ASCII file of the outline information of the memory macro-cell layout, and comprises information such as memory pins, a power supply main line and the like, wherein the power supply main line is a metal layer for supplying power to the memory macro-cell and is drawn in the memory macro-cell layout so as to be connected by SoC designers when power supply planning is carried out.
As shown in fig. 1, during power supply planning of an SoC, a single-layer power line connecting a memory macro cell needs to have a certain direction, so a layout and an LEF file generated by a memory compiler need to provide a complete memory macro cell power main line 11 with a certain direction for connection of a power supply planning tool, and the memory compiler generally provides a rectangular power main line metal layer. When the power supply planning is carried out in the vertical direction, the macro cell of the memory needs to be provided with a power supply main line in the horizontal direction; similarly, when the power supply is planned for horizontal wiring, the memory macro cell needs to have a power main line in the vertical direction. In addition, in order to facilitate automation of the power planning tool, it is sometimes required that the macro cell power main line of the memory needs to be distributed as much as possible in the horizontal direction.
The invention provides a method for acquiring a power supply main line of a memory layout, which comprises the following steps of:
step S11: and adding a power supply main line mark on each layout basic unit, wherein the power supply main line mark comprises a mark rectangle and a power supply identifier.
When the layout programming is used for drawing the basic unit, a predefined level is used for adding a marking rectangle at a position needing to be connected with a power supply, meanwhile, according to different power supplies, a predefined marking character level is used for adding a power supply identifier, and the marking rectangle and the power supply identifier jointly form a power supply main line marker. As shown in fig. 3a, the basic cell 1 has two power source main line marks, one power source main line mark of the power source 1 and one power source main line mark of the power source 2, and the basic cell 2 has only one power source main line mark of the power source 2.
Step S12: and splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, wherein the power main line mark on each layout basic unit is used as the power main line mark of the top layer unit.
The basic principle of the layout programming splicing algorithm is module splicing, a high-level module is formed by splicing basic units of a layout, and then the modules are spliced until a top-level unit is finally formed. And (3) splicing the layout basic units by layout programming to generate a new unit, and taking the power supply main line mark of the basic unit used for splicing as the power supply main line mark of the new unit until the top layer unit is spliced. As shown in fig. 3b, the newly created cell includes a basic cell 1 and a basic cell 2, and the power main line flags of the power supply 1 and the power supply 2 of the two basic cells are used as the power main line flags of the newly created cell. The power main line mark is in the newly built cell and is coincident with the position in the basic cell.
Step S13: and calculating and drawing a power supply main line according to the power supply main line mark of the top-layer unit.
As shown in fig. 3c, in the top level cell, the power main line is calculated and drawn according to the power main line flag. The calculation method of the power main line relates to coverage combination of rectangles, and the rectangles subjected to coverage combination are used as the positions of the power main line to prepare for extracting the LEF file.
According to the method for acquiring the power supply main line of the memory layout, provided by the embodiment of the invention, the drawing of the power supply main line of the layout and the programming of the layout are independently started (decoupled), so that the development of a memory compiler is more flexible; the power supply main line is drawn only in the top unit, and a fixed power supply main line does not need to be drawn in the basic unit of the memory, so that the workload of a memory compiler is reduced; meanwhile, when the LEF file is extracted, the calculation of the power main line metal layer rectangle is only carried out in the top unit, so that the speed of extracting the LEF file is improved.
Optionally, when the marked rectangles with the same power source identifier intersect, the calculating and drawing the power source main line according to the power source main line mark in the top-level cell includes:
when a power supply main line in the horizontal direction is drawn, covering and merging a plurality of marked rectangles with the same power supply identification in the horizontal direction, and taking the covered and merged rectangles as metal layer rectangles of the power supply main line in the horizontal direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the horizontal direction.
Optionally, overlapping and merging the intersected marked rectangles with the same power source identification to form an overlapping rectangle;
if the covering rectangle is intersected with other marking rectangles with the same power supply identification, covering and combining the covering rectangle and the other marking rectangles to form a new covering rectangle;
and if the coverage rectangles with the same power supply identification are intersected, covering and merging the intersected coverage rectangles to form a new coverage rectangle.
For the method of performing coverage merging on a plurality of marked rectangles in the horizontal direction, fig. 4a-4d illustrate the process of performing coverage merging on a group of marked rectangles of the same power source identifier in the horizontal direction. A, B, C, D shows a marked rectangle of four power main line marks of the same power identification, and the marked rectangle C and the marked rectangle D intersect to form an overlapping rectangle overlapping the marked rectangle C and the marked rectangle D, as shown by the shaded part in FIG. 4 b. The covering rectangle is a single rectangle with the minimum covering of the covering mark rectangle C and the marking rectangle D, namely the minimum value of the X coordinates of the lower left corners of the covering rectangles is taken as the X coordinate of the lower left corner of the covering rectangles, and the minimum value of the Y coordinates of the lower left corners of the covering rectangles is taken as the Y coordinate of the lower left corner of the covering rectangles; and taking the maximum value of the X coordinates of the upper right corners of the mark rectangle C and the mark rectangle D as the X coordinate of the upper right corner of the covering rectangle, and taking the maximum value of the Y coordinates of the upper right corners of the mark rectangle C and the mark rectangle D as the Y coordinate of the upper right corner of the covering rectangle.
And if the cover rectangle C and the mark rectangle D are crossed with the combined cover rectangle and mark rectangle B, the cover rectangle is covered and combined with the mark rectangle B to form a new cover rectangle, as shown in FIG. 4C. The same new covering rectangle is the smallest covering single rectangle that covers the covering rectangle and the marking rectangle B. The mark rectangle a does not intersect with other rectangles, and the rectangle corresponding to the mark rectangle a and the mark rectangle B, C, D are overlaid on the metal layer rectangle which is the merged rectangle used as the power main line, as shown in fig. 4 d. And when the LEF file is extracted subsequently, the two rectangular coordinates are directly read.
When the marked rectangles with the same power source identification intersect, the metal layer rectangles covering and combining the marked rectangles to form the power source main line further comprise the following conditions: and if the coverage rectangle formed by coverage combination of the mark rectangles intersects with other coverage rectangles, performing coverage combination on the intersected coverage rectangles to form a new coverage rectangle.
Optionally, when the marked rectangles with the same power source identifier do not intersect, the calculating and drawing the power source main line according to the power source main line mark in the top-level cell includes:
and taking each marking rectangle as a metal layer rectangle of the power supply main line corresponding to the power supply identifier.
When drawing the power main line in the horizontal direction, in order to facilitate automation of a power planning tool, sometimes the power main line of the memory macro cell needs to be distributed over the width of the memory macro cell in the horizontal direction as much as possible; similarly, when drawing the power main line in the vertical direction, it is sometimes required that the power main line of the memory macrocell must be as full as possible in the vertical direction as the height of the memory macrocell. As shown in fig. 5, for a power main line extended to the width of a macro cell:
when the mark rectangles with the same power source identification on the top unit intersect, optionally, the mark rectangles on the top unit are expanded to the width of the macro unit before the covering and combining of the mark rectangles with the same power source identification in the horizontal direction.
When the marked rectangles with the same power source identifier on the top-level cell do not intersect, optionally, before the metal layer rectangle taking each marked rectangle as the power source main line corresponding to the power source identifier, the marked rectangles on the top-level cell are expanded to the width of the macro cell.
That is, before the marked rectangle of the power main line mark in the top-level cell is covered and combined to form the metal layer rectangle of the power main line, the marked rectangle of the power main line mark needs to be expanded to the width of the macro cell. And then, performing coverage combination according to the coverage combination method to form a power main line metal layer rectangle. A, B, C, D, as shown in fig. 6a, the marked rectangles of the four power main line marks of the same power identifier are formed by first extending the marked rectangle A, B, C, D to the width of the macro cell in the horizontal direction, and then overlapping and merging the intersected rectangles to form the power main line metal layer rectangle. When the mark rectangles corresponding to the power main line marks of the top-level unit are not intersected, each mark rectangle on the top-level unit is firstly expanded to the width of the macro unit, and the expanded rectangle is used as a power main line metal layer rectangle.
Optionally, when the power main line in the vertical direction is drawn, the top-level cell is rotated counterclockwise by 90 degrees, a plurality of marked rectangles with the same power identifier are covered and merged in the horizontal direction, the top-level cell is rotated clockwise by 90 degrees, and the covered and merged rectangles are used as metal layer rectangles of the power main line in the vertical direction. And taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the vertical direction. The method for performing coverage merging on a plurality of marked rectangles with the same power source identifier in the horizontal direction is consistent with the coverage merging method for drawing the power source main line in the horizontal direction in the foregoing content, and details are not repeated here.
Optionally, the layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming.
The layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming, namely, how to select the layout basic units, how to splice the layout basic units, adjustment of the number and the positions of the layout basic units and the like in the process of splicing the layout basic units to form a top layer unit.
An embodiment of the present invention further provides a device for acquiring a power supply main line of a layout of a memory, as shown in fig. 7, the device includes:
the adding unit 71 is used for adding a power supply main line mark on each layout basic unit, wherein the power supply main line mark comprises a mark rectangle and a power supply identifier;
the splicing unit 72 is used for splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, and the power main line mark on each layout basic unit is used as the power main line mark of the top layer unit;
and the calculation drawing unit 73 is used for calculating and drawing the power supply main line according to the power supply main line mark of the top layer unit.
For the adding unit 71, when the layout programming is used for drawing the basic unit, a predefined hierarchical adding mark rectangle is used at a position where a power supply needs to be connected, and a power supply identifier is added by using a predefined mark word hierarchy according to different power supplies, the mark rectangle and the power supply identifier together form a power supply main line mark, as shown in fig. 3a, the basic unit 1 has two power supply main line marks, one power supply main line mark of the power supply 1, one power supply main line mark of the power supply 2, and the basic unit 2 only has one power supply main line mark of the power supply 2.
For the splicing unit 72, the basic principle of the layout programming splicing algorithm is module splicing, the modules are spliced from the layout basic unit to form a high-level module, and then the modules are spliced until a top-level unit is finally formed. And splicing the layout basic units by layout programming to generate a new unit, and taking the power supply main line mark of the layout basic unit used for splicing as the power supply main line mark of the new unit until the top layer unit is spliced. As shown in fig. 3b, the newly created cell includes a basic cell 1 and a basic cell 2, and the power main line flags of the power supply 1 and the power supply 2 of the two basic cells are used as the power main line flags of the newly created cell. The position of the power main line mark in the newly created cell coincides with that in the basic cell.
For the calculation drawing unit 73, as shown in fig. 3c, in the top level cell, the power main line is calculated and drawn according to the power main line flag. The calculation method of the power main line relates to coverage combination of the marked rectangles, and the rectangles after the coverage combination are used as the positions of the power main line to prepare for extracting the LEF file.
According to the device for acquiring the power supply main line of the memory layout, provided by the embodiment of the invention, the drawing of the power supply main line of the layout and the programming of the layout are independently started (decoupled), so that the development of a memory compiler is more flexible; meanwhile, because the power supply main line is only drawn in the top layer unit, a fixed power supply main line does not need to be drawn in the basic unit of the memory, and the workload of a memory compiler is reduced; meanwhile, when the LEF file is extracted, the calculation of the power main line metal layer rectangle is only carried out in the top unit, so that the speed of extracting the LEF file is improved.
Optionally, the calculation drawing unit 73 is configured to, when marker rectangles with the same power source identifier intersect, perform coverage merging on a plurality of marker rectangles with the same power source identifier in the horizontal direction when drawing the power source main line in the horizontal direction, and use the covered and merged rectangles as metal layer rectangles of the power source main line in the horizontal direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the horizontal direction.
Optionally, the calculation drawing unit 73 is configured to perform coverage merging on the marked rectangles with the same power source identifier and having an intersection to form a covered rectangle; when the covering rectangle is intersected with other marking rectangles with the same power supply identification, covering and combining the covering rectangle and the other marking rectangles to form a new covering rectangle; and when the coverage rectangles with the same power source identification are intersected, performing coverage combination on the intersected coverage rectangles to form a new coverage rectangle.
For the method of performing coverage merging on a plurality of marked rectangles in the horizontal direction, fig. 4a-4d illustrate the process of performing coverage merging on a group of marked rectangles of the same power source identifier in the horizontal direction. A, B, C, D shows a marked rectangle of four power main line marks of the same power identification, and the marked rectangle C and the marked rectangle D intersect to form an overlapping rectangle overlapping the marked rectangle C and the marked rectangle D, as shown by the shaded part in FIG. 4 b. The covering rectangle is a single rectangle with the minimum covering of the covering mark rectangle C and the marking rectangle D, namely the minimum value of the X coordinates of the lower left corners of the covering rectangles is taken as the X coordinate of the lower left corner of the covering rectangles, and the minimum value of the Y coordinates of the lower left corners of the covering rectangles is taken as the Y coordinate of the lower left corner of the covering rectangles; and taking the maximum value of the X coordinates of the upper right corners of the mark rectangle C and the mark rectangle D as the X coordinate of the upper right corner of the covering rectangle, and taking the maximum value of the Y coordinates of the upper right corners of the mark rectangle C and the mark rectangle D as the Y coordinate of the upper right corner of the covering rectangle.
And if the cover rectangle C and the mark rectangle D are crossed with the combined cover rectangle and mark rectangle B, the cover rectangle is covered and combined with the mark rectangle B to form a new cover rectangle, as shown in FIG. 4C. The same new covering rectangle is the smallest covering single rectangle that covers the covering rectangle and the marking rectangle B. The mark rectangle a does not intersect with other rectangles, and the rectangle corresponding to the mark rectangle a and the mark rectangle B, C, D are overlaid on the metal layer rectangle which is the merged rectangle used as the power main line, as shown in fig. 4 d. And when the LEF file is extracted subsequently, the two rectangular coordinates are directly read.
When the marked rectangles with the same power source identification intersect, the metal layer rectangles covering and combining the marked rectangles to form the power source main line further comprise the following conditions: and if the coverage rectangle formed by coverage combination of the mark rectangles intersects with other coverage rectangles, performing coverage combination on the intersected coverage rectangles to form a new coverage rectangle.
Optionally, the calculation drawing unit 73 is configured to, when mark rectangles with the same power source identifier do not intersect, use each mark rectangle as a metal layer rectangle of the power source main line corresponding to the power source identifier.
When drawing the power main line in the horizontal direction, in order to facilitate automation of a power planning tool, sometimes the power main line of the memory macro cell needs to be distributed over the width of the memory macro cell in the horizontal direction as much as possible; similarly, when drawing the power main line in the vertical direction, it is sometimes required that the power main line of the memory macrocell must be as full as possible in the vertical direction as the height of the memory macrocell. As shown in fig. 5, for a power main line extended to the width of a macro cell:
when the marked rectangles with the same power source identification on the top unit intersect, optionally, a first extension unit is further included for extending the marked rectangles on the top unit to the width of the macro unit before the covering and merging of the marked rectangles with the same power source identification in the horizontal direction.
When the marked rectangles with the same power source identifier on the top-level cell do not intersect, optionally, the method further includes a second expansion unit, configured to expand the marked rectangles on the top-level cell to the macrocell width before the metal layer rectangle that uses each marked rectangle as the power source main line corresponding to the power source identifier.
That is, before the power main line mark rectangle in the top-level cell is covered and combined to form the metal layer rectangle of the power main line, the power main line mark rectangle needs to be expanded to the width of the macro cell. And then, performing coverage combination according to the coverage combination method to form a power main line metal rectangle. As shown in fig. 6b, A, B, C, D is a marked rectangle of four power main line marks of the same power identifier, where the marked rectangle A, B, C, D is expanded to the width of a macro cell in the horizontal direction, and then the intersected rectangles are covered and combined to form a power main line metal layer rectangle.
Optionally, when drawing the power main line in the vertical direction, the calculation drawing unit 73 first rotates the top-level unit counterclockwise by 90 degrees, covers and merges a plurality of marked rectangles with the same power identifier in the horizontal direction, then rotates the top-level unit clockwise by 90 degrees, and takes the covered and merged rectangles as metal layer rectangles of the power main line in the vertical direction. And taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the vertical direction. The method for performing coverage merging on a plurality of marked rectangles with the same power source identifier in the horizontal direction is consistent with the coverage merging method for drawing the power source main line in the horizontal direction in the foregoing content, and details are not repeated here.
Optionally, the layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming.
The layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming, namely, how to select the layout basic units, how to splice the layout basic units, adjustment of the number and the positions of the layout basic units and the like in the process of splicing the layout basic units to form a top layer unit.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (16)
1. A method for acquiring a power main line of a memory layout is characterized by comprising the following steps:
adding a power supply main line mark on each layout basic unit, wherein the power supply main line mark comprises a mark rectangle and a power supply identifier, the mark rectangle represents an expected arrangement position of a power supply main line on the basic unit, and the power supply identifier represents a power supply individual number;
splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, wherein a power main line mark on each layout basic unit is used as a power main line mark of the top layer unit;
and calculating and drawing a power supply main line according to the power supply main line mark of the top-layer unit.
2. The method according to claim 1, wherein when marker rectangles with the same power source identifier intersect, the calculating and drawing a power source main line according to the power source main line marker in the top-level cell includes:
when a power supply main line in the horizontal direction is drawn, covering and merging a plurality of marked rectangles with the same power supply identification in the horizontal direction, and taking the covered and merged rectangles as metal layer rectangles of the power supply main line in the horizontal direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the horizontal direction.
3. The method according to claim 1, wherein when marker rectangles with the same power source identifier intersect, the calculating and drawing a power source main line according to the power source main line marker in the top-level cell includes:
when drawing a power supply main line in the vertical direction, firstly rotating the top layer unit by 90 degrees anticlockwise, covering and merging a plurality of marked rectangles with the same power supply identification in the horizontal direction, then rotating the top layer unit by 90 degrees clockwise, and taking the covered and merged rectangles as metal layer rectangles of the power supply main line in the vertical direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the vertical direction.
4. The method for obtaining the power main line of the memory layout according to claim 2 or 3, wherein before the overlapping and merging the plurality of marked rectangles with the same power source identifier in the horizontal direction, the method further comprises:
the marker rectangle on the top level cell is extended to the macrocell width.
5. The method for obtaining the power main line of the memory layout according to claim 4, wherein the performing the overlay merging of the plurality of marked rectangles having the same power source identifier in the horizontal direction includes:
covering and combining the intersected marked rectangles with the same power supply identification to form a covered rectangle;
if the covering rectangle is intersected with other marking rectangles with the same power supply identification, covering and combining the covering rectangle and the other marking rectangles to form a new covering rectangle;
and if the coverage rectangles with the same power supply identification are intersected, covering and merging the intersected coverage rectangles to form a new coverage rectangle.
6. The method according to claim 1, wherein when the marked rectangles with the same power source identifier do not intersect, the calculating and drawing the power source main line according to the power source main line mark in the top-level cell includes:
and taking each marking rectangle as a metal layer rectangle of the power supply main line corresponding to the power supply identifier.
7. The method according to claim 6, wherein before the step of using each marked rectangle as the metal layer rectangle of the power supply main line corresponding to the power supply identifier, the method further comprises:
the marker rectangle on the top level cell is extended to the macrocell width.
8. The method for obtaining the power supply main line of the layout of the memory according to claim 1, wherein the layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming.
9. An apparatus for obtaining a power main line of a memory layout, comprising:
the layout basic unit comprises an adding unit, a power supply unit and a power supply unit, wherein the adding unit is used for adding a power supply main line mark on each layout basic unit, the power supply main line mark comprises a mark rectangle and a power supply identifier, the mark rectangle represents an expected arrangement position of a power supply main line on the basic unit, and the power supply identifier represents a power supply individual number;
the splicing unit is used for splicing the layout basic units according to a layout programming splicing algorithm to form a top layer unit, and the power supply main line mark on each layout basic unit is used as the power supply main line mark of the top layer unit;
and the calculation drawing unit is used for calculating and drawing the power supply main line according to the power supply main line mark of the top layer unit.
10. The apparatus according to claim 9, wherein the calculation drawing unit is configured to, when marker rectangles with the same power source identifier intersect with each other, perform coverage merging on a plurality of marker rectangles with the same power source identifier in a horizontal direction when drawing a power source main line in the horizontal direction, and use the covered and merged rectangles as metal layer rectangles of the power source main line in the horizontal direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the horizontal direction.
11. The apparatus according to claim 9, wherein the calculation drawing unit is configured to, when marker rectangles with the same power source identifier intersect with each other, rotate the top-level unit counterclockwise by 90 degrees first, overlay and merge multiple marker rectangles with the same power source identifier in the horizontal direction, rotate the top-level unit clockwise by 90 degrees, and use the overlaid and merged rectangles as metal layer rectangles of the power source main line in the vertical direction; and taking other marked rectangles which are not intersected with the overlaid and combined rectangle and have the same power supply identification as the metal layer rectangles of the power supply main line in the vertical direction.
12. The apparatus according to claim 10 or 11, further comprising a first expanding unit, configured to expand the marker rectangle on the top-level cell to a macrocell width before the computing and drawing unit performs overlay merging on the plurality of marker rectangles with the same power source identifier in the horizontal direction.
13. The apparatus according to claim 12, wherein the calculation drawing unit is configured to perform coverage merging on intersecting marked rectangles with the same power source identifier to form a covered rectangle; when the covering rectangle is intersected with other marking rectangles with the same power supply identification, covering and combining the covering rectangle and the other marking rectangles to form a new covering rectangle; and when the coverage rectangles with the same power source identification are intersected, performing coverage combination on the intersected coverage rectangles to form a new coverage rectangle.
14. The apparatus according to claim 9, wherein the calculation drawing unit is configured to, when marker rectangles with the same power identifier do not intersect with each other, use each marker rectangle as a metal layer rectangle of the power main line corresponding to the power identifier.
15. The apparatus according to claim 14, further comprising a second expansion unit, configured to expand, by the computation drawing unit, the marker rectangle on the top-level cell to the width of the macro cell before the marker rectangle is used as the metal layer rectangle of the power supply main line corresponding to the power supply identifier.
16. The apparatus according to claim 9, wherein the layout programming splicing algorithm is a splicing algorithm of layout basic units in layout programming.
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Citations (3)
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|---|---|---|---|---|
| US6598206B2 (en) * | 2001-05-10 | 2003-07-22 | International Business Machines Corporation | Method and system of modifying integrated circuit power rails |
| US6609242B1 (en) * | 2001-07-20 | 2003-08-19 | Hewlett-Packard Development Company, L.P. | Automated creation of power distribution grids for tiled cell arrays in integrated circuit designs |
| CN103106294A (en) * | 2012-12-24 | 2013-05-15 | 西安华芯半导体有限公司 | Territory programming method for static random access memory compiler |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6598206B2 (en) * | 2001-05-10 | 2003-07-22 | International Business Machines Corporation | Method and system of modifying integrated circuit power rails |
| US6609242B1 (en) * | 2001-07-20 | 2003-08-19 | Hewlett-Packard Development Company, L.P. | Automated creation of power distribution grids for tiled cell arrays in integrated circuit designs |
| CN103106294A (en) * | 2012-12-24 | 2013-05-15 | 西安华芯半导体有限公司 | Territory programming method for static random access memory compiler |
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