CN108446412B - Memory compiling method and device and generated memory - Google Patents
Memory compiling method and device and generated memory Download PDFInfo
- Publication number
- CN108446412B CN108446412B CN201710083864.8A CN201710083864A CN108446412B CN 108446412 B CN108446412 B CN 108446412B CN 201710083864 A CN201710083864 A CN 201710083864A CN 108446412 B CN108446412 B CN 108446412B
- Authority
- CN
- China
- Prior art keywords
- memory
- gate
- level
- unit
- definition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a memory compiling method and device and a generated memory. When the structured definition is carried out on the storage array of the memory, the structured definition is firstly carried out on the storage unit, the structured definition of the storage unit is repeatedly called according to the number of bits and the number of terms of the memory to form the structured definition of the storage array, the structure of the formed storage array of the memory is regular, therefore, the time sequence performance is improved, the layout and the wiring are easy to control due to the regular storage array, and the performance is high in the aspects of area, controllable layout and the like. The memory cell is transparently visible based on the internal path of the gate level cell, thereby facilitating the modification of the internal circuit of the memory by a user and facilitating the subsequent static timing analysis.
Description
Technical Field
The present invention relates to the field of memory system technology for digital computer systems, and in particular, to a memory compiling method and apparatus, and a generated memory.
Background
A semiconductor memory (memory) is a memory using a semiconductor circuit as a storage medium, and has been developed for over 50 years since the first 60 th century. In today's chips more than 70% of the transistors are used in memories, and this ratio will continue to increase in the foreseeable future. This situation is more pronounced at the system level, with semiconductor memory capacities of hundreds of gigabytes and even more than a few Tbytes being included in high performance workstations and computers, and this capacity continues to grow as integrated circuit technology advances. At present, the production of various types of memories and the ordering of market share thereof are DRAM, SRAM, ROM, EPROM, E2PROM and Flash in turn. Semiconductor memory is generally considered to be the most important microelectronic device in the design of digital logic systems, including microprocessor or SoC (system on chip) based systems from satellite to consumer electronics.
Many integrated circuit design companies are working on developing intellectual property cores for memories for commercial purposes, and many chip manufacturers (foundries) also have their own memory compilers, such as TSMC, SMIC, UMC, etc., to provide customers with IPs for a variety of memories, often designed in a fully customized manner down to the pipeline level. In the prior art, a method for generating a memory is to automatically generate a memory by using a memory compiler provided by a chip manufacturer, a memory unit module generated by the memory compiler can be an SRAM, a ROM, a Flash, and the like, and the memory compiler can generate memory unit modules with different sizes and can optimize the area and the speed of the unit modules. The user generally generates a GDSII file and a netlist file of the desired memory module unit, etc. according to a Generator (Generator) of a memory compiler.
In the second method for generating the memory in the prior art, the memory is generated by a third-party logic synthesis tool (Design Compiler), a Design library (Design Ware) is provided by an integrated circuit Design tool manufacturer and is essentially realized by the logic level of a register file, and the third-party logic synthesis tool calls the Design library in the logic synthesis process to synthesize and generate a simple register file storage unit array gate-level netlist for the use of back-end physical Design.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
for the memory which is automatically generated by adopting a memory compiler, the memory generated by the compiler is opaque to the design flow based on standard cells in the digital back-end design, and a user only sees one macro cell and cannot modify the circuit and layout in the memory. The lib document file can only be generated by a generator of a memory compiler in Static Timing Analysis (STA) to obtain the timing information of the static timing analysis, the type, the size and the communication mode of a device on an internal path of the lib document file are invisible, delay information of the internal device is more invisible, great inconvenience is brought to the static timing analysis, and the analysis accuracy is reduced. For a memory generated by a third-party logic synthesis tool (Design Compiler), the memory generated by the Compiler is transparent to a Design flow based on a standard cell in digital back-end Design, but the readability of a netlist generated by the method is low, the result of netlist logic synthesis is not fixed, the readability of internal logic is poor, and layout and wiring are not easy to control, so that the performance such as time sequence, area, layout controllability and the like is poor.
Disclosure of Invention
The invention provides a memory compiling method and device and a generated memory, wherein the generated memory is transparent and visible based on a gate-level standard cell, so that a user can modify an internal circuit of the memory conveniently and the subsequent static time sequence analysis is facilitated, meanwhile, the memory forms a regular memory array structure based on the gate-level standard cell, the layout and the wiring are easy to control, and the performance in the aspects of time sequence, area, layout controllability and the like is higher.
In one aspect, the present invention provides a memory compilation method, comprising:
receiving user requirement definition and memory structure configuration parameters input by a user;
receiving a structural definition of a memory input by a user, wherein the structural definition of the memory comprises a structural definition of a storage unit and a structural definition of a read/write decoding circuit;
based on a gate level unit library, repeatedly calling the structural definition of the storage unit according to the bit number and the item number of the storage in the storage structure configuration parameters to generate the structural definition of the storage array;
generating a hardware description language model according to the structural definition of the storage array and the structural definition of the read/write decoding circuit;
calling a standard gate-level unit and a full-custom gate-level unit in the gate-level unit library according to the hardware description language model to generate a netlist;
and performing regular layout, clock tree generation and wiring according to the netlist and the user requirement definition to obtain a layout of the memory.
In another aspect, the present disclosure provides a memory compiling apparatus, including:
the first receiving unit is used for receiving user requirement definition and memory structure configuration parameters input by a user;
the second receiving unit is used for receiving the structural definition of the memory input by a user, wherein the structural definition of the memory comprises the structural definition of the storage unit and the structural definition of the read/write decoding circuit;
the first generation unit is used for repeatedly calling the structural definition of the storage unit according to the digit and the item number of the storage in the storage structure configuration parameters based on a gate level unit library to generate the structural definition of the storage array;
the second generating unit is used for generating a hardware description language model according to the structural definition of the storage array and the structural definition of the read/write decoding circuit;
the third generation unit is used for calling a standard gate-level unit and a full-custom gate-level unit in the gate-level unit library according to the hardware description language model to generate a netlist;
and the fourth generating unit is used for performing regular layout, clock tree generation and wiring according to the netlist and the user requirement definition to obtain the layout of the memory.
In a third aspect, an embodiment of the present invention further provides a memory, where the memory is prepared by using the above memory compiling method.
According to the memory compiling and generating method and device and the generated memory provided by the embodiment of the invention, firstly, the storage array and the read-write decoding which form the memory are structurally defined, a hardware description language module is formed according to the structural definition, a netlist is formed according to the hardware description language module, and then a layout is formed through regular layout and wiring. When the structured definition is carried out on the storage array of the memory, the structured definition is firstly carried out on the storage unit, the structured definition of the storage unit is repeatedly called according to the number of bits and the number of terms of the memory to form the structured definition of the storage array, the structure of the formed storage array of the memory is regularized, and therefore the time sequence performance is improved, the layout and the wiring are easy to control due to the regularized storage array, and the performance in the aspects of area, controllable layout and the like is improved. The memory cell can be constructed by adopting a standard gate-level cell or a full-custom structure, and is transparent and visible based on an internal path of the gate-level cell, so that a user can modify an internal circuit of the memory conveniently and the subsequent static timing analysis is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a memory compilation generation method according to an embodiment of the present invention;
FIG. 2 is a detailed flowchart of a memory compilation generation method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a register file structure;
FIG. 4 is a schematic diagram of a memory cell of a two-write and two-read memory;
FIG. 5 is a diagram illustrating a layout and routing structure in a memory compiling and generating method according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a memory compiling and generating device according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The invention provides a memory compiling and generating method, as shown in fig. 1, the method comprises the following steps:
s11, receiving user requirement definition and memory structure configuration parameters input by a user;
s12, receiving a structural definition of a memory input by a user, wherein the structural definition of the memory comprises a structural definition of a storage unit and a structural definition of a read/write decoding circuit;
s13, based on a gate level unit library, repeatedly calling the structural definition of the storage unit according to the bit number and the item number of the storage in the storage structure configuration parameters to generate the structural definition of the storage array;
s14, generating a hardware description language model according to the structural definition of the storage array and the structural definition of the read/write decoding circuit;
s15, calling a standard gate level unit and a full-custom gate level unit in the gate level unit library according to the hardware description language model to generate a netlist;
and S16, performing regular layout, generating a clock tree and wiring according to the netlist and the user requirement definition to obtain a layout of the memory.
The memory compiling and generating method provided by the embodiment of the invention comprises the steps of firstly, carrying out structured definition on a memory array and read-write decoding which form a memory, forming a hardware description language module according to the structured definition, forming a netlist according to the hardware description language module, and further forming a layout through regular layout and wiring. When the structural definition is carried out on the storage array of the memory, the structural definition is firstly carried out on the storage unit, the structural definition of the storage unit is repeatedly called according to the bit number and the item number of the memory to form the structural definition of the storage array, the structure of the formed storage array of the memory is regulated, and therefore the time sequence performance is improved, the layout and the wiring are easy to control due to the regulated storage array, and the performance in the aspects of area, layout controllability and the like is improved. The memory unit can be constructed by adopting a standard gate-level unit or a full-custom unit, and is transparent and visible based on the internal path of the gate-level unit, so that the modification of the internal circuit of the memory by a user and the subsequent static timing analysis are facilitated.
Optionally, the gate level cell library includes a time sequence library and a physical layout of the standard gate level cell and the fully-customized gate level cell.
Optionally, the internal circuits of the memory cell and the read/write decoding circuit are constructed by standard gate level cells in the gate level cell library, or the internal circuits of the memory cell and the read/write decoding circuit are constructed by fully-customized gate level cells in the gate level cell library.
Optionally, the user requirement definition includes: the shape, size, input port location, and output port location of the memory.
Optionally, the memory structure configuration parameters include: the number of bits in the memory, the number of entries, the number of read ports, the number of write ports, the aspect ratio of the memory, and whether the memory has write enable.
Optionally, the storage unit is a single-port read-write or multi-port read-write. In the back end design of a digital integrated circuit, especially in the design of a processor chip, a plurality of memory cell circuits are needed, the scale of the circuits is not large, the memory size is generally about several K bits, and the composition units of the circuits can be different according to different logic functions to be completed by the circuits. The characteristic of diversified functional requirements directly influences the implementation mode of the circuit, for example, some memories require multi-port reading and writing, and thus when the circuit is implemented, the multi-port reading and writing can be ensured to be simultaneously carried out by the multi-port reading and writing. The memory macro-cell generated by the traditional custom memory compiler is advantageous in terms of area and performance, but it only satisfies simultaneous read/write of two ports at most, and its design is non-transparent, and it is a black box for back-end designers, which brings great inconvenience to Static Timing Analysis (STA) due to the invisibility of its internal paths and cells. Meanwhile, because the design of the memory is non-transparent, a user cannot modify the memory. The memory designed based on the third-party tool has poor performance in terms of timing, area, layout controllability and the like, although the design is transparent.
According to the memory compiling method provided by the invention, when the structural definition is carried out on the memory array of the memory, the structural definition is firstly carried out on the memory unit, the structural definition of the memory array is formed by repeatedly calling the structural definition of the memory unit according to the digit and the number of terms of the memory, so that the structure of the generated memory array of the memory is regular, the time sequence performance is improved, the layout and the wiring are easy to control due to the regular memory array, and the performance in the aspects of area, controllable layout and the like is higher. The memory cell can be constructed by adopting a standard gate-level cell or a full-custom structure, and is transparent and visible based on an internal path of the gate-level cell, so that a user can modify an internal circuit of the memory conveniently and the subsequent static timing analysis is facilitated.
Fig. 2 shows a detailed flowchart of a memory compiling and generating method according to an embodiment of the present invention, where the memory compiling and generating method is based on a whole digital integrated circuit back-end design process. The digital integrated circuit back end design has two main characteristics, one is based on standard cell design, and the other is Static Timing Analysis (STA). First, modern integrated circuit designs are based on standard cell designs, and chip manufacturers provide their users with a library of standard cells that can be manufactured by the chip manufacturers, where the library contains layouts of various components that are equal in height and unequal in width and called standard cells. A user can use a special layout and wiring tool to automatically call the standard cells according to design requirements to complete layout design, so that the design efficiency is greatly improved. The so-called Static Timing Analysis (STA) is an exhaustive analysis method to measure the circuit performance. It extracts all the timing paths of the whole circuit, finds out the error violating the timing constraint by calculating the delay propagation of the signal along the path, mainly checking if the setup time and hold time meet the requirements, and they are obtained by analyzing the maximum path delay and the minimum path delay respectively. In the flow of the memory compiling method provided by the embodiment of the invention, firstly, a user requirement definition, a memory structure configuration parameter and a gate level unit library are input. The user requirement definition mainly comprises the shape, the size, the input/output port position and the like of the memory. The configuration parameters of the memory structure mainly comprise the number of bits, the number of terms, the number of read ports, the number of write ports, the width-to-length ratio of the memory, whether write enable exists or not and the like of the memory. Taking the register file storage structure as an example, table 1 defines configuration parameters of a part of the register file type storage structure, where NDCbit is the number of write or read address bits, nbit is the input/output data width, nword is the number of storage data items, nwrite is the number of write-once data items, and Nread is the number of read-once data items.
TABLE 1
The gate level unit library comprises standard gate level units and full-custom gate level units, and the standard gate level units in the gate level unit library comprise standard unit time sequence libraries, physical layouts and the like under different threshold types, channel lengths and process angles. A fully customized gate level cell is a cell that is customized to the needs of performance.
Next, the structural definition of each module constituting the memory is described, and in this embodiment, the compiling generation of the register file type memory structure is taken as an example, and as shown in fig. 3, the register file type memory structure mainly includes read address decoding, write address decoding, a data memory array, and the like, and each part can be designed separately.
First, a memory cell is defined to be a basic memory structure in a memory, and various register file type memory structures are formed based on the memory cell, and the basic function of the memory cell is to complete a memory function for 1 bit (0 or 1). A memory is a memory array made up of a plurality of such bitcells. The memory bit unit is divided into single-port reading and writing and multi-port reading and writing, and the multi-port reading and writing has higher realization difficulty in function and circuit realization. Taking a two-write and two-read memory as an example, the basic circuit structure is shown in fig. 4, where Wen0 and Wen1 are write strobe signals obtained by decoding write addresses, and Ren0 and Ren1 are read strobe signals obtained by decoding read addresses. Din0 and Din1 are data signal inputs, and Dout0 and Dout1 are data signal outputs. The internal circuit structure of the storage unit can be constructed by adopting standard gate-level units in a gate-level unit library and can also be realized by full customization according to performance requirements, and the internal circuit structure of the storage unit can realize further full customization optimization of the storage unit by adopting types such as a trigger, a latch and the like, so that the performance of data storage is further improved.
After the structural definition of the storage unit is completed, the structural definition of the storage unit is repeatedly called according to the bit number and the term number of the storage in the storage structure configuration parameter, and the structural definition of the storage array is generated, so that the storage array formed by the repeatedly called storage units has the bit number and the term number of the storage in the storage structure configuration parameter. The structural definition of the storage array is formed by repeatedly calling the standard storage unit, so that the structure of the storage array of the finally generated register file storage structure is regulated, the time sequence performance is improved, the layout and the wiring are easy to control due to the regulated storage array, and the performance in the aspects of area, layout controllability and the like is improved. In addition, the memory unit can be constructed by adopting a standard gate-level unit or a full-custom unit, and the internal path of the gate-level unit is transparently visible, so that the modification of the internal circuit of the memory by a user and the subsequent static timing analysis are facilitated. The generated register file storage structure has the advantages of available memory size and read-write port number, high flexibility and high compatibility, the maximum port number can support eight-write eight-read, and the maximum storage capacity is 2048x 2048=4M bit.
After the memory array is structurally defined, the read-write decoding circuit is structurally defined, and an internal circuit structure in the decoding circuit can be constructed by adopting a standard gate-level unit or a full-custom construction.
After each module forming a register file storage structure is structurally defined, based on the structural definition of the storage array and the structural definition of the read-write decoding circuit, a hardware description language model is built by adopting relevant parameters in the structural definition of the storage array and the structural definition of the read-write decoding circuit, and then the hardware description language model is generated. And calling a standard gate-level unit and a full-custom gate-level unit in the gate-level unit library based on the hardware description language model, and generating a netlist through logic synthesis.
And according to the netlist and the user requirement definition, performing layout through layout planning, generating a clock tree, and wiring to obtain a layout of the memory, and completing compiling of the memory. Wherein, the layout refers to the arrangement position of the unit in the gate-level netlist. The layout rule is set during physical layout according to the change of the size of the memory and the number of ports, the size of the whole layout area is estimated, and the reasonability of the layout is ensured. The layout mode can adopt an algorithm of a user script to realize automatic layout, and can also utilize a regular automatic layout tool such as an ICC (Integrated Circuit) to carry out layout. Taking the algorithm of the user script as an example, relevant parameters in the algorithm are defined, and the position of the storage unit in the layout can be calculated by controlling the parameters according to the actual use requirements, so that the rapid, automatic, compact and regular layout is realized. Then, the trend of the clock critical path can be controlled by adopting a gating clustering mode to generate a clock tree. And then wiring is carried out, and when wiring is carried out, the power supply line and the clock signal are firstly wired, and then the signal line is wired, so that the purpose of meeting the timing sequence to the maximum extent is achieved.
The layout mode of the register file type memory can be adjusted according to input ports, output ports, keys, gated clustering and other factors, semi-customized design is implemented, and the trend and the time delay of a read-write path of data after the design is completed are completely controllable. The layout mode can be varied according to the design requirement, and the following description is introduced in a spatial layout mode in a clock gating clustering mode, and the structure of the spatial layout mode is shown in fig. 5. The same item of the storage array is controlled by adopting the same clock gating, the same item reaches each item of the storage unit through a branch, and the write bit strobe signal and the read bit strobe signal of which the write address and the read address are decoded also carry out gating control on each storage unit. The gating and the decoder are both arranged in the middle, and the path reaching each storage unit adopts buffer control, so that the time delay reaching the storage units on two sides is balanced. And the clock gating clustering mode is adopted, so that the space is saved, and the construction of a clock tree and the splicing of digits are facilitated. In the layout process, the decoded gating logic of the read/write address reaches each memory cell through a buffer (buffer), and the size and the position of the inserted buffer can be accurately controlled through an algorithm to control the routing direction.
After the gate-level netlist formed after logic synthesis is subjected to Layout and wiring, static timing analysis and SPICE simulation, DRC (Design Rule Check) and LVS (Layout vs schema Check) Check and the result is output. The output result comprises a Verilog model, a netlist file, a DEF file, a synopsis.lib file and a layout file, and the file format and the back-end process related to most IC back-end design processes are met.
The memories generated by the invention are all designed based on gate-level standard cells, the generated intermediate results are compatible and visible in common digital back-end design tools, and the method has better support for Static Timing Analysis (STA), which is a common timing performance analysis means in back-end design. The output result of the configurable memory compiler based on the gate-level standard cell has 5 items, including a Verilog model, a netlist file, a DEF file, a synopsis. Lib file and a layout file, and meets the file format and the back-end eco flow related to most IC back-end design flows.
The memory storage array generated by the invention has flexible and quick generation mode, overcomes the defect that the memory generated by the full-custom memory compiler is invisible as a macro unit in the back-end static time sequence analysis, and has advantages in performance and area compared with the memory generated by a third-party tool. In performance result analysis, compared with a logic level register file storage mode, the invention has the advantage that the performance indexes such as time sequence, area and the like are greatly improved. The experimental evaluation result under a certain 40nm process environment shows that the performance of the memory generated by the compiler is improved by 8% and the area is saved by 10% compared with the register file generated by the memory compiler. Compared with the performance of a memory compiler provided by a third-party process manufacturer, the performance of the memory compiler is improved by 30%, and the performance of the memory with the same scale designed by a full-customization mode is improved by more than 70%.
An embodiment of the present invention further provides a memory compiling and generating apparatus, as shown in fig. 6, the apparatus includes:
a first receiving unit 61, configured to receive a user requirement definition and a memory structure configuration parameter input by a user;
a second receiving unit 62, configured to receive a structural definition of a memory input by a user, where the structural definition of the memory includes a structural definition of a storage unit and a structural definition of a read/write decoding circuit;
a first generating unit 63, configured to repeatedly invoke the structural definition of the storage unit according to the number of bits and the number of terms of the memory in the memory structure configuration parameter, based on the gate level cell library, and generate the structural definition of the storage array;
a second generating unit 64, configured to generate a hardware description language model according to the structural definition of the storage array and the structural definition of the read/write decoding circuit;
a third generating unit 65, configured to invoke a standard gate-level cell and a full-custom gate-level cell in the gate-level cell library according to the hardware description language model to generate a netlist;
and a fourth generating unit 66, configured to perform a regular layout, generate a clock tree, and route according to the netlist and the user requirement definition to obtain a layout of the memory.
The memory compiling and generating device provided by the embodiment of the invention firstly carries out structured definition on the memory array and the read-write decoding which form the memory, forms a hardware description language module according to the structured definition, forms a netlist according to the hardware description language module, and further forms a layout through regular layout and wiring. When the structured definition is carried out on the storage array of the memory, the structured definition is firstly carried out on the storage unit, the structured definition of the storage unit is repeatedly called according to the number of bits and the number of terms of the memory to form the structured definition of the storage array, the structure of the formed storage array of the memory is regularized, and therefore the time sequence performance is improved, the layout and the wiring are easy to control due to the regularized storage array, and the performance in the aspects of area, controllable layout and the like is improved. The memory cell can be constructed by adopting a standard gate-level cell or a full-custom structure, and is transparent and visible based on an internal path of the gate-level cell, so that a user can modify an internal circuit of the memory conveniently and the subsequent static timing analysis is facilitated.
Optionally, the gate level cell library includes a time sequence library and a physical layout of the standard gate level cell and the fully customized gate level cell.
Optionally, the internal circuits of the memory cell and the read/write decoding circuit are constructed by standard gate level cells in the gate level cell library, or the internal circuits of the memory cell and the read/write decoding circuit are constructed by fully customized gate level cells in the gate level cell library.
Optionally, the user requirement definition includes: the shape, size, input port location, and output port location of the memory.
Optionally, the memory fabric configuration parameters include: the number of bits in the memory, the number of entries, the number of read ports, the number of write ports, the aspect ratio of the memory, and whether the memory has write enable.
Optionally, the storage unit is a single-port read-write or multi-port read-write.
In a third aspect, an embodiment of the present invention further provides a memory, where the memory is prepared by using the above memory compiling and generating method.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A memory compilation method, comprising:
receiving user requirement definition and memory structure configuration parameters input by a user;
receiving a structural definition of a memory input by a user, wherein the structural definition of the memory comprises a structural definition of a storage unit and a structural definition of a read/write decoding circuit;
based on a gate level unit library, repeatedly calling the structural definition of the storage unit according to the bit number and the item number of the storage in the storage structure configuration parameters to generate the structural definition of the storage array, wherein the storage unit is transparent and visible based on the internal path of the gate level unit;
generating a hardware description language model according to the structural definition of the storage array and the structural definition of the read/write decoding circuit;
calling standard gate-level units and full-custom gate-level units in the gate-level unit library according to the hardware description language model to generate a netlist;
performing regularized layout according to the netlist and the user requirement definition, wherein the layout refers to arranging positions of units in the gate-level netlist;
controlling the trend of a clock key path by adopting a gating clustering mode so as to generate a clock tree, wiring to obtain a layout of a memory, and after wiring, further comprising the following steps: outputting a result, the output result including at least a DEF file.
2. The memory compilation method of claim 1, wherein the bank of gate level cells comprises a sequential bank and a physical layout of the standard gate level cells and the fully custom gate level cells.
3. The memory compilation method of claim 2, wherein the memory cells and the internal circuitry of the read/write decoding circuit are implemented by standard gate-level cells in the gate-level cell library, or wherein the memory cells and the internal circuitry of the read/write decoding circuit are implemented by fully-customized gate-level cells in the gate-level cell library.
4. The memory compilation method of claim 1, wherein the user requirement definition comprises: the shape, size, input port location, and output port location of the memory.
5. The memory compilation method of claim 1, wherein the memory structure configuration parameters comprise: the number of bits of the memory, the number of terms, the number of read ports, the number of write ports, the aspect ratio of the memory, and whether the memory has write enable.
6. The memory compilation method of claim 1, wherein the memory unit is one-port read-write or multi-port read-write.
7. A memory compilation apparatus, comprising:
the first receiving unit is used for receiving user requirement definition and memory structure configuration parameters input by a user;
the second receiving unit is used for receiving the structural definition of the memory input by a user, wherein the structural definition of the memory comprises the structural definition of the storage unit and the structural definition of the read/write decoding circuit;
the first generation unit is used for repeatedly calling the structural definition of the storage unit according to the number of bits and the number of terms of the storage in the storage structure configuration parameters based on a gate-level unit library to generate the structural definition of the storage array, wherein the storage unit is transparent and visible based on an internal path of the gate-level unit;
the second generating unit is used for generating a hardware description language model according to the structural definition of the storage array and the structural definition of the read/write decoding circuit;
the third generation unit is used for calling a standard gate-level unit and a full-custom gate-level unit in the gate-level unit library according to the hardware description language model to generate a netlist;
the fourth generation unit is used for performing regular layout according to the netlist and the user requirement definition, wherein the layout refers to the arrangement positions of the units in the gate-level netlist, the trend of a clock key path is controlled in a gating clustering mode so as to generate a clock tree, and the layout of the memory is obtained through wiring;
wherein the fourth generation unit is further configured to output a result after the wiring, the output result including at least a DEF file.
8. The memory compilation device of claim 7, wherein the bank of gate level cells comprises a sequential bank and a physical layout of the standard gate level cells and fully-custom gate level cells.
9. The memory compilation device of claim 8, wherein the memory cells and the internal circuitry of the read/write decoding circuitry are implemented by standard gate-level cells in the gate-level cell library, or wherein the memory cells and the internal circuitry of the read/write decoding circuitry are implemented by fully-customized gate-level cells in the gate-level cell library.
10. The memory compilation device of claim 7, wherein the user requirement definition comprises: the shape, size, input port location, and output port location of the memory.
11. The memory compilation device of claim 7, wherein the memory fabric configuration parameters comprise: the number of bits in the memory, the number of entries, the number of read ports, the number of write ports, the aspect ratio of the memory, and whether the memory has write enable.
12. A memory, wherein the memory is prepared by the memory compiling method of any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710083864.8A CN108446412B (en) | 2017-02-16 | 2017-02-16 | Memory compiling method and device and generated memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710083864.8A CN108446412B (en) | 2017-02-16 | 2017-02-16 | Memory compiling method and device and generated memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108446412A CN108446412A (en) | 2018-08-24 |
| CN108446412B true CN108446412B (en) | 2023-01-24 |
Family
ID=63190576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710083864.8A Active CN108446412B (en) | 2017-02-16 | 2017-02-16 | Memory compiling method and device and generated memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108446412B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109670255B (en) * | 2018-12-26 | 2020-04-07 | 北京华大九天软件有限公司 | Typical simulation condition recommendation method for time sequence parameter clustering |
| CN110164489B (en) * | 2019-05-28 | 2021-05-07 | 珠海创飞芯科技有限公司 | Correlation method and system for optimizing Nor Flash memory array area |
| CN111796831B (en) * | 2020-06-24 | 2023-02-28 | 苏州大学 | Compiling method and device for multi-chip compatibility |
| US11347920B2 (en) * | 2020-10-21 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit synthesis optimization for implements on integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541850A (en) * | 1994-05-17 | 1996-07-30 | Vlsi Technology, Inc. | Method and apparatus for forming an integrated circuit including a memory structure |
| CN102376348A (en) * | 2010-08-20 | 2012-03-14 | 中国科学院微电子研究所 | Low-power dynamic random memory |
| CN103106294A (en) * | 2012-12-24 | 2013-05-15 | 西安华芯半导体有限公司 | Territory programming method for static random access memory compiler |
-
2017
- 2017-02-16 CN CN201710083864.8A patent/CN108446412B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541850A (en) * | 1994-05-17 | 1996-07-30 | Vlsi Technology, Inc. | Method and apparatus for forming an integrated circuit including a memory structure |
| CN102376348A (en) * | 2010-08-20 | 2012-03-14 | 中国科学院微电子研究所 | Low-power dynamic random memory |
| CN103106294A (en) * | 2012-12-24 | 2013-05-15 | 西安华芯半导体有限公司 | Territory programming method for static random access memory compiler |
Non-Patent Citations (2)
| Title |
|---|
| 嵌入式SRAM编译器的容量扩展方法的研究;潘非;《中国优秀硕士学位论文全文数据库 信息科技辑》;20140915(第9期);第I137-31页 * |
| 面向嵌入式SOC的Memory_Compiler设计与实现;龚展立;《中国优秀硕士学位论文全文数据库 信息科技辑》;20121015(第10期);第I137-31页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108446412A (en) | 2018-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108446412B (en) | Memory compiling method and device and generated memory | |
| US9390212B2 (en) | Methods and apparatus for synthesizing multi-port memory circuits | |
| JPH10293782A (en) | Layout compiling method and design system | |
| US11783104B2 (en) | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | |
| US9727681B2 (en) | Generating specific memory models using generic memory models for designing memories in VLSI design | |
| WO2014106038A1 (en) | Local clock skew optimization and incremental clock tree synthesis | |
| Ataei et al. | AMC: An asynchronous memory compiler | |
| Gibiluka et al. | A bundled-data asynchronous circuit synthesis flow using a commercial EDA framework | |
| US20160371411A1 (en) | Scaling of Integrated Circuit Design Including High-Level Logic Components | |
| US7844937B2 (en) | Method and apparatus for making a semiconductor device using hardware description having merged functional and test logic blocks | |
| US9690890B1 (en) | Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design | |
| US20090241082A1 (en) | Method and System for Generating an Accurate Physical Realization for an Integrated Circuit Having Incomplete Physical Constraints | |
| US20220147683A1 (en) | Method for implementing an integrated circuit comprising a random-access memory-in-logic | |
| Marinberg et al. | Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach | |
| Madhavan et al. | Physical Design and Implementation of Lakshya-Sub-system of Built in Self Test System | |
| US10157253B2 (en) | Multi-bit-mapping aware clock gating | |
| US10354032B2 (en) | Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus | |
| Han et al. | Clocked and asynchronous FIFO characterization and comparison | |
| Patan et al. | Design and implementation of optimized register file for streaming applications | |
| Shahu | ASIC Design Implementation of UART using Synopsys EDA tools | |
| Ataei et al. | A unified memory compiler for synchronous and asynchronous circuits | |
| Melnikova et al. | Using multi-FPGA systems for ASIC prototyping | |
| Das | Physical design of monolithic 3D integrated systems and memory | |
| Luk et al. | Development of a high bandwidth merged logic/DRAM multimedia chip | |
| Chang | Concept of Logic Synthesis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Applicant after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Applicant before: LOONGSON TECHNOLOGY Corp.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |