CN108446412A - Memory Compilation Method, device and the memory of generation - Google Patents
Memory Compilation Method, device and the memory of generation Download PDFInfo
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Abstract
The present invention provides a kind of memory Compilation Method, device and the memories of generation, first to constituting the storage array of memory, the definition of read-write decoding progress structuring, hardware description language module is formed according to the definition of its structuring, netlist is formed according to hardware description language module, and then domain is formed by the layout of regularization, wiring.When the storage array to memory carries out stzwctlrred definition, stzwctlrred definition first is carried out to storage unit, the stzwctlrred definition for according to the digit of memory, item number repeating that the stzwctlrred definition of storage unit is called to form storage array, the structure of the storage array of the memory of formation is regularization, to improve timing performance, the storage array of regularization makes placement-and-routing be easy to control, higher in controllable etc. the performance of area, layout.Storage unit is transparent based on gate leve unit inner track as it can be seen that consequently facilitating user modifies to memory inside circuit and convenient for subsequent static timing analysis.
Description
Technical field
The present invention relates to the storage system technical field of digital computing system more particularly to a kind of memory compiling sides
Method, device and the memory of generation.
Background technology
Semiconductor memory (memory) is a kind of memory using semiconductor circuit as storaging medium, is occurred earliest
Twentieth century sixties, more than 50 years development course is had been subjected to so far.In current chip, 70% or more transistor
It is in memory, in foreseeable future, this ratio will also to continue growing.This situation is in system-level layer
Show more prominent on secondary, the semiconductor memory capacity for including in high-performance workstation and computer is up to hundreds of G bytes
Even more than number T bytes, and as the development of integrated circuit technique this capacity is also in sustainable growth.Currently, various types
The sequence of the yield and its occupation rate of market of memory is followed successively by DRAM, SRAM, ROM, EPROM, E2PROM and Flash.Partly lead
Body memory be often viewed as digital logic system design in most important microelectronic component, these systems include from satellite to
System of the consumer electronics product based on microprocessor or SoC (systems-on-a-chip).
Many IC design companies are dedicated to the memory IP core heart of the research and development for commercial object, Hen Duoxin
Piece manufactory (Foundry) also has the memory compiler of oneself, such as TSMC, SMIC, UMC etc. to be supplied to client's multiple memorizers
IPs, this IPs is often lower to be designed to pipe grade using full custom mode.The method for generating memory in the prior art
First, automatically generating memory, the storage list that memory compiler generates using the memory compiler that chip maker provides
Element module can be SRAM, ROM, can also be Flash etc., and memory compiler can generate different size of memory list
Element module, and can accomplish the optimization of unit module area and speed.User is generally according to the generator of memory compiler
(Generator) GDSII file and the net meter file etc. to generate required memory module unit.
The method of memory is generated in the prior art second is that passing through third party's logic synthesis tool (Design Compiler)
Memory is generated, design library (Design Ware) is provided by integrated circuit design tool manufacturer, and essence is register file
The logic level of heap realizes that third party's logic synthesis tool calls design library in logic synthesis process, comprehensive to generate one simply
Register file memory cell array gate level netlist, for back-end physical design use.
In the implementation of the present invention, inventor has found at least to have the following technical problems in the prior art：
For automatically generating memory using memory compiler, the memory that compiler generates is designed in digital back-end
In be for the design cycle based on standard block it is opaque, user see only a macroelement, storage cannot be changed
Circuit inside device and domain.To the generator of memory compiler be relied on to generate in static timing analysis (STA)
.lib document files obtain its timing information, the type of device, size and mode of communicating on its inner track can not
See, the delay information of internal components is more invisible, brings huge inconvenience to static timing analysis, reduces the standard of analysis
True property.For generating memory, the storage that compiler generates by third party's logic synthesis tool (Design Compiler)
Device is transparent for the design cycle based on standard block in digital back-end design, but the netlist that this mode generates is readable
Property it is relatively low, be not fixed by the result of netlist logic synthesis, internal logic readability is poor, and placement-and-routing is not easy to control, to make
It is poor at performances such as sequential, area, layout controllabilitys.
Invention content
The present invention provides a kind of memory Compilation Method, device and the memory of generation, and the memory of generation is based on gate leve
Standard block is transparent visible, consequently facilitating when user modifies to memory inside circuit and is convenient for subsequent static
Sequence is analyzed, and simultaneous memory is based on gate leve standard block, the memory array structure of formation rule, and placement-and-routing is easy to control,
To higher in controllable etc. the performance of sequential, area, layout.
On the one hand, the present invention provides a kind of memory Compilation Method, the method includes：
Receive user demand definition input by user and memory construction configuration parameter；
The stzwctlrred definition of memory input by user is received, the stzwctlrred definition of the memory includes storage unit
The stzwctlrred definition of stzwctlrred definition and read/write decoding circuit；
Based on gate leve cell library, the digit of the memory in parameter is configured according to the memory construction and item number repeats to adjust
With the stzwctlrred definition of the storage unit, the stzwctlrred definition of storage array is generated；
Hardware is generated according to the stzwctlrred definition of the stzwctlrred definition of the storage array and the read/write decoding circuit to retouch
State language model；
The standard gate leve unit and full custom door in the gate leve cell library are called according to the hardware description language model
Grade unit generates netlist；
Regularization layout is carried out according to the netlist and user demand definition, generates Clock Tree, wiring to be deposited
The domain of reservoir.
On the other hand, the present invention provides a kind of memory compilation device, and described device includes：
First receiving unit configures parameter for receiving user demand definition input by user and memory construction；
Second receiving unit, the stzwctlrred definition for receiving memory input by user, the structuring of the memory
Definition includes the stzwctlrred definition of storage unit and the stzwctlrred definition of read/write decoding circuit；
First generation unit configures the memory in parameter for being based on gate leve cell library according to the memory construction
Digit and item number repeat to call the stzwctlrred definition of the storage unit, generate the stzwctlrred definition of storage array；
Second generation unit, for according to the stzwctlrred definition of the storage array and the knot of the read/write decoding circuit
Structureization definition generates hardware description language model；
Third generation unit, for calling the standard gate in the gate leve cell library according to the hardware description language model
Grade unit and full custom gate leve unit generate netlist；
4th generation unit, when for carrying out regularization layout according to the netlist and user demand definition, generating
Zhong Shu, wiring are to obtain the domain of memory.
The third aspect, the embodiment of the present invention also provide a kind of memory, and the memory uses memory described above
Compilation Method is prepared.
Memory provided in an embodiment of the present invention compiles generation method, device and the memory of generation, is deposited first to composition
The storage array of reservoir, read-write decoding carry out the definition of structuring, and hardware description language mould is formed according to the definition of its structuring
Block forms netlist according to hardware description language module, and then forms domain by the layout of regularization, wiring.To memory
Storage array carry out stzwctlrred definition when, first to storage unit carry out stzwctlrred definition, according to the digit of memory, item number weight
The stzwctlrred definition of polyphony storage unit forms the stzwctlrred definition of storage array, the knot of the storage array of the memory of formation
Structure is regularization, and to improve timing performance, the storage array of regularization makes placement-and-routing be easy to control, area,
Controllable etc. performance is laid out to improve.Standard gate leve cell formation or full custom structure may be used in storage unit, is based on gate leve
Unit inner track is transparent as it can be seen that consequently facilitating when user modifies to memory inside circuit and is convenient for subsequent static
Sequence is analyzed.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only
Some embodiments of the present invention without creative efforts, may be used also for those of ordinary skill in the art
With obtain other attached drawings according to these attached drawings.
Fig. 1 is the flow chart that memory of the embodiment of the present invention compiles generation method；
Fig. 2 is the detail flowchart that memory of the embodiment of the present invention compiles generation method；
Fig. 3 is the structural schematic diagram of register file；
Fig. 4 is the structural schematic diagram of two storage units for writing two reading memories；
Fig. 5 is the allocation wiring structure schematic diagram in memory of embodiment of the present invention compiling generation method；
Fig. 6 is the structural schematic diagram that memory of the embodiment of the present invention compiles generating means.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
The every other embodiment that personnel are obtained without making creative work, shall fall within the protection scope of the present invention.
The present invention provides a kind of memory compiling generation method, as shown in Figure 1, the method includes：
S11, user demand definition input by user and memory construction configuration parameter are received；
The stzwctlrred definition of S12, the stzwctlrred definition for receiving memory input by user, the memory includes that storage is single
The stzwctlrred definition of member and the stzwctlrred definition of read/write decoding circuit；
S13, it is based on gate leve cell library, the digit and item number weight of the memory in parameter is configured according to the memory construction
The stzwctlrred definition of the polyphony storage unit, generates the stzwctlrred definition of storage array；
S14, it is generated firmly according to the stzwctlrred definition of the storage array and the stzwctlrred definition of the read/write decoding circuit
Part description language model；
S15, standard gate leve unit in the gate leve cell library and complete fixed is called according to the hardware description language model
Gate leve unit processed generates netlist；
S16, regularization layout is carried out according to the netlist and user demand definition, generates Clock Tree, wiring to obtain
To the domain of memory.
Memory provided in an embodiment of the present invention compiles generation method, first storage array, the read-write to constituting memory
Decoding carries out the definition of structuring, hardware description language module is formed according to the definition of its structuring, according to hardware description language
Module forms netlist, and then forms domain by the layout of regularization, wiring.Structuring is carried out in the storage array to memory
When definition, stzwctlrred definition first is carried out to storage unit, the structure for calling storage unit is repeated according to the digit of memory, item number
Change the stzwctlrred definition that definition forms storage array, the structure of the storage array of the memory of formation is regularization, to carry
High timing performance, the storage array of regularization make placement-and-routing be easy to control, and are carried in controllable etc. the performance of area, layout
It is high.Storage unit may be used standard gate leve cell formation or full custom structure, based on gate leve unit inner track it is transparent as it can be seen that
Consequently facilitating user modifies to memory inside circuit and convenient for subsequent static timing analysis.
Optionally, the gate leve cell library include the standard gate leve unit and full custom gate leve unit timing sequence library and
Physical layout.
Optionally, the internal circuit of the storage unit and the read/write decoding circuit passes through in the gate leve cell library
Standard gate leve cell formation, alternatively, the internal circuit of the storage unit and the read/write decoding circuit passes through the gate leve
Full custom gate leve cell formation in cell library.
Optionally, the user demand, which defines, includes：Shape, size, input port position and the output port of memory
Position.
Optionally, memory construction configuration parameter includes：The digit of memory, read port number, write port number, is deposited item number
It is enabled whether reservoir length-width ratio, memory are write.
Optionally, the storage unit is single port read-write or multi-port read-write.In digital integrated electronic circuit rear end is designed,
Especially in processor chips design, many storage unit circuits are needed, the scale of these circuits is not big, amount of storage size
Generally in several K bits or so, different according to the logic function to be completed of circuit, the component units of circuit are multifarious.
The diversified feature of its functional requirement directly affects the realization method of circuit again, such as some memory requirement multiports are read
It writes, then we will accomplish ensure that multiple ports can be read while write when circuit is realized.Traditional customization grade memory is compiled
The memory macro unit for translating device generation is more advantageous in area and aspect of performance, but it at most only meets two ports simultaneously
Read/write, and its design is nontransparent, is a black box for the projector of rear end, due to its internal road
Diameter and unit it is invisible, larger inconvenience is brought to static timing analysis (STA).Simultaneously because the design of the memory is
Nontransparent, user can not modify to the memory.Although its design of the memory based on third party's tool design is
Bright, but its memory generated is poor in sequential, area, layout controllability etc. performance.
Memory Compilation Method provided by the invention is first right when the storage array to memory carries out stzwctlrred definition
Storage unit carries out stzwctlrred definition, according to the digit of memory, item number repeats that the stzwctlrred definition of storage unit is called to be formed
The stzwctlrred definition of storage array so that the structure of the storage array of the memory of generation is regularization, when to improve
The storage array of sequence energy, regularization makes placement-and-routing be easy to control, higher in controllable etc. the performance of area, layout.It deposits
Storage unit may be used standard gate leve cell formation or full custom structure, based on gate leve unit inner track it is transparent as it can be seen that
It modifies to memory inside circuit convenient for user and convenient for subsequent static timing analysis.
The detail flowchart of memory compiling generation method provided in an embodiment of the present invention is as shown in Fig. 2, the memory is compiled
It is based on the design cycle of entire digital integrated electronic circuit rear end to translate generation method.There are two the designs of digital integrated electronic circuit rear end
Main feature, first, standard cell design is based on, second is that static timing analysis (STA).First, modern integrated circuits, which design, is all
Design based on standard block, the chip manufacturing factory chamber of commerce provide the standard cell lib that they can manufacture to the user, include in library
The domains of various components, equal, the width etc. of domain height of these components, referred to as standard block.User can make
With special placement-and-routing's tool, these standard blocks is called to complete layout design automatically according to design requirement, to significantly
Improve design efficiency.And so-called static timing analysis (STA), it is a kind of limit analysis method, to weigh circuit performance.It
All timing paths for extracting entire circuit are found out along the delay transit on path by calculating signal and violate temporal constraint
Mistake mainly checks whether settling time and retention time meet the requirements, and they are respectively by prolonging to maximum path
It is obtained late with the analysis of minimal path delay.It is defeated first in the flow of memory Compilation Method provided in an embodiment of the present invention
Access customer requirement definition, memory construction configuration parameter and gate leve cell library.User demand defines the main shape for including memory
Shape, size, input/output port position etc..Memory construction configuration parameter mainly includes the digit of memory, item number, read port
Number, write port number, memory breadth length ratio, if write enabled etc..By taking register file storage organization as an example, table 1 is register file
Type storage organization part configures parameter definition, and wherein NDCbit is to be written or read address size, and Nbit is input, output data
Width, Nword are storage data item number, and Nwrite is write-once data item number, and Nread is once to read data item number.
Table 1
Gate leve cell library includes standard gate leve unit and full custom gate leve unit, the standard gate leve list in gate leve cell library
Member includes different threshold types, channel length, standard block timing sequence library and physical layout under process corner etc..Full custom gate leve list
Member is the unit being customized according to the needs of performance.
Secondly, stzwctlrred definition is carried out to each module for constituting memory, is stored in the present embodiment with register heap-type
The compiling of structure illustrates for generating, as shown in figure 3, the storage organization of register heap-type, includes mainly to read address to translate
Code, write address decoding, data storage array etc., each part can individually be designed.
The definition of structuring is carried out to storage unit first, storage unit is the basic storage organization in memory, and each
The storage organization of kind register heap-type is formed based on storage unit, and the basic function of storage unit is completed for 1
The store function of (0 or 1).One memory forms a storage array by multiple such bit locations.And for storing position
Unit be divided into for single port read-write and multi-port read-write, multi-port read-write functionally with circuit realize on all have larger reality
Existing difficulty.By taking two write two reading memories as an example, basic circuit structure as shown in figure 4, wherein Wen0, Wen1 be write address through translating
The write strobe signals obtained after code, similarly Ren0 and Ren1 is the read strobe signal read address and obtained after decoding.Din0 and
Din1 inputs for data-signal, and Dout0 and Dout1 export for data-signal.The internal circuit configuration of storage unit may be used
Standard gate leve cell formation in gate leve cell library can also realize that the inside of storage unit is electric according to performance requirement full custom
The types such as trigger, latch may be used to realize the further full custom optimization of storage unit in line structure so that data are deposited
The performance of storage is further promoted.
After complete to storage unit progress stzwctlrred definition, the memory in parameter is configured according to the memory construction
Digit and item number repeat to call the stzwctlrred definition of the storage unit, generate the stzwctlrred definition of storage array so that weight
Polyphony use after storage unit composition storage array have the memory construction configuration parameter in memory digit and
Item number.Since the stzwctlrred definition of storage array is the register for repeating that standard memory location is called to be formed, thus ultimately produced
The structure of the storage array of heap storage organization is regularization, and to improve timing performance, the storage array of regularization makes
Placement-and-routing is easy to control, and in area, is laid out controllable etc. performance raising.In addition standard gate leve list may be used in storage unit
Member structure or full custom structure are transparent as it can be seen that consequently facilitating user is to memory inside circuit based on gate leve unit inner track
It modifies and convenient for subsequent static timing analysis.The memory size of the register file storage organization of generation and read-write end
Mouth quantity can match, and there is high flexibility and highly compatible, port number maximum eight can be supported to write eight readings, memory capacity is up to
2048x 2048=4M bit sizes.
After carrying out stzwctlrred definition to storage array, stzwctlrred definition, decoding circuit are carried out to read-write decoding circuit
In internal circuit configuration may be used standard gate leve cell formation or full custom structure.
After carrying out stzwctlrred definition to each module for constituting register file storage organization, based on the storage array
The stzwctlrred definition of stzwctlrred definition and the read-write decoding circuit, by the stzwctlrred definition of the storage array and the read-write
Relevant parameter in the stzwctlrred definition of decoding circuit builds model using hardware description language, and then generates hardware description language
Model.The standard gate leve unit and full custom gate leve list in the gate leve cell library are called based on the hardware description language model
Member generates netlist by logic synthesis.
According to the netlist and the user demand be defined through allocation plan be laid out, generate Clock Tree, wiring with
The domain of memory is obtained, the compiling of memory is completed.Wherein, layout refers to is arranged position by the unit in gate level netlist.
Wherein placement rule refers to the variation according to memory size and port number, and placement rule is arranged in physical layout, estimation
The size of whole layout area, it is ensured that the reasonability of layout.The algorithm that user's script may be used in the mode of layout is realized automatically
Change layout, regularization automatic layout tool such as ICC can also be used and be laid out.By taking the algorithm of user's script as an example, algorithm is defined
In relevant parameter, according to actual use demand can calculate position of the storage unit in layout by controlling these parameters
It sets, to realize layout fast and automatically, compact, regular.It is then possible to control clock critical path in such a way that gate clusters
The trend of diameter generates Clock Tree.It is connected up, first power cord and clock signal is connected up when wiring, then to signal wire later
Wiring, it is therefore an objective to farthest meet sequential.
Register heap-type memory layout mode can be according to input port, output port, crucial, the factors such as gate cluster
It is adjusted, carries out the design of semidefinite inhibition and generation, the trend of the read/write path of data and delay are fully controllable after the completion of design.Root
There are many modes that it is laid out according to design requirement, and space layout form is introduced in a manner of Clock gating cluster below, ties
Structure is as shown in Figure 5.The same item of storage array is controlled using same Clock gating, through branching to each of storage unit
, the write bit gating signal and read bit gating signal of write address and reading address after decoding also gate each storage unit
Control.Gate and decoder are all located at centre position, and the path for reaching each storage unit uses cushioning control, so as to get reach
The delay balance of the storage unit of both sides.Space is more saved using Clock gating cluster mode, is conducive to the structure of Clock Tree
With the splicing of digit.In layout process, gate logic of the read/write address after decoding is reached every by buffer (buffer)
A storage unit can accurately control the size and location of Buffer insertion by algorithm to control direction of routing.
The gate level netlist formed after logic synthesis emulates after placement-and-routing using static timing analysis and SPICE
Afterwards, using DRC (Design Rule Check, design rule check), LVS (Layout vs Schematic Check, net
Table consistency check) check after export result.The wherein described output result includes Verilog models, net meter file, DEF files,
Synopsys.lib files and layout file meet file format and rear end stream that most of rear ends IC design cycle is related to
Journey.
The memory that the present invention is generated is all based on the design of gate leve standard block, and the intermediate result generated is common
Digital back-end design tool in it is compatible as it can be seen that common timing performance analysis means --- static timing in designing rear end
Analysis (STA) has preferable supportive.The output result of configurable memory compiler based on gate leve standard block has 5,
Including Verilog models, net meter file, DEF files, synopsys.lib files and layout file, after meeting most of IC
The file format and rear end eco flows that end design cycle is related to.
The memory array that the present invention is generated, generating mode is flexibly quick, it solves full custom memory volume
Translate memory that device is generated as macroelement the sightless disadvantage in the static timing analysis of rear end, while compared to third party
Memory caused by tool is advantageous in performance and area.In results of property analysis, the present invention is posted compared to logic level
Register file storage mode has larger promotion in the performance indicators such as sequential and area.Reality under certain 40nm process environments
Testing evaluation result shows the opposite register file generated based on memory compiler of the memory of compiler generation in performance
On improve 8%, save 10% on area.It is improved in the memory compiler performance provided relative to third party's technique manufacturer
30%, at the same reached the identical scale that is designed by full custom mode memory performance 70% or more.
The embodiment of the present invention also provides a kind of memory compiling generating means, and as shown in Fig. 6, described device includes：
First receiving unit 61 configures parameter for receiving user demand definition input by user and memory construction；
Second receiving unit 62, the stzwctlrred definition for receiving memory input by user, the structure of the memory
It includes the stzwctlrred definition of storage unit and the stzwctlrred definition of read/write decoding circuit to change definition；
First generation unit 63 configures the storage in parameter for being based on gate leve cell library according to the memory construction
The digit and item number of device repeat to call the stzwctlrred definition of the storage unit, generate the stzwctlrred definition of storage array；
Second generation unit 64, for according to the stzwctlrred definition of the storage array and the read/write decoding circuit
Stzwctlrred definition generates hardware description language model；
Third generation unit 65, for calling the standard in the gate leve cell library according to the hardware description language model
Gate leve unit and full custom gate leve unit generate netlist；
4th generation unit 66, for carrying out regularization layout according to the netlist and user demand definition, generating
Clock Tree, wiring are to obtain the domain of memory.
Memory provided in an embodiment of the present invention compiles generating means, first storage array, the read-write to constituting memory
Decoding carries out the definition of structuring, hardware description language module is formed according to the definition of its structuring, according to hardware description language
Module forms netlist, and then forms domain by the layout of regularization, wiring.Structuring is carried out in the storage array to memory
When definition, stzwctlrred definition first is carried out to storage unit, the structure for calling storage unit is repeated according to the digit of memory, item number
Change the stzwctlrred definition that definition forms storage array, the structure of the storage array of the memory of formation is regularization, to carry
High timing performance, the storage array of regularization make placement-and-routing be easy to control, and are carried in controllable etc. the performance of area, layout
It is high.Storage unit may be used standard gate leve cell formation or full custom structure, based on gate leve unit inner track it is transparent as it can be seen that
Consequently facilitating user modifies to memory inside circuit and convenient for subsequent static timing analysis.
Optionally, the gate leve cell library include the standard gate leve unit and full custom gate leve unit timing sequence library and
Physical layout.
Optionally, the internal circuit of the storage unit and the read/write decoding circuit passes through in the gate leve cell library
Standard gate leve cell formation, alternatively, the internal circuit of the storage unit and the read/write decoding circuit passes through the gate leve
Full custom gate leve cell formation in cell library.
Optionally, the user demand, which defines, includes：Shape, size, input port position and the output port of memory
Position.
Optionally, memory construction configuration parameter includes：The digit of memory, read port number, write port number, is deposited item number
It is enabled whether reservoir length-width ratio, memory are write.
Optionally, the storage unit is single port read-write or multi-port read-write.
The third aspect, the embodiment of the present invention also provide a kind of memory, and the memory uses memory described above
Compiling generation method is prepared.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, all answer by the change or replacement that can be readily occurred in
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (12)
1. a kind of memory Compilation Method, which is characterized in that including：
Receive user demand definition input by user and memory construction configuration parameter；
The stzwctlrred definition of memory input by user is received, the stzwctlrred definition of the memory includes the structure of storage unit
Change the stzwctlrred definition of definition and read/write decoding circuit；
Based on gate leve cell library, the digit of the memory in parameter is configured according to the memory construction and item number repeats to call institute
The stzwctlrred definition for stating storage unit generates the stzwctlrred definition of storage array；
Hardware description language is generated according to the stzwctlrred definition of the stzwctlrred definition of the storage array and the read/write decoding circuit
Say model；
The standard gate leve unit and full custom gate leve list in the gate leve cell library are called according to the hardware description language model
Member generates netlist；
Regularization layout is carried out according to the netlist and user demand definition, generates Clock Tree, wiring to obtain memory
Domain.
2. memory Compilation Method according to claim 1, which is characterized in that the gate leve cell library includes the mark
The timing sequence library and physical layout of quasi- gate leve unit and full custom gate leve unit.
3. memory Compilation Method according to claim 2, which is characterized in that the storage unit and the read/write are translated
The internal circuit of code circuit is by the standard gate leve cell formation in the gate leve cell library, alternatively, the storage unit and institute
The internal circuit for stating read/write decoding circuit passes through the full custom gate leve cell formation in the gate leve cell library.
4. memory Compilation Method according to claim 1, which is characterized in that the user demand, which defines, includes：Storage
Shape, size, input port position and the output port position of device.
5. memory Compilation Method according to claim 1, which is characterized in that memory construction configures parameter and includes：It deposits
The digit of reservoir, item number, read port number, write port number, memory length-width ratio, that whether memory is write is enabled.
6. memory Compilation Method according to claim 1, which is characterized in that the storage unit be single port read and write or
Multi-port read-write.
7. a kind of memory compilation device, which is characterized in that including：
First receiving unit configures parameter for receiving user demand definition input by user and memory construction；
Second receiving unit, the stzwctlrred definition for receiving memory input by user, the stzwctlrred definition of the memory
The stzwctlrred definition of stzwctlrred definition and read/write decoding circuit including storage unit；
First generation unit configures the position of the memory in parameter according to the memory construction for being based on gate leve cell library
Number and item number repeat to call the stzwctlrred definition of the storage unit, generate the stzwctlrred definition of storage array；
Second generation unit is used for the structuring of the stzwctlrred definition and the read/write decoding circuit according to the storage array
Definition generates hardware description language model；
Third generation unit, for calling the standard gate leve list in the gate leve cell library according to the hardware description language model
Member and full custom gate leve unit generate netlist；
4th generation unit, for according to the netlist and user demand definition carry out regularization layout, generate Clock Tree,
Wiring is to obtain the domain of memory.
8. memory compilation device according to claim 7, which is characterized in that the gate leve cell library includes the mark
The timing sequence library and physical layout of quasi- gate leve unit and full custom gate leve unit.
9. memory compilation device according to claim 8, which is characterized in that the storage unit and the read/write are translated
The internal circuit of code circuit is by the standard gate leve cell formation in the gate leve cell library, alternatively, the storage unit and institute
The internal circuit for stating read/write decoding circuit passes through the full custom gate leve cell formation in the gate leve cell library.
10. memory compilation device according to claim 7, which is characterized in that the user demand, which defines, includes：Storage
Shape, size, input port position and the output port position of device.
11. memory compilation device according to claim 7, which is characterized in that memory construction configures parameter and includes：It deposits
The digit of reservoir, item number, read port number, write port number, memory length-width ratio, that whether memory is write is enabled.
12. a kind of memory, which is characterized in that the memory is using any one of the claim 1-6 memory compilings
Method is prepared.
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