CN112001136A

CN112001136A - Software implementation method for automatically generating memory layout and netlist

Info

Publication number: CN112001136A
Application number: CN202010840904.0A
Authority: CN
Inventors: 王勇; 侯劲松; 张萍; 李宁
Original assignee: Mircoscape Technology Co ltd
Current assignee: Mircoscape Technology Co ltd
Priority date: 2020-08-20
Filing date: 2020-08-20
Publication date: 2020-11-27

Abstract

The invention relates to a software implementation method for automatically generating a layout and a netlist of a memory, which realizes a memory splicing description language MCDL, can complete memory splicing of any complex structure by using the language and finally obtains layout and netlist output. The characteristics of defining the memory splicing by MCDL are as follows: 1) the layout splicing does not need to define absolute coordinates, and the coordinates of all units are automatically calculated through topological relations between adjacent units. 2) And automatically extracting port information from the bottom layout unit to the top unit. 3) The layout ring structure is automatically generated, unit functions of non-key parts are shielded, and simulation operation amount is reduced. 4) And the netlist splicing is automatically connected with the ports with the same name.

Description

Software implementation method for automatically generating memory layout and netlist

Technical Field

The invention relates to the field of memory design in integrated circuit aided design software tools.

Background

Memory (Memory) design is a specialized area in the development of integrated circuit chips (ICs), and includes SRAM, DRAM, ROM, Register File, Flash, and the like. In order to enable the memory to be used in multiple chips, the memory is generally divided into a plurality of bottom layer cells (Leaf cells), and then the cells are spliced into a memory with a specified size according to a certain splicing rule. Its capacity and structure are generally specified by the following variables: capacity of Words (Words), number of Bits (Bits) per word, and width of multiplexer (Mux).

The Memory layout and netlist automatic generation software (Memory Compiler) is a software tool for completing the splicing of corresponding memories according to word, Bits and Mux specified by a user. The output of the result comprises a GDSII layout and a CDL netlist.

The invention realizes a Memory splicing Description Language (MCDL), which is called MCDL for short, and can be used for completing the Memory splicing of any complex structure to finally obtain the layout and netlist output.

Disclosure of Invention

FIG. 1 is a flow diagram of a process for memory compilation using the present invention. The program first reads in the concatenation definition described by the MCDL statement and loads leaf element information from the specified standard GDS/CDL format file. Then, the program completes the memory splicing according to the leaf unit information and the splicing rule defined by MCDL according to the capacity size (Word, Bits) and the structure (Mux) parameters specified by the user. The GDS and CDL files of the memory are finally output.

MCDL is based on TCL language, provides basic syntax structure support such as variable access, expression calculation, and control structure (if, while, for), and provides the following extended commands for memory splicing:

1) MCDL _ Place < cell >: < rotate > < side >: and splicing the layout cell to the current cell. The placement of a layout cell is determined by two parameters, coordinates (x, y) and rotation direction rotate. There are 8 kinds of rotation directions, be R0 (irrotational), R90 (anticlockwise rotation 90 degrees), R180 (rotation 180 degrees), R270 (rotation 270 degrees), MX (along Y axle mirror image), MXR90 (follow Y axle mirror image earlier and rotate 90 degrees again), MY (follow X axle mirror image), MYR90 (follow X axle mirror image earlier and rotate 90 degrees again), the coordinate needs adjust according to the rotation direction. The MCDL _ Place command is characterized in that the coordinates are not required to be considered in the unit placement, but only in the upper, lower, left or right (side) of the existing graph, and the program automatically calculates the coordinates and keeps the coordinates of the lower left corner of the current unit to be (0, 0) all the time.

3) MCDL _ MapBorderLabel < pattern > < pin-list >: and extracting the Label of the bottom unit of the layout, and mapping the Label to be an external port. The ordinary memory compiler only provides a layer of Label mapping, and finally forms an external port to be subjected to multilayer Label mapping, while the MCDL command is characterized in that the external port definition can be completed only by one-time mapping. The command first looks up the Label in the Leaf unit according to the pattern, which is a regular expression, e.g., D × matches D <0>, D <1>, D <2>. D [0-3] matches D0, D1, D2, D3. The labels conforming to the pattern are extracted and arranged in the order of coordinates from small to large, so that the labels at the bottom and top of the memory are arranged from left to right, and the labels at the left and right of the memory are arranged from bottom to top. The arranged Label and the pin-list correspond to each other one by one in sequence, and the external ports are generated at the same position. For example, the Label extraction results a0, a1, a0, a1, a2, and a < 3: 4>, A < 0: 2>, then external port a <3> is generated at the first a0, external port a <4> is generated at the first a1, external port a <0> is generated at the second a0, external port a <1> is generated at the second a1, and external port a <2> is generated at a 2.

4) MCDL _ Donut bitcell-row. -. col.: and generating a donut circle ring of the layout. The word bit unit of the memory is called bitcell, and the main part of the memory except for the control decoding circuit is a bit array formed by splicing bitcells. For a large memory, the process of extracting its timing characteristics through simulation can be time consuming. Because the time sequence characteristics are only related to the outer ring bitcell of the bit array, the middle part of the bit array is hollowed in a simulation used layout, namely the Mos tube in the middle part is removed, and only the connecting line is reserved. The MCDL _ Donut command is designed to handle this situation, and only one command is needed to form a Donut circle of the layout. Row/col in the command controls which cells to reserve and empty, e.g., -row 151 denotes row 1 and row 7 out of 7 rows to reserve, and 5 in the middle to empty; col 171 denotes the 1 st and 9 th of the 9 remaining columns, hollowing out the middle 7 columns; the two are combined to show that the outer circle in the array is reserved, and the bitcell in the middle is hollowed out.

5) MCDL _ Connect < cell > -pin > net.: and splicing the netlist cell. Port connections are specified by-pin pin ═ net, e.g., -pin DIN < 0: 3> d0 d1 d2 d3, which means that port DIN <0> is connected to net d0, port DIN <1> is connected to net d1, port DIN <2> is connected to net d2, and port DIN <3> is connected to net d 3. The command is characterized in that if the port name is the same as the net name, the unwritten can be ignored. In a memory system, most of the line net names and port names are the same, such as CLK, WEB, etc., so this feature greatly simplifies the splice definition.

6) MCDL _ DefPin < pin >: ports of the netlist cells are defined.

7) MCDL _ LoadLeafCell < gds >/< cdl >: and loading the designated Lead unit layout or netlist. The layout units are stored in a GDS format, and each unit comprises unit name, unit size, contained graph, Label and other information. Netlist cells are stored in CDL format, with each cell including information such as cell name, port list, etc.

Drawings

FIG. 1: memory compiler flow diagram.

FIG. 2: MCDL _ Place command example. The graph corresponds to the command:

MCDL_Place A：R0

MCDL_Place B：MX Right

MCDL_Place C：MY Bottom

firstly, the unit A is placed, no rotation operation is performed, and after the operation, the current unit only comprises the unit A and coordinates (0, 0) at the lower left corner. And then placing a unit B on the right side of the unit A, rotating the unit B according to the Y axis before placing, checking the height of the unit B is consistent with that of the unit A by a program, checking that the current unit comprises the unit A and the unit B after operation, wherein the height is consistent with that of the unit A, the width is the width of the unit A plus the unit B, and the lower left corner coordinates (0, 0). And then placing a unit C below the current unit, rotating the unit C according to the X axis before placing, checking the width of the unit C is consistent with that of the current unit by a program, and after operation, the current unit comprises a unit A, a unit B and a unit C, wherein the height is equal to the height of the unit A plus the height of the unit B, the width is equal to the width of the unit A plus the width of the unit B, and the lower left corner coordinate is still (0, 0).

After GDS is output, cell A coordinates (0, H)_C) (coordinate 1 in the figure), direction of rotation R0; unit B coordinate (W)_A+W_B，H_C) (coordinate 2 in the figure) the direction of rotation MX; cell C coordinate (0, 0) (coordinate 1 in the figure), rotation direction MY. Wherein H_CRepresents the height of the unit C, W_AAnd W_BRepresenting the width of cells a and B, respectively.

FIG. 3: example of the MCDL _ mapbedderlabel command. The graph corresponds to the command:

MCDL_MapBorderLabel DI D<0：6>

MCDL_MapBorderLabel DO Q<0：6>

MCDL_MapBorderLabel A*A<6：7>，A<3：5>，A<0：2>

the lower part of the memory is shown in the figure, and the memory consists of 4 RD units, one YDECH unit, one YDECL unit, 1 XDEC unit and 3 RD units from left to right, wherein each RD unit leads out one DI and one DO and has two data signals, the YDECH unit leads out two address signals A0 and A1, the YDECL unit leads out three address signals A0-A2, and the XDECL unit leads out three address signals A0-A2.

Command extraction of DI as 6 data input signals D < 0: 6>, 0-6 are arranged from left to right; extract DO as 6 data output signals Q < 0: 6>, 0-6 are arranged from left to right; extracting a as 8 address signals, since the address signals are not monotonically increasing from left to right, the order of arrangement a6, a7, A3, a4, a5, a0, a1, a2 is to be specified in the command.

FIG. 4: MCDL _ Donut command example. The graph corresponds to the command:

MCDL_MakeDonutCell CELL6T poly diff nsdm psdm

MCDL_Donut CELL6T-row‘1 161’-col‘1 16 1’

the memory CELL array is CELL6T, which is 18 × 15 memory CELL array, and there is a row of strap CELLs in every 5 CELLs in the array direction of the CELL array, and they are not counted in the CELL array. The first command first generates a donut CELL for CELL6T that removes all the graphics in the poly, diff, nsdm, and psdm layers (i.e., removes the Mos tube), and the other metal layer graphics are preserved (i.e., preserves the links). The second command generates a circular loop, all CELL6T in the middle are replaced by donut CELLs, but the CELL6T CELLs in the first row (bottom), last row (top), first column (left), and last column (right) are preserved.

FIG. 5: MCDL _ Connect command example. The graph corresponds to the command:

MCDL_DefPin D<0：6>，Q<0：6>，A<0：4>，CLK，WEB，OEB

MCDL_Connect XDEC-pin A＝＞A<0：1>

MCDL_Connect YDEC-pin A＝＞A<2：4>

MCDL_Connect WINGL-pin D＝＞D<0：3>-pin Q＝＞Q<0：3>

MCDL_Connect WINGR-pin D＝＞D<4：6>-pin Q＝＞Q<0：3>

DefPin defines the external port: data input D < 0: 6>, data output Q < 0: 6>, address signal a < 0: 4>, control signals CLK, WEB, and OEB. The Connect signal connects 4 units XDEC, YDEC, WINGL, and WINGR. The 3 control signals are identical and therefore are not described in the splice definition. The BL, WL signal definition between WING and DEC is also the same and may be omitted in the concatenation. The address line is divided into two parts, A < 0: 1> and A < 2: 4>, respectively sending the signals to an X decoder XDEC and a Y decoder YDEC; the data line is also divided into two parts, D/Q < 0: 3> and D/Q < 4: 6> are respectively sent into the left array WINGL and the right array WINGR. The connection of the address lines and the data lines needs to be described in the Connect command.

The specific implementation mode is as follows:

the automatic generation software of the memory layout and the netlist is realized by a Tcl language, and a C + + realized function library is provided for each MCDL extended command. The software implementation process is as follows:

in the first step, a user writes an MCDL file of a piece of memory, specifies a GDS/CDL file of a Leaf unit in the MCDL file, splices the memory by using MCDL _ Place and MCDL _ Connect, and presents and uses parameters related to the capacity size and structure of the memory, such as Word, Bits, Mux and the like in a variable form.

In the second step, the user specifies the size of the specific memory to be generated and the values of the configuration parameters, for example, Word 512, Bits 8, and Mux 4, i.e., 512 words are generated, each Word has 8 Bits, and the memory has 4K Bits and uses 4-way multiplexers, i.e., 512/4 128 rows of Word lines and 8x 4 columns of bit lines. For each version of the MCDL described memory, a variety of specific memories of specified size and structure within the effective range can be generated.

And thirdly, automatically generating software of the memory layout and the netlist according to the MCDL and the parameters to splice and generate a memory with a specified size and structure, outputting the result layout as a GDS format file, and outputting the result netlist as a CDL format file.

Claims

1. A syntax of Memory mosaic Description Language (Memory Compiler Description Language) abbreviated as mcdl is defined, a software tool can generate a layout and a netlist of any complex structure through the syntax according to requirements, and the syntax is characterized in that:

1.1. absolute coordinates do not need to be defined in the layout of the units, and the coordinates of all the units are automatically calculated through topological relations between adjacent units;

1.2. the port information of the bottom unit in the layout can be automatically extracted to the top unit and automatically named to be used as an external interface of the memory;

1.3, in order to improve the simulation efficiency, a layout automatically generates a unit of a circular ring, the unit function of a non-key part is shielded, and the operation amount is reduced;

and 1.4, automatically connecting ports with the same name in netlist splicing, and simplifying netlist definition.