CN102129483A

CN102129483A - Method for automatically generating test vector of design rule checking (DRC) rule file

Info

Publication number: CN102129483A
Application number: CN2010100313883A
Authority: CN
Inventors: 侯劲松; 张萍
Original assignee: MIRCOSCAPE TECHNOLOGY Co Ltd
Current assignee: MIRCOSCAPE TECHNOLOGY Co Ltd
Priority date: 2010-01-20
Filing date: 2010-01-20
Publication date: 2011-07-20

Abstract

The invention discloses a method for automatically generating the test vector of a design rule checking (DRC) rule file, wherein the method provided by the invention is an optimization method in the DRC in an integrated circuit aided design software tool. The method belongs to the field of DRC in integrated circuit aided design software tools. In order to guarantee the accuracy of a DRC rule file, the general method is as follows: according to the description of the rule file, a plurality of test vectors are constructed artificially; and whether the calculation result of the test vectors is consistent with anticipation or not is analyzed. The method for artificially constructing test examples has the following two obvious defects: firstly, the method is large in workload and low in efficiency; and secondly, the artificially-constructed vector examples have less possibility of guaranteeing the comprehensiveness of the test. In order to overcome the defects of the method for artificially constructing the test examples, the invention provides a method for automatically generating the test vector. The method is characterized in that a computer program automatically generates the test vectors capable of being comprehensively covered. The test vectors can be generated within short time, thereby greatly improving the developing efficiency, and guaranteeing the accuracy of the rule file.

Description

The automatic generation method of layout verification rule file test vector

Technical field

The automatic generation method of layout verification rule file test vector is a kind of optimization method in the layout verification (DRC) in the integrated circuit Autocad instrument.The invention belongs to layout verification field in the integrated circuit Autocad instrument.

Background technology

The later stage of integrated circuit (IC) design comprises layout design and layout verification, and these two functions are the important steps in the eda tool; Layout verification is according to the logical relation of layout design rules, electricity rule and original input layout design to be carried out accuracy verification and can be by to circuit and Parameter Extraction, the input file that produces breadboardin carries out the back simulation, with further inspection electric property.

The layout verification rule file is to be used for verifying whether layout design meets the vital document of processes constraint condition, and the correctness direct relation of this file the chip manufacture success or failure.In order to verify the correctness of this rule file, method in common is: according to the description of rule file, by a plurality of test vectors of manual construction, whether the result of calculation of analytical test vector is consistent with expection then.What test vector referred to here generally is one group of domain figure, is used for reflecting the test case of whether violating design rule.

The method of manual construction test case has two remarkable shortcomings, and at first, along with the continuous development of technology, the number of design rule sharply expands, and the method workload of manual construction test vector is very big, and efficient is very low.According to statistics, after integrated circuit technology enters nano-scale, the design rule number of one cover technology is often above 1000, suppose that each design rule need construct the test vector more than 6, each test vector structure need be spent 3 minutes, the test vector structure that amounts to set of rule needs cost 18000 minutes, and promptly 300 hours, this time can have a strong impact on development efficiency.What secondly, manual construction vector use-case was difficult to guarantee to test is comprehensive.Because the people has little carelessness and mistake unavoidably in structure use-case process, can cause final design rule file to imply some mistake, finally causes the chip manufacture failure.

In order to overcome the defective of manual construction test vector, the present invention proposes a kind of automatic generation method of test vector, this method is generated automatically by computer program and covers comprehensive test vector, can finish the generation of test vector in a short period of time, improve development efficiency greatly, guaranteed the correctness of rule file.

Summary of the invention

The present invention proposes the automatic generation method of layout verification rule file test vector, main contents are as follows:

1. at the original process supporting paper of layout verification, construct a kind of formal descriptive language, natural language is converted into the understandable descriptive language of computing machine;

For example, the natural language of a typical metal width description is:

Min.Width?of?ME1?is?0.6

In order to make above-mentioned natural language be accepted by computer program, the present invention proposes a kind of formal language and describe above-mentioned rule, formalized description is as follows:

RuleBegin

RuleName METAL1_hla

LayerNum 1

Layer1No 6

Keyword Width

MaxValue 0.6

MinValue 0

RuleEnd

In the above-mentioned formalized description, RuleName is this regular name, and LayerNum is the total number of this regular input layer, Layer1No is the level number of data, Keyword is the key word that rule is checked, MaxValue is this regular maximal value, and MinValue is this regular minimum value.

2. the formal description language that generates at previous step by the method for automatic structure, is generated the script of corresponding test vector automatically by computer program.

Still the example with previous step is an example, and at formal description language, program will generate a collection of figure that meets design rule automatically, and this batch figure is described in the mode of script, directly perceived more and understanding easily.Theing contents are as follows of script:

GDSfileName good_METAL1_hla.gds

DBunit 1000

CellBegin

CellName good_METAL1_hla

createText 6?0?10000?1000?width_should_not?be_less_than_0.6

createBox 6?0?0?10000?600

createBox 6?0?5000?10000?5620

CellEnd

Above-mentioned script has been described at the automatic one group of test vector figure that generates of the design rule of the first step, wherein gdsFileName is a test vector file name of preparing output, Dbunit is the unit of database, CellName is the test vector cell name of output, createText is the note of the test vector of Automatic Program generation, createBox is 2 test vector figures that Automatic Program generates, and the width of this figure just satisfies 0.6 size of he design rules specify.

Above-mentioned example has only provided the test vector figure that satisfies design rule, and actual program also needs automatic generation not satisfy the test vector figure of design rule in realizing, method is consistent with foregoing description, repeats no more.

3. the script that generates at previous step by the method for automatic translation, is generated the standard gds formatted file of test vector by computer program.

The script that previous step generates automatically is more directly perceived, understands easily, but also is not the Final Format descriptive language of test vector figure.In order to make test vector to be read in by different Software tools, must be converted into the general formatted file of industry member to the script of test vector, this formatted file generally is the form of gds2.

The present invention adopts automatic converting method, by computer program script is changed, and generates the gds2 form of standard.And can show intuitively in the layout editing instrument that the domain directly perceived of this use-case shows sees accompanying drawing 1.

In addition, Fig. 2 and Fig. 3 further illustrate the spacing inspection and generate the result automatically with the test vector that comprises inspection.

Description of drawings

The test vector of Fig. 1 width inspection generates figure as a result automatically

The test vector of Fig. 2 spacing inspection generates figure as a result automatically

The test vector that Fig. 3 comprises inspection generates figure as a result automatically

Embodiment:

The first step:, write the formal description language of layout verification rule file according to the natural language description of technical papers.

Second step: call automated tool FormalGen, generate the script of test vector by the formalization language automatically.

The 3rd step: call automated tool ScriptGen, generate the standard gds2 file of test vector by script automatically.

Adopt above-mentioned steps, at the authenticating documents of typical 1000 rules, the written form file only spends 3 hours, and operation FormalGen instrument only needs 1 minute, operation ScriptGen instrument only needs 20 seconds, is far smaller than manual 300 hours the time that generates test vector.

Claims

1. the automatic generation method of layout verification rule file test vector, its basic meaning be the layout verification rule write finish after, need a large amount of test vector of structure to verify whether this document is accurate, existing method is to rely on manual construction fully, and workload is big and can't cover comprehensive; In order to improve the development efficiency of test vector, the present invention proposes the method that a kind of test vector generates automatically.

Concrete steps are as follows:

(1) at the original process supporting paper of layout verification, construct a kind of formal descriptive language, natural language is converted into the understandable descriptive language of computing machine:

(2) formal description language that generates at (1) by the method for automatic structure, is generated the script of corresponding test vector automatically by computer program.

(3) script that generates at (2) by the method for automatic translation, is generated the standard gds formatted file of test vector by computer program.