US20090290444A1

US20090290444A1 - Semiconductor device

Info

Publication number: US20090290444A1
Application number: US12/094,768
Authority: US
Inventors: Masayuki Satoh
Original assignee: Individual
Current assignee: Taiyo Yuden Co Ltd
Priority date: 2005-11-28
Filing date: 2005-11-28
Publication date: 2009-11-26
Also published as: US7652946B2; WO2007060738A1; CN101310442A; JP4703655B2; TW200721190A; CN101310443A; JPWO2007060738A1; WO2007060763A1; US20090154282A1; TWI367494B; CN101310443B

Abstract

A semiconductor device includes a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data. Each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit. The number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to three or more other memory cell blocks.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a semiconductor device capable of operating a memory as a logic circuit.
2. Description of the Related Art
Existing semiconductor devices, such as a large scale integrations (LSIs), are manufactured through a plurality of steps including a functional design step, a logic circuit design step, a wafer production step, and an assembly step. These manufacturing steps are suitable for mass production for manufacturing a large number of products of the same type. However, the manufacturing steps are not suitable for high-mix low-volume production, since the steps are costly.
Accordingly, a technology suitable for high-mix low-volume production has been developed. An example of such a technology is a field programmable gate array (FPGA). An FPGA is a semiconductor device (e.g., an LSI) that allows a user to program a logic circuit after being manufactured.
However, since an FPGA includes a plurality of components (e.g., a logic circuit, interconnection lines, and switches), a multilayer interconnection structure including a plurality of interconnection layers and a highly advanced manufacturing technique are disadvantageously required for a semiconductor process.
To solve such a problem, Japanese Unexamined Patent Application Publication No. 2003-224468 describes a semiconductor device that functions as a logic circuit after a truth table is written to a memory, such as a static random access memory (SRAM). When an address is input to the semiconductor device, the semiconductor device outputs the content of the memory.
However, in the semiconductor device described in Japanese Unexamined Patent Application Publication No. 2003-224468, memory cell blocks each including a plurality of memory cells each storing a predetermined amount of data are arranged in an array. Data output from one of the memory cell blocks is output to only two of the neighboring four memory cell blocks (for example, only the right block in the horizontal direction and the lower block in the vertical direction). Accordingly, it is difficult to operate as a logic circuit that requires return of data (i.e., feedback of data to the memory cell from which data was output). In addition, the optimization of the scale of the memory cell block (e.g., the number of inputs and the number of outputs) is not described.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a semiconductor device for serving as a memory capable of functioning as a logic circuit, facilitating feedback of data, and having an optimum scale of a memory cell block.
According to an embodiment of the present invention, a semiconductor device includes a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data. Each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit. The number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to other three or more memory cell blocks.
In a semiconductor device according to the present invention, a memory that functions as a logic circuit can easily perform data feedback, and the scale of a memory cell block can be optimized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a semiconductor device and an information processing apparatus according to an embodiment of the present invention;

FIG. 2 is an exemplary configuration diagram of a memory cell which is a storage element of the semiconductor device shown in FIG. 1;

FIG. 3 is an exemplary configuration diagram of a memory cell block;

FIG. 4 is a connection diagram of readout ports of the semiconductor device;

FIG. 5 is an exemplary internal configuration diagram of the semiconductor device;

FIG. 6 is an example configuration diagram of a 3-bit adder;

FIG. 7A is a schematic illustration of the memory cell block, and FIG. 7B is a truth table stored in a first memory cell block group;

FIG. 8A is a schematic illustration of the memory cell block, and FIG. 8B is a truth table stored in a second memory cell block group;

FIG. 9A is a schematic illustration of the memory cell block, and FIG. 9B is a truth table stored in a third memory cell block group;

FIG. 10 is an exemplary connection diagram of readout ports of a semiconductor device;

FIG. 11 is an exemplary internal configuration diagram of the semiconductor device; and

FIG. 12 is a flow chart of an exemplary process performed when bit data is loaded in the semiconductor device that functions as a logic circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device according to an embodiment of the present invention is described below with reference to the accompanying drawings.
FIG. 1 is a block diagram of a semiconductor device and an information processing apparatus according to the present embodiment. An information processing apparatus 100 is a computer apparatus. The information processing apparatus 100 includes an input unit 101 (e.g., a keyboard), a storage unit 102 (e.g., a hard disk), a memory 103 (e.g., a random access memory (RAM)), an output unit 104 (e.g., a cathode ray tube (CRT)), a communication unit 105 serving as communication equipment, and a processing unit 106 (e.g., a central processing unit (CPU)).
Note that bit data generated by the information processing apparatus 100 (refer to step S1104 shown in FIG. 12 described below) may be stored in a read only memory (ROM) (not shown).
A semiconductor device 110 is connected to the communication unit 105 of the information processing apparatus 100. In terms of hardware, the semiconductor device 110 is a storage device similar to a widely used SRAM. The semiconductor device 110 is described in more detail below with reference to FIG. 2 and the subsequent drawings.
FIG. 2 is a configuration diagram of a memory cell which is a storage element of the semiconductor device 110 shown in FIG. 1. A memory cell 200 includes read word lines 201 and 202, a write word line 211, read data lines 221 and 222, write data lines 231 and 232, gates 241, 242, 251, 252, 261, and 262, and a flip-flop 271.
In this embodiment, the gates 241, 242, 251, 252, 261, and 262 are of a negative-metal oxide semiconductor (N-MOS) type. However, these gates may be of a positive-metal oxide semiconductor (P-MOS) type. Furthermore, these gates may be of a complex gate type including an N-MOS type and a P-MOS type. In such a case, peripheral circuits can be appropriately changed as needed.
The read word lines 201 and 202 are interconnection lines to which a voltage is applied when data is read out from the memory cell 200. When a voltage is applied to the read word line 201, the gates 241 and 242 are open. When a voltage is applied to the read word line 202, the gates 251 and 252 are open.
The write word line 211 is an interconnection line to which a voltage is applied when data is written to the memory cell 200. When a voltage is applied to the write word line 211, the gates 261 and 262 are open.
The read word lines 221 and 222 are interconnection lines used for reading out data stored in the flip-flop 271 when a predetermined voltage is applied to the read word lines 201 and 202 so that the gates 241, 242, 251, and 252 are open. When data 11011 is read out from the read word line 221, data “1” is read out from the read word line 222. In contrast, when data “1” is read out from the read word line 221, data “0” is read out from the read word line 222. In this way, the read word lines 221 and 222 operate as a differential signal system.
The write data lines 231 and 232 are interconnection lines used for writing data to the flip-flop 271 when a voltage is applied to the write word line 211 so that the gates 261 and 262 are open. When data “0” is written from the write data line 231, data “1” is written from the write data line 232. In contrast, when data “1” is written from the write data line 231, data “0” is written from the write data line 232.
The flip-flop 271 holds binary data (“0”, or “1”) stored in the memory cell 200 in the above-described manner.
FIG. 3 is a configuration diagram of a memory cell block in an internal structure of the semiconductor device 110 shown in FIG. 1 (see FIG. 2 if necessary).
A memory cell block 300 includes a plurality of the memory cells 200 arranged in an array and connected to each other and read address decoders 311 and 312. As described above, by disposing the read address decoders 311 and 312 of the read word lines 201 and 202 on the left and right sides of the memory cell block 300, the memory cell block 300 can have the following interconnection function.
In the memory cell block 300, the read word lines 221 and 222 are connected to another memory cell block 300 (not shown) at positions located above the uppermost and outer memory cells 200, that is, the memory cell 200 (Cell31, 0) and the memory cell 200 (Cell31, 3). In addition, the read word lines 221 and 222 are connected to another memory cell block 300 (not shown) at positions below the lowermost and inner memory cells 200, that is, the memory cell 200 (Cell0, 1) and the memory cell 200 (Cell0, 2).
Furthermore, in the memory cell block 300, the read word lines 221 and 222 are disconnected at positions located above the uppermost and inner memory cells 200, that is, the memory cell 200 (Cell31, 1) and the memory cell 200 (Cell31, 2). In addition, the read word lines 221 and 222 are disconnected at positions located below the lowermost and outer memory cells 200, that is, the memory cell 200 (Cell0, 0) and the memory cell 200 (Cell0, 3).
That is, in the memory cell block 300, pairs of the outer read data interconnection lines are connected upwardly while pairs of the inner read data interconnection lines are connected downwardly. In this way, the scale of the output (readout) of the memory cell block 300 can be minimized, and therefore, the load of a variety of data processing can be reduced. In addition, a plurality of data items can be output in a plurality of directions.
In the memory cell block 300, the read address decoder 311 is disposed on the left side so as to receive a plurality of address differential signals from address input lines 322. In addition, in the memory cell block 300, the read address decoder 312 is disposed on the right side so as to receive a plurality of address differential signals from address input lines 323.
Note that the number of inputs or outputs “three” or “four” described in the appended claims correspond to three pairs or four pairs of differential signals.
In the memory cell block 300, any one of the plurality of read word lines 331 to 362 (each corresponding to the read word line 202 shown in FIG. 2) can be selected on the basis of the inputs from the address input lines 322, the address input lines 323, and a select line 301 (an address selection line that selects a particular address). Thereafter, a voltage can be applied to the selected read word line.
Furthermore, the select line 301 includes an inverter 302. The read address decoder 311 includes a plurality of logic circuits 370 (e.g., AND circuits). A write word line 371 (corresponding to the write word line 211 shown in FIG. 2) is connected to a write address decoder 411 (see FIG. 5).
Since logic circuits of the read address decoder 312 are similar to those of the read address decoder 311, the descriptions thereof are not repeated (for example, a logic circuit 380 is connected to a read word line 381).
As shown in FIG. 3, for example, when data “1” is input from the select line 301, the upper half of the memory cell 200 in the memory cell block 300 operates. In contrast, when data “0” is input from the select line 301, the lower half of the memory cell 200 in the memory cell block 300 operates.
Accordingly, for example, if the upper half of the memory cell 200 in the memory cell block 300 serves as an adder and the lower half of the memory cell 200 serves as a subtractor, switching between the adder and the subtractor can be conducted instantaneously by simply switching a signal from the select line 301. Similarly, for example, switching between the adder and an original storage device can be conducted.
The memory cell block 300 has been described in detail. As described above, by arranging the memory cells 200 into a 32×4 array and decreasing the lengths of the read word lines 221 and 222 (see FIG. 2), the need for a sense amplifier can be eliminated. Therefore, the circuits can be simplified.
FIG. 4 is a connection diagram of readout ports (pairs of upper and lower outputs of the read data line shown in FIG. 3 and pairs of inputs from the address input lines 322 and 323) of the semiconductor device 110 shown in FIG. 1. In FIG. 4, only an upper left portion of the semiconductor device 110 is illustrated when viewed in plan.
In each of memory cell blocks 300 d to 300 l, an input A0 (for simplicity, hereinafter simply referred to as “A0”, and the same for “A1” to “A3”) represents a combination of A0 and /A0 shown in FIG. 3. The same applies to A1 to A3.
In addition, in each of the memory cell blocks 300 d to 300 l, an output D0 (for simplicity, hereinafter simply referred to as “D0”, and the same for “D1” to “D3”) represents a combination of two read data lines of the memory cell 200 (Cell31, 0) shown in FIG. 3. The same applies to D1 to D3.
A0 to A3 and D0 to D3 of the memory cell blocks 300 d to 300 l are connected as shown in FIG. 4.
A driver circuit 420 converts a signal input from an external apparatus to this device (the semiconductor device 110) into a differential signal. In addition, an amplifier 430 amplifies the input differential signal, and converts the differential signal to a normal signal. The amplifier 430 then outputs the normal signal to the external apparatus.
By making interconnection in such a manner, the semiconductor device 110 can easily achieve feedback of data. More specifically, for example, when data is transmitted from D3 of the memory cell block 300 d to A1 of the memory cell block 300 g, a truth table indicating that data input from A1 is output from D1 is written to the memory cell block 300 g. In this way, the data can be fed back to A3 of the memory cell block 300 d.
In addition, by simply changing truth tables written to the memory cell blocks 300 d to 300 l, the semiconductor device 110 can function as a variety of logic circuit without changing the interconnection lines.
Note that the number of turns and the shapes of the turns of the interconnection lines are not limited to those shown in FIG. 4, and can be changed as needed.
FIG. 5 is an internal configuration diagram of the semiconductor device 110 shown in FIG. 1. The memory cell blocks 300 are arranged in an array. The write address decoder 411 is disposed on the left side. A write/read circuit 401 is disposed on the lower side. The write address decoder 411 and the write/read circuit 401 are connected as shown in the drawing. That is, FIG. 5 is a diagram illustrating a state other than connection of the readout ports in the semiconductor device 110 similar to that shown in FIG. 4.
The write address decoder 411 identifies an x address of the memory cell block 300 (an address in the vertical direction of the semiconductor device 110 shown in FIG. 5) when writing data into the memory cell block 300. An x address for identifying a particular memory cell block 300 from among the plurality of memory cell blocks 300 is input to a high address (in this example, A4 w, A5 w, A6 w . . . ). An x address for identifying an internal location (one of the memory cells 200) of the identified memory cell block 300 is input to a low address (in this example, A0 w to A3 w).
The write/read circuit 401 identifies a y address of the memory cell block 300 from and to which data is to be read and written. The write/read circuit 401 then reads and writes data from and to the identified memory cell block 300.
More specifically, a y address (an address in the horizontal direction of the semiconductor device 110 shown in FIG. 5; Ayw2 in this example) for identifying one of the memory cell blocks 300 is input to the write/read circuit 401. A y address for identifying an internal location (one of the memory cells 200) of the identified memory cell block 300 is then input (in this example, Ayw0 and Ayw1). In addition, data of a plurality of bits (four bits in this example) are input from input 402 to the write/read circuit 401.
In this way, a particular memory cell 200 in a particular memory cell block 300 can be selected, and the truth table data can be updated.
That is, when truth table data stored in the memory cells 200 of one of the memory cell blocks 300 is updated, the semiconductor device 110 can change the operation thereof in accordance with the updated truth table data.
The case where the semiconductor device 110 shown in FIG. 4 is used for a 3-bit adder is described next with reference to FIGS. 6 to 9B.
FIG. 6 is a configuration diagram of a 3-bit adder. In FIG. 6, connection between memory cell blocks is similar to that shown in FIG. 4.
The following description is made with reference to the case where two 3-bit values E and F are added, and the sum Y is output. “E0” represents the least significant bit of E. “E1” represents the next bit. “E2” represents the most significant bit of E. In addition, “F0” represents the least significant bit of F. “F1” represents the next bit. “F2” represents the most significant bit of F. Furthermore, “Y0” represents the least significant bit of Y. “Y1” represents the next bit. “Y2” represents the most significant bit of Y. “C0” represents a carry from the least significant bit as a result of addition. “C1” represents a carry from the next bit as a result of addition. “C2” represents a carry from the most significant bit as a result of addition. Although each signal is a differential signal, the notation is abbreviated for simplicity.
In the memory cell block 300 d, E0 is input to A0, and F0 is input to A1. Subsequently, addition is performed. As a result of the addition, Y0 is output from D3. C0 is output from D2. In the memory cell block 300 e, E1 is input to A0, and F1 is input to A1. C0 is input to A3. Subsequently, addition is performed. As a result of the addition, Y1 is output from D3. C1 is output from D2. In the memory cell block 300 f, E2 is input to A0, and F2 is input to A1. C1 is input to A3. Subsequently, addition is performed. As a result of the addition, Y2 is output from D3. C2 is output from D2.
Y0 output from D3 of the memory cell block 300 d is output from D3 of the memory cell block 300 j through a route shown in the drawing. Y1 output from D3 of the memory cell block 300 e is output from D3 of the memory cell block 300 k through a route shown in the drawing. Y2 output from D3 of the memory cell block 300 f is output from D3 of the memory cell block 300 l through a route shown in the drawing. In this way, as a result of the addition, Y0, Y1, and Y2 can be obtained.
FIG. 7A is a schematic illustration of the memory cell block 300. FIG. 7B illustrates a truth table stored in each of the memory cell blocks 300 d, 300 e, and 300 f (see FIG. 6 if necessary).
As shown in FIG. 7A, in the memory cell block 300, when inputs are fed to A0 to A3, values defined in the truth table are output from D0 to D3 in accordance with the inputs.
As shown in FIG. 7B, when E (E0 to E2), F (F0 to F2), and C_in(C0 to C2) are input to A0, A1, and A3, the three values are summed. The resultant bit value Y (Y0 to Y2) is output from D3. A carry C_out(C0 to C2) is output from D2.
Note that since D0 and D1 are not used in this example, “0” is output from D0 and D1 at all times. In addition, the first to fourth rows, fifth to eighth rows, ninth to twelfth rows, and thirteenth to sixteenth rows have the same pattern of truth values except for the values of A2. This is because correct outputs can be obtained even when either of “0” or “1” is input to A2.
FIG. 8A is a schematic illustration of the memory cell block 300. FIG. 8B illustrates a truth table stored in each of the memory cell blocks 300 g, 300 j, 300 k, and 300 l (see FIG. 6 if necessary).
As shown in FIG. 8A, in the memory cell block 300, when inputs are fed to A0 to A3, values defined in the truth table are output from D0 to D3 in accordance with the inputs.
As shown in FIG. 8B, when Y (Y0 to Y2) is input to A1, that value is directly output from D3. Note that since D0 and D2 are not used in this example, “0” is output from D0 and D2 at all times.
In practice, a truth table having only two types (two rows) of patterns from A1 to D3 (i.e., patterns of “0” to “0” and “1” to “1”) is required. However, in order to obtain correct output results even when either value of “0” or “1” is input to A0, A2, and A3, a truth table of sixteen rows is used.
FIG. 9A is a schematic illustration of the memory cell block 300. FIG. 9B illustrates a truth table stored in each of the memory cell blocks 300 h and 300 i (see FIG. 6 if necessary). As shown in FIG. 9A, in the memory cell block 300, when inputs are fed to A0 to A3, values defined in the truth table are output from D0 to D3 in accordance with the inputs.
As shown in FIG. 9B, when C (C0 to C2) is input to A0, that value is directly output from D1. In addition, when Y (Y0 to Y2) is input to A1, that value is directly output from D3. Note that since D0 and D2 are not used in this example, “0” is output from D0 and D2 at all times. In addition, as in the case of FIG. 5B, even when either value of “0” or “1” is input to A2 and A3, a correct resultant output value can be obtained.
FIG. 10 is a connection diagram of the readout ports of a semiconductor device 110 a which is a modification of the semiconductor device 110 shown in FIG. 4. In the semiconductor device 110 a, memory cell blocks 300 m to 300 o are disposed in the leftmost column. Memory cell blocks 300 s to 300 u are disposed in a third column from the left. Memory cell blocks 300 p to 300 r disposed in a column between the two columns are positionally shifted by half a memory cell block in the vertical direction. In addition, A0 to A3 and D0 to D3 of each of these memory cell blocks are connected as shown in the drawing.
As described above, by disposing some of the memory cell blocks while shifting the memory cell blocks, the length of the interconnection line from one of D0 to D3 of one memory cell block to a corresponding one of A0 to A3 of another memory cell block can be reduced, as compared with the semiconductor device 110 shown in FIG. 4.
Note that the number of turns and the shapes of the turns of the interconnection lines are not limited to those shown in FIG. 10, and can be changed as needed. In addition, the internal structure of the semiconductor device 110 a (corresponding to FIG. 5) is shown in FIG. 11.
As noted above, according to the semiconductor device of the present embodiment, a memory can function as a logic circuit. By providing the output from one memory cell block to four memory cell blocks, feedback of data can be easily achieved.
In an existing manufacturing process of FPGAs, for example, a C language program is written, and subsequently, a hardware description language (HDL) is generated. Thereafter, logic synthesis is performed using the HDL so that a logic circuit is generated. Logic modules and interconnection lines are distributed on an FPGA on the basis of the logic circuit. That is, such complicated and highly advanced process procedures are required.
In contrast, according to the present embodiment, the semiconductor device functions as a memory or a storage element. Accordingly, after compiling a C language program, the resultant data can be loaded into the semiconductor device in the form of a truth table. Thus, the manufacturing process can be facilitated. In addition, since the semiconductor device of the present embodiment functions as a storage element, a different logic circuit can be achieved by simply changing a truth table written to the memory cell 200 without changing the interconnection lines.
This advantage is described in more detail below with reference to FIG. 12 (see FIG. 1 if necessary). FIG. 12 is a flow chart of an exemplary process performed when bit data is loaded into the semiconductor device that functions as a logic circuit.
First, in step S1101, the information processing apparatus 100 receives, from the input unit 101, a C language program that describes a desired function, and stores the C language program in the storage unit 102. The storage unit 102 prestores programs for performing a variety of functions (e.g., addition and subtraction).
Subsequently, in step S1102, an operator of the information processing apparatus 100 adds a declaration statement (the “Include” statements) to the C language program using the input unit 101 in order to refer to a necessary program prestored in the storage unit 102.
In step S1103, the processing unit 106 creates a truth table (e.g., a truth table 600 shown in FIG. 7) on the basis of the C language program including the added “Include” statement. In step S1104, the processing unit 106 generates bit data on the basis of the truth table. Subsequently, in step S1105, the processing unit 106 loads the bit data into the semiconductor device 110 via the communication unit 105.
In this way, according to the present embodiment, the operation that allows the semiconductor device 110 to function as a logic circuit can be simplified.
In addition, according to the semiconductor device of the present embodiment, since an actual logic circuit is not used, malfunction of part of the memory can be easily dealt with by, for example, not using the faulty part.
Furthermore, if, as described in the present embodiment, 32 word lines are used for one memory cell block, attenuation of data (signals) can be reduced, and therefore, the need for a sense amplifier can be eliminated. However, if the performance of the semiconductor device is critical, the number of the word lines may be increased to 33 or more by providing an intermediate buffer to the read sense amplifier or the read data lines.
Furthermore, according to the semiconductor device of the present embodiment, by using a plurality of memories and installing test programs in some of the memories, one of the other memories can be tested. In addition, after the test is completed, the test programs are erased from the memories. Thus, these memories can be used as normal memories.
Still furthermore, a memory included in a system LSI may be configured so as to function as the semiconductor device of the present embodiment. After the memory is self-tested, a C language test program is written to the memory so that a test logic circuit is achieved. Thus, other logic circuits in the system LSI can be tested.
Yet still furthermore, connection between the memory cell blocks is not limited to a connection pattern in which one memory block is connected to four other memory blocks, For example, any connection to three or more other memory cell blocks that enables data feedback may be employed. In addition, while the above-described embodiment has been described with reference to the differential read data lines, the interconnection may be achieved using one-side read data lines in accordance with a semiconductor layout and the logic circuit of a read address decoder.
While the present invention has been described as carried out in a specific embodiment thereof, it should be apparent to those skilled in the art that it is not limited thereto. For example, according to the present invention, a semiconductor device may be achieved using a dynamic random access memory (DRAM) or a flash memory in place of an SRAM.
Furthermore, in order to improve the performance of the memories, a function such as a pre-charging function may be employed.
Still furthermore, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising:

a plurality of memory cell blocks, each including a plurality of memory cells each storing a predetermined amount of data;

wherein each of the memory cell blocks stores, in the memory cells thereof, truth table data used for outputting desired logical values in response to input of a given address so as to function as a logic circuit, and wherein the number of inputs and the number of outputs of the memory cell block is three or more, and the memory cell blocks are connected to each other so that three or more outputs from one memory cell block are input to three or more other memory cell blocks.

2. The semiconductor device according to claim 1, wherein the number of inputs and the number of outputs of the memory cell block is four, and the memory cell blocks are connected to each other so that four outputs from one memory cell block are input to four other memory cell blocks.

3. The semiconductor device according to claim 1, wherein the plurality of memory cell blocks have a rectangular shape of the same size, and wherein the memory cell blocks are connected to each other such that at least some of the memory cell blocks are positionally shifted from an array arrangement.

4. The semiconductor device according to claim 1, wherein the plurality of memory cell blocks are arranged in an array and are connected to each other using interconnection lines.

5. The semiconductor device according to claim 1, wherein each of the memory cell blocks further includes two read address decoders therein, and the memory cell includes two read word lines corresponding to the two read address decoders, and wherein, when a voltage is applied to the two read word lines, data stored in the memory cell is read out using a read data line.

6. The semiconductor device according to claim 1, further comprising:

a write address decoder connected to the plurality of memory cell blocks, the write address decoder specifying an x address related to the plurality of memory cell blocks and the memory cell in the memory cell blocks; and

a write/read circuit connected to the plurality of memory cell block, the write/read circuit specifying a y address related to the plurality of memory cell blocks and the memory cell in the memory cell blocks so as to write data to the memory cell;

wherein the data is written to the memory cell by the write/read circuit when the memory cell is specified by the write address decoder and the write/read circuit.

7. The semiconductor device according to claim 1, wherein the semiconductor device functions as a normal storage device when the memory cell of the memory cell block does not store the truth table data.

8. The semiconductor device according to claim 7, wherein an operating area of the memory cell of the memory cell block is separated into two, and wherein, when a particular address select line of the read address decoder is switched, the operating areas of the memory cell are switched so that switching between an operation in which the memory cell functions as two logic circuits and an operation in which the memory cell functions as a logic circuit and a normal storage device is instantaneously performed.

9. The semiconductor device according to claim 1, wherein, when truth table data stored in memory cells in some of the memory cell blocks is updated, the operation of the semiconductor device is changed in accordance with the updated truth table data.

10. The semiconductor device according to claim 1, wherein the semiconductor device is included in a system LSI, the semiconductor device performs a self-test function, and the semiconductor device tests other logic circuits included in the system LSI.

11. The semiconductor device according to claim 1, wherein the semiconductor device operates on the basis of a compilation result of a C language program that describes the operation of the semiconductor device.