JP4187714B2 - Semiconductor memory layout method and semiconductor memory - Google Patents

Description

  The present invention relates to a layout method of a semiconductor memory (compiled memory) that is laid out in a desired number of rows and columns, that is, a desired word size and bit size, by editing a circuit registered in a library in advance. The present invention also relates to a semiconductor memory.

  In recent years, with the improvement of semiconductor technology, various logic integrated circuits with built-in memories have been developed. In these logic integrated circuits with built-in memories, from high-function memories to low-function memories. Therefore, a compiled memory having various functions is required.

  For example, FIG. 5A shows a part of a so-called 1 RW (read / write) compiled memory having one read / write port, where 1 is a memory cell for 1 RW. 2 is a row decoder for 1RW, and 3 is an input / output circuit for 1RW.

  FIG. 5B shows a part of a so-called 2RW compiled memory having multiple ports, for example, two read / write ports, in which 4 is a memory cell for 2RW. Reference numeral 5 denotes a 2RW row decoder, and reference numeral 6 denotes a 2RW input / output circuit.

  When layout is performed for these 1RW compiled memory and 2RW compiled memory, the memory cell 1 for 1RW, the row decoder 2 for 1RW, the input / output circuit 3 for 2RW, 2RW The memory cell 4, the 2RW row decoder 5, the 2RW input / output circuit 6 and the like are created as basic circuits.

For each of these basic circuits, a layout and circuit simulation are performed, and then a physical compiler, which is a program for automatically arranging the basic circuits, is created, and the operation of the automatically arranged entire circuits is verified. A logic compiler, which is a program of, was created.
Japanese Unexamined Patent Publication No. 4-1993

  As described above, conventionally, when layout is performed for a compiled memory, a basic circuit to be registered in a library is created for each compiled memory having different functions.

  For this reason, when trying to lay out various compiled memories with different functions according to customer requirements, it is necessary to create a basic circuit for each compiled memory with different functions in advance. This required a great amount of man-hours for layout, and hindered the reduction of development man-hours, the shortening of the development period, and early start-up.

  In view of the above, the present invention provides a semiconductor memory layout method and a semiconductor memory that can be laid out with a small number of man-hours and can achieve a reduction in development man-hours, a shortened development period, and an early start-up. Objective.

  The semiconductor memory layout method of the present invention includes a step of registering layout data of memory cells, row decoders, and input / output circuits necessary for constituting a one-read / write compiled memory as a basic circuit, and an option The circuit includes a read word line portion of the memory cell, a write word line portion of the memory cell, a read bit line portion of the memory cell, a write bit line portion of the memory cell, a read word line portion of the row decoder, and the row A step of registering layout data of each of the write word line unit, the output circuit, and the input circuit of the decoder, and a step of laying out the compiled memory by a combination of the registered basic circuit or a combination of the basic circuit and the optional circuit. That's it.

The semiconductor memory of the present invention has a port configuration consisting of m read ports and n write ports, where at least one of them is a natural number of 2 or more, and memory cells are arranged in a matrix, A plurality of memory cell units for holding data to be read / written, and a plurality of word lines provided for each row of the plurality of memory cell units, and connected to the memory cells in the plurality of memory cell units. A plurality of row decoder units to be selected, and provided for each column of the plurality of memory cell units, input / output data on a plurality of bit lines connected to the memory cells in the plurality of memory cell units. A semiconductor memory comprising a plurality of input / output circuit units, wherein each of the memory cell units is a read / write port. 1 a basic memory cell portion of which correspond to and configuration, provided on a side where the row decoder units of each Rutotomoni the memory cell unit provided adjacent to said primary memory cell section are arranged, m-1 Memory cell read word line units and n-1 memory cell write word line units , which are provided adjacent to the basic memory cell unit, and the input / output circuit unit of the memory cell unit is disposed. Provided with m−1 read bit line portions and n−1 write bit line portions, and each of the row decoder units corresponds to one read / write port configuration. M-1 row decoder read words provided adjacent to each of the basic row decoder units. Each of the input / output circuit units includes one basic input / output circuit unit corresponding to one read / write port configuration, and n-1 row decoder write word line units. It comprises m−1 output circuit units and n−1 input circuit units provided adjacent to the basic input / output circuit unit.

  According to the semiconductor memory layout method of the present invention, a semiconductor memory having a desired function is laid out by combining a plurality of basic circuits or a combination of a plurality of basic circuits and a desired option circuit. It is not necessary to create a basic circuit for each, and various semiconductor memories having different functions can be laid out with less man-hours.

  According to the semiconductor memory of the present invention, it is not necessary to create a basic circuit for each semiconductor memory having different functions, and various semiconductor memories having different functions can be laid out with less man-hours. Shortening and early start-up can be achieved.

  FIG. 1 is a diagram for explaining one embodiment of a semiconductor memory layout method of the present invention. In one embodiment of the semiconductor memory layout method of the present invention, first, circuit diagrams of a basic circuit and an optional circuit are shown. Created.

  Here, as a basic circuit, the simplest memory cell 11 necessary for configuring a 1RW compiled memory, the simplest row decoder 12 required for configuring a 1RW compiled memory, and a 1RW compiled The simplest input / output circuit 13 necessary for configuring the memory and the column decoder 14 capable of supporting the maximum number of bits are selected.

  The optional circuit includes a memory cell read word line unit 15, a memory cell write word line unit 16, a memory cell read bit line unit 17, a memory cell write bit line unit 18, and a row decoder read word line unit. 19, a write word line section 20 of the row decoder, an output circuit 21, an input circuit 22, an address register 23, an address side test circuit 24, an input / output register 25, and a data side test circuit 26 are selected.

  Next, layout and circuit simulation are performed for each of the basic circuits 11 to 14 and the option circuits 15 to 26, and the respective circuit diagram data and layout data are registered in the library.

  Then, a physical compiler that is a program for automatically arranging the basic circuits 11 to 14 and the option circuits 15 to 26 is created, and a logic compiler that is a program for verifying the operation of the automatically arranged entire circuits is created. Is done.

  Here, based on one embodiment of the semiconductor memory layout method of the present invention, for example, when a 1 RW compiled memory is laid out, as shown in a part of FIG. A necessary number of memory cells 11, row decoders 12 and input / output circuits 13 are arranged so as to have a bit size, and a column decoder 14 is arranged.

  When a multi-port, for example, 2RW1R compiled memory is laid out, the memory cell 11 and the row decoder 12 have a desired word size and bit size, as shown in part of FIG. In addition, a necessary number of input / output circuits 13 are arranged, and a column decoder 14 is arranged.

  A read word line unit 15, a memory cell write word line unit 16, a memory cell read bit line unit 17, and a memory cell write bit line unit 18 are added to the memory cell 11.

  In addition, a read word line unit 19 of the row decoder and a write word line unit 20 of the row decoder are added to the row decoder 12, and an output circuit 21 and an input circuit 22 are added to the input / output circuit 13. The compiled memory configured as described above is the first embodiment of the semiconductor memory of the present invention.

  Further, for example, when a 2RW1R compiled memory having a test circuit, an address register, and an input / output register is laid out, the basic circuit 11 shown in FIG. -14 and option circuits 15-22, an address register 23, an address side test circuit 24, an input / output register 25, and a data side test circuit 26 are added. The compiled memory configured as described above is the second embodiment of the semiconductor memory of the present invention.

  As described above, in the embodiment of the semiconductor memory layout method of the present invention, the basic circuits 11 to 14 necessary for configuring a 1 RW compiled memory and the optional circuits 15 to 26 necessary for the optional function are provided. A circuit diagram is created, each circuit diagram data and layout data are registered in a library, and a desired range is obtained within a predetermined range by combining these basic circuits 11 to 14 or the basic circuits 11 to 14 and option circuits 15 to 26. Compiled memory is laid out.

  Therefore, according to an embodiment of the semiconductor memory layout method of the present invention, there is no need to create a circuit diagram of a basic circuit for each compiled memory having different functions, and the number of compiled memories having different functions can be reduced. Layout can be achieved, reducing development man-hours, shortening the development period, and achieving early start-up.

  Note that Patent Document 1 describes only the contents corresponding to the prior art of the present invention (FIG. 5) regarding the circuit configuration of the semiconductor memory.

It is a figure for demonstrating one Embodiment of the layout method of the semiconductor memory of this invention. It is a figure which shows the structure of a part of an example of 1 RW compiled memory laid out based on one Embodiment of the layout method of the semiconductor memory of this invention. It is a figure which shows the structure of a part of an example (1st Embodiment of the semiconductor memory of this invention) of 2RW1R compiled memory laid out based on one Embodiment of the layout method of the semiconductor memory of this invention. It is a figure which shows the structure of a part of other example (2nd Embodiment of the semiconductor memory of this invention) of the compiled memory of 2RW1R laid out based on one Embodiment of the layout method of the semiconductor memory of this invention. It is a figure for demonstrating the layout method of the conventional compiled memory.

Explanation of symbols

11-14 Basic circuit 15-26 Optional circuit

Claims (6)

m and n each having at least one natural number of 2 or more, and having a port configuration consisting of m read ports and n write ports,
A plurality of memory cell units in which memory cells are arranged in a matrix and hold data to be read / written, and
A plurality of row decoder units provided for each row of the plurality of memory cell units, for selecting a plurality of word lines connected to the memory cells in the plurality of memory cell units;
A plurality of input / output circuit units that are provided for each column of the plurality of memory cell units and that input / output data on a plurality of bit lines connected to the memory cells in the plurality of memory cell units; Semiconductor memory,
Each of the memory cell units includes
One basic memory cell unit corresponding to one read / write port configuration;
The row decoder unit is provided on the side to be arranged, the read word line portions and the n-1 for m-1 memory cells of each Rutotomoni the memory cell unit provided adjacent to said primary memory cell section A write word line portion for the memory cell ,
M−1 read bit line units and n−1 write bits provided adjacent to the basic memory cell unit and provided on the side of the memory cell unit where the input / output circuit unit is disposed. Line part,
Each of the row decoder units is
One basic row decoder corresponding to one read / write port configuration;
Each of them is composed of m-1 row decoder read word line units and n-1 row decoder write word line units provided adjacent to the basic row decoder unit,
Each of the input / output circuit units is
1 basic input / output circuit unit corresponding to 1 read / write port configuration;
A semiconductor memory comprising m-1 output circuit units and n-1 input circuit units, which are respectively provided adjacent to the basic input / output circuit unit. 2. The column decoder for selecting the plurality of bit lines is provided in common for the plurality of memory cell units, the plurality of row decoder units, and the plurality of input / output circuit units. Semiconductor memory. 2. The semiconductor memory according to claim 1, further comprising a plurality of address register units which are provided for each row of the plurality of memory cell units and hold addresses inputted to the plurality of row decoder units. 2. The semiconductor memory according to claim 1, further comprising a plurality of input / output register units that are provided for each column of the plurality of memory cell units and hold data input to the plurality of input / output circuit units. A plurality of address side test circuit units provided for each row of the plurality of memory cell units, for testing the semiconductor memory;
2. The semiconductor memory according to claim 1, further comprising a plurality of data side test circuit units that are provided for each column of the plurality of memory cell units and that test the semiconductor memory. The column decoder
Arranged between a basic row decoder of one memory cell unit of the plurality of memory cell units and one basic input / output circuit portion of the plurality of input / output circuit units.
The semiconductor memory according to claim 2.

Images