JPH0844781A - Laying-out method for compiled memory - Google Patents

Abstract

PURPOSE:To lay out the compiled memory with a desired function in small man-hours by laying out the memory with plural basic circuits or a combination of plural basic circuits and desired option circuits. CONSTITUTION:The basic circuits 11-14 and option circuits 15-26 are laid out and simulated respectively and circuit diagram data and layout data are registered in a library. Then a physical compiler as a program for arranging the basic circuits 11-14 and option circuits 15-26 automatically is generated, and a logical compiler as a program for verifying the operation of the entire circuit which is automatically arranged is generated. The desired compiled memory is laid out within a specific range with the basic circuits 11-14 or the combination of the basic circuits 11-14 and option circuits 15-26. Therefore, the memory can be laid out in small man-hours.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory which is laid out in a desired number of rows and columns, that is, a desired word size and bit size by editing a circuit registered in a library in advance, that is, a so-called The present invention relates to a compiled memory layout method.

In recent years, with the improvement of semiconductor technology, various logic integrated circuits having a built-in memory have been developed.
In a logic integrated circuit containing these memories,
Compiled memories having various functions from high-performance memory to low-function memory are required.

[0003]

2. Description of the Related Art For example, FIG. 5A shows a so-called 1RW (read / write) having one read / write port.
1 shows a part of a compiled memory (write), in which 1 is a memory cell for 1RW, 2 is a row decoder for 1RW, and 3 is an input / output circuit for 1RW.

FIG. 5B also shows a so-called 2 port having multiple ports, for example, 2 read / write ports.
It shows a part of a compiled memory of RW. In the figure, 4 is a memory cell for 2RW, 5 is a row decoder for 2RW, and 6 is an input / output circuit for 2RW.

[0005] These 1RW compiled memory,
When the layout is performed for the 2RW compiled memory, the 1RW memory cell 1, the 1RW row decoder 2, the 1RW input / output circuit 3, the 2RW memory cell 4, and the 2RW memory cell are prepared in advance. Input / output circuits 6 for the row decoders 5 and 2RW are created as basic circuits.

After performing layout and circuit simulation for each of these basic circuits, a physical compiler, which is a program for automatically arranging the basic circuits, is created, and the operation of the automatically arranged whole circuit is performed. A logical compiler, which is a program for verification, was created.

[0007]

As described above, conventionally, when the layout of the compiled memory is performed, the basic circuit to be registered in the library is created for each compiled memory having a different function. .

For this reason, when various compiled memories having different functions are to be laid out according to the customer's request, the basic circuit is created for each compiled memory having different functions. This requires a lot of man-hours for layout, which hinders reduction of development man-hours, shortening of development period, and early start-up.

In view of the above points, the present invention makes it possible to lay out various compiled memories having different functions with a small number of man-hours, and achieves reduction of development man-hours, shortening of development period, and early start-up. An object of the present invention is to provide a compiled memory layout method.

[0010]

A method of designing a compiled memory according to the present invention comprises a plurality of basic circuits required for constructing a basic compiled memory and a plurality of option circuits required for an optional function. Registered,
It is a layout of a compiled memory having a desired function by using a plurality of basic circuits or a combination of a plurality of basic circuits and a desired option circuit.

[0011]

According to the present invention, a compiled memory having a desired function is laid out by using a plurality of basic circuits or a combination of a plurality of basic circuits and a desired option circuit. It is not necessary to create a basic circuit for each memory, and various compiled memories having different functions can be laid out with a small number of steps.

[0012]

1 is a diagram for explaining an embodiment of the present invention. In this embodiment, first, a circuit diagram of a basic circuit and an option circuit is prepared.

Here, as a basic circuit, the simplest memory cell 11 required to form a 1RW compiled memory, the simplest row decoder 12 required to form a 1RW compiled memory, 1RW. The simplest input / output circuit 13 and the column decoder 14 capable of dealing with the maximum number of bits required for constructing the compiled memory are selected.

As the option circuit, the read word line section 15 of the memory cell, the write word line section 16 of the memory cell, the read bit line section 17 of the memory cell, the write bit line section 18 of the memory cell, and the read of the row decoder. Word line unit 19, write word line unit 20 of row decoder, output circuit 21, input circuit 2
2, address register 23, address side test circuit 2
4, the input / output register 25 and the data side test circuit 26 are selected.

Next, layout and circuit simulation are performed on each of the basic circuits 11 to 14 and the option circuits 15 to 26, and the respective circuit diagram data and layout data are registered in the library.

A physical compiler, which is a program for automatically arranging the basic circuits 11 to 14 and the option circuits 15 to 26, is created, and a logic, which is a program for verifying the operation of the automatically arranged whole circuit. A compiler is created.

Based on this embodiment, for example, 1
When the RW compiled memory is laid out, a memory cell 11, a row decoder 12 and an input / output circuit 13 are required to have a desired word size and bit size as shown in a part of FIG. And column decoders 14 are arranged.

Further, in the case where a multi-port, for example, a 2RW1R compiled memory is laid out, FIG.
As shown in FIG. 1, a required number of memory cells 11, row decoders 12 and input / output circuits 13 are arranged, and column decoders 14 are arranged so as to have a desired word size and bit size.

The read word line section 15 for the memory cell 11 and the write word line section 1 for the memory cell
6, a read bit line portion 17 of the memory cell and a write bit line portion 18 of the memory cell are added.

A read word line section 19 of the row decoder and a write word line section 20 of the row decoder are added to the row decoder 12, and an output circuit 21 and an input circuit 22 are added to the input / output circuit 13. To be done.

Further, for example, when a 2RW1R compiled memory having a test circuit, an address register and an input / output register is laid out, FIG.
As shown in a part thereof, the basic circuits 11 to 1 shown in FIG.
4, an address register 23, an address-side test circuit 24, an input / output register 25, and a data-side test circuit 26 are added in addition to 4 and the option circuits 15 to 22.

Thus, in this embodiment, 1RW
Basic circuit 1 required to configure the compiled memory of
1 to 14 and optional circuit 1 required for optional functions
5 to 26 circuit diagrams are created, the respective circuit diagram data and layout data are registered in the library, and a predetermined range is obtained by combining the basic circuits 11 to 14 or the basic circuits 11 to 14 and the option circuits 15 to 26. At
The desired compiled memory is laid out.

Therefore, according to this embodiment, it is not necessary to prepare a circuit diagram of a basic circuit for each compiled memory having a different function, and a compiled memory having a different function can be laid out with a small number of steps.

[0024]

As described above, according to the present invention, a plurality of basic circuits or a combination of a plurality of basic circuits and a desired option circuit necessary for forming a basic compiled memory can be used to obtain a desired Since a compiled memory having functions is laid out, it is not necessary to create a basic circuit for each compiled memory having a different function, and a compiled memory having a different function can be laid out with a small number of steps. It is possible to reduce the development man-hours, the development period, and the early start-up.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an example of a 1 RW compiled memory laid out according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an example of a 2RW1R compiled memory laid out according to an embodiment of the present invention.

FIG. 4 is a diagram showing the configuration of another example of a 2RW1R compiled memory laid out according to an embodiment of the present invention.

FIG. 5 is a diagram for explaining a conventional compiled memory layout method.

[Explanation of symbols]

 11-14 Basic circuit 15-26 Optional circuit

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Claims (3)

[Claims] 1. A plurality of basic circuits necessary for configuring a basic compiled memory and a plurality of option circuits necessary for an optional function are registered, and the plurality of basic circuits or the plurality of basic circuits are registered. Compiled with the desired function by combining the circuit and the desired option circuit
A method for laying out compiled memory, characterized by laying out memory. 2. The basic compiled memory comprises:
2. The compiled memory layout method according to claim 1, wherein the compiled memory has one read / write port. 3. The layout method for a compiled memory according to claim 1, wherein the option circuit includes a circuit for increasing the number of ports, an address register, an input / output register, or a test circuit.