JP2006172623A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the test of a built-in RAM can be carried out with reduced number of external terminals, a defective point can be simply specified, and connection of an input/output terminal of the outside terminal and a memory part can be switched on the basis of package information. <P>SOLUTION: When the input/output of the RAM is connected to the external terminal of a semiconductor device, flip-flops constituting first and second latch circuits 110, 111 are provided between the external terminal and the address terminal 115 and a data input terminal 116 of an SRAM 101. Since an address/data external terminal 107 can be shared by the address terminal 115 and the data input terminal 116 by latching data by the first and second latch circuits 110, 111 so that test vector can be inputted simultaneously to the SRAM 101, inspection of the RAM can be carried out even when the number of external terminals are reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a RAM test circuit incorporated in a system LSI.

  In recent years, semiconductor integrated circuits have succeeded in reducing the area due to advances in ultrafine processing technology. Under such circumstances, demands for semiconductor integrated circuits have been greatly increased, and the number of transistors incorporated in the circuit has been remarkably increased. For this reason, it has become very difficult to inspect a semiconductor integrated circuit. In particular, an easy-to-inspect design that can easily inspect a random access memory (hereinafter referred to as RAM) that has become almost indispensable for a semiconductor integrated circuit has become essential.

FIG. 20 shows a configuration of a semiconductor device incorporating a general SRAM test circuit.
In FIG. 20, reference numeral 2000 denotes a semiconductor device. The semiconductor device 2000 includes an SRAM 2001, a test circuit 2002, a mode storage unit 2003, a CLK external terminal 2004, a WEN external terminal 2005, a REN external terminal 2006, an ADR external terminal 2007, a DIN external terminal 2008, and a DOUT external terminal 2009.

  The semiconductor device 2000 can transmit signals with an external device via the CLK external terminal 2004, the WEN external terminal 2005, the REN external terminal 2006, the ADR external terminal 2007, the DIN external terminal 2008, and the DOUT external terminal 2009. . The CLK external terminal 2004 is a terminal for inputting a clock to the SRAM 2001 in the RAM test mode. A WEN external terminal 2005 is a terminal for inputting a write enable signal to the SRAM 2001 in the RAM test mode. The REN external terminal 2006 is a terminal for inputting a read permission (read enable) signal to the SRAM 2001 in the RAM test mode. The ADR external terminal 2007 is a terminal for inputting an address signal to the SRAM 2001 in the RAM test mode. The DIN external terminal 2008 is a terminal for inputting a data signal to the SRAM 2001 in the RAM test mode. The DOUT external terminal 2009 is a terminal for outputting data from the SRAM 2001 to the outside in the RAM test mode.

  The SRAM 2001 includes a CLK terminal 2011, a WEN terminal 2012, a REN terminal 2013, an ADR terminal 2014, a DIN terminal 2015, and a DOUT terminal 2016, and transmits signals to and from other circuits in the semiconductor device 2000 via these terminals. Can do. A CLK terminal 2011 is a terminal for inputting an operation clock of the SRAM 2001. The WEN terminal 2012 is a terminal for inputting a write permission (write enable) signal. The REN terminal 2013 is a terminal for inputting a read permission (read enable) signal. The ADR terminal 2014 is a terminal for inputting an address signal of the SRAM 2001. The DIN terminal 2015 is a terminal for inputting write data of the SRAM 2001. The DOUT terminal 2016 is a terminal for outputting data written in the SRAM 2001.

  The mode storage unit 2003 stores the operation mode of the semiconductor device 2000 and transmits the information to the peripheral circuit, thereby enabling switching between the normal mode and the test mode.

  The test circuit 2002 changes the operation mode by the mode storage unit 2003. After shifting to the RAM test mode by the mode storage unit 2003, the CLK external terminal 2004 is connected to the CLK terminal 2011, the WEN external terminal 2005 is connected to the WEN terminal 2012, and the REN external terminal 2006 by a control signal of the control circuit 2010. Is connected to the REN terminal 2013 and the ADR external terminal 2007 is connected to the ADR terminal 2014. The DIN external terminal 2008 is connected to the DIN terminal 2015.

  Thereby, at the time of inspection, the test vector can be directly input to the SRAM 2001 to inspect the SRAM. Even when there are a plurality of SRAMs, the control circuit can select the SRAM to be inspected from among the plurality of SRAMs.

  However, the conventional semiconductor device requires the same number of external terminals as the number of input terminals and output terminals of the SRAM when inspecting the memory, and it is difficult to inspect the SRAM with a semiconductor device having a small number of external terminals. . Further, in the conventional semiconductor device, even if the number of external terminals is sufficient, the inspection of the SRAM becomes difficult when the number of pins of the package is small and the number of external terminals connected to the pins of the package is limited.

For this reason, a technology that incorporates a circuit that can perform pass / fail judgment between the output terminal and the external terminal of the SRAM, and the result can be judged by 1 bit, such as low output for a non-defective product and high output for a non-defective product. There is also. It has been reported that this technique can reduce the number of external terminals used for inspection (see Patent Document 1).
JP-A-5-20898

  However, in the conventional semiconductor device, since the number of RAM input / output terminals has increased as the capacity of the RAM incorporated in the semiconductor device has increased, there has been a problem that the number of required external terminals tends to increase further. .

  Even when the number of external input / output terminals is the same as the number of RAM input / output terminals, for example, there are external terminals that are not connected to package pins during packaging, such as debugging terminals. There was a problem that the RAM test could not be performed.

  The present invention has been made in order to solve the above-described conventional problems. The built-in RAM can be tested with a small number of external terminals, and a defective portion can be easily identified. An object of the present invention is to provide a semiconductor device capable of switching connection between an external terminal and an input / output terminal of a memory portion based on information.

  In order to solve the above problems, the present invention has the following configuration. A semiconductor device according to claim 1 of the present invention includes an electrically rewritable volatile memory unit, an operation mode storage unit that stores a plurality of operation modes including a memory test mode for testing the operation of the memory unit, A test circuit for testing the memory unit; and a plurality of external terminals for transmitting signals to the outside, wherein the external terminal is a WEN external terminal connected to a write enable terminal of the memory unit in a memory test mode And an ADR / DIN external terminal for inputting an address signal and a data signal of the memory unit in the memory test mode, and the test circuit receives an address signal and a data signal input from the ADR / DIN external terminal in the memory test mode. It has a latch circuit which memorizes temporarily.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the latch circuit is constituted by a shift register.

  According to a third aspect of the present invention, there is provided a semiconductor device comprising: an electrically rewritable volatile memory portion; an operation mode storage portion for storing a plurality of operation modes including a memory test mode for testing the operation of the memory portion; A first external terminal and a second external terminal for transmitting signals to and from the outside, and a test circuit for testing the memory unit, and when the memory test mode is selected, the memory unit Connecting all even-numbered terminals of the data input terminals and the first external terminals, and connecting all odd-numbered terminals of the data input terminals of the memory unit and the second external terminals. It is characterized by this.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, further comprising a third external terminal and a fourth external terminal for transmitting a signal to the outside, wherein the test circuit comprises: A first data output circuit that selects and outputs a logical product and a logical sum of data outputs from even-numbered terminals of the data output terminals of the memory unit; and data from odd-numbered terminals of the data output terminals of the memory unit. A second data output circuit for selecting and outputting a logical product and a logical sum of the outputs; and when the memory test mode is selected, the output of the first data output circuit is transmitted to the third external output The output from the terminal is output to the outside, and the output of the second data output circuit is output from the fourth external terminal to the outside.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the fourth aspect, comprising one or more of the memory units, and when the memory test mode is selected, all of the data input terminals of the memory unit are selected. Connect even-numbered terminals and the first external terminal, connect all odd-numbered terminals of the data input terminal of the memory unit and the second external terminal, and connect all of the data output terminals of the memory unit An even-numbered terminal is connected to the first data output circuit, and all odd-numbered terminals of the data output terminals of the memory unit are connected to the second data output circuit. is there.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fifth aspect, further comprising a second memory unit having a different number of columns from the memory unit, wherein the test circuit includes the second memory unit. It further has an address conversion circuit for converting an address input based on the number of columns.

  A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, further comprising a package selection external terminal for inputting package information, wherein the number of external terminals connected to package pins is the memory. When the number of input / output terminals is larger than the number of input / output terminals, and in the memory test mode, all the input / output terminals of the memory section are switched to be directly connected to a plurality of predetermined external terminals.

  According to the semiconductor device of the first aspect of the present invention, the operation mode storage unit stores a plurality of operation modes including an electrically rewritable volatile memory unit and a memory test mode for testing the operation of the memory unit. And a test circuit for testing the memory unit and a plurality of external terminals for transmitting signals to the outside, and the external terminal is connected to the write enable terminal of the memory unit in the memory test mode An external terminal and an ADR / DIN external terminal for inputting an address signal and a data signal of the memory unit in the memory test mode, and the test circuit includes an address signal input from the ADR / DIN external terminal in the memory test mode, and Since it has a latch circuit that temporarily stores data signals, it is Effect that it is possible to reduce the number of external terminals required for the address input and data input device easy to obtain.

  According to a second aspect of the semiconductor device of the present invention, in the semiconductor device according to the first aspect, the latch circuit is constituted by a shift register. An effect is obtained in which the number of external terminals required for input can be easily reduced, and generation of a clock input to the latch circuit at that time can be simplified.

  According to a semiconductor device of a third aspect of the present invention, an operation mode storage unit for storing a plurality of operation modes including an electrically rewritable volatile memory unit and a memory test mode for testing the operation of the memory unit. And a first external terminal for transmitting a signal to the outside, a second external terminal, and a test circuit for testing the memory unit, and when the memory test mode is selected, Connecting all even-numbered terminals of the data input terminals of the memory unit and the first external terminal; and connecting all odd-numbered terminals of the data input terminals of the memory unit and the second external terminals. Since the connection is made, data of “00”, “FF”, “55”, “AA” (when 8-bit) can be input to the memory section in two memory terminals in the memory test mode. Can Effect can be obtained.

  According to a semiconductor device according to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the test circuit further comprises a third external terminal and a fourth external terminal for transmitting a signal to the outside. The first data output circuit for selecting and outputting the logical product and the logical sum of the data outputs from the even-numbered terminals of the data output terminals of the memory unit, and the odd-numbered terminals of the data output terminals of the memory unit A second data output circuit that selects and outputs a logical product and a logical sum of the data outputs of the first and second data outputs, and when the memory test mode is selected, outputs the first data output circuit to the third data output circuit. Since the output of the second data output circuit and the output of the second data output circuit are output to the outside from the fourth external terminal, in the memory test mode, “00”, “FF”, “ 55 " "AA" is the effect that the value of (8 when bits) can be read easily by using two external terminals the data in the memory unit that is written is obtained.

  According to a semiconductor device of a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, when one or more of the memory units are provided and the memory test mode is selected, the data input terminal of the memory unit is selected. Connect all even-numbered terminals and the first external terminal, connect all odd-numbered terminals of the data input terminal of the memory unit and the second external terminal, and connect the data output terminal of the memory unit Since all the even-numbered terminals and the first data output circuit are connected, and all the odd-numbered terminals of the data output terminals of the memory unit are connected to the second data output circuit. Even when there are a plurality of memory portions of the same type, there is an effect that the memory can be tested with a small number of external terminals.

  According to a semiconductor device of a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, even when memory units having different numbers of columns coexist, the memory unit can be tested with a small number of external terminals by using an address conversion circuit. There is an effect that can be done.

  According to a semiconductor device of a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects of the present invention, the semiconductor device further includes a package selection external terminal for inputting package information, and the number of external terminals connected to the pins of the package is Since the number of input / output terminals of the memory unit is larger than the number of input / output terminals and in the memory test mode, all the input / output terminals of the memory unit are switched so as to be directly connected to a plurality of predetermined external terminals. The test can be performed and the test time can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
A semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows a configuration of a semiconductor device according to a first embodiment of the present invention.
In FIG. 1, reference numeral 100 denotes a semiconductor device. The semiconductor device 100 includes an SRAM 101, a test circuit 102, a mode storage unit 103, a CLK external terminal 104, a WEN external terminal 105, a REN external terminal 106, an ADR / DIN external terminal 107, a DOUT external terminal 108, and a package selection external terminal 118. . The semiconductor device 100 transmits signals to and from an external device via the CLK external terminal 104, the WEN external terminal 105, the REN external terminal 106, the ADR / DIN external terminal 107, the DOUT external terminal 108, and the package selection external terminal 118. be able to. The CLK external terminal 104 is a terminal for inputting a clock to the SRAM 101 in the memory test mode (described later). The WEN external terminal 105 is a terminal for inputting a write enable signal to the SRAM 101 in the memory test mode. The REN external terminal 106 is a terminal for inputting a read permission (read enable) signal to the SRAM 101 in the memory test mode. The ADR / DIN external terminal 107 is a terminal for inputting an address signal and a data signal to the SRAM 101 in the memory test mode. The DOUT external terminal 108 is a terminal for outputting data from the SRAM 101 to the outside in the RAM test mode. The package selection external terminal 118 is a terminal for inputting information such as the type of package and the number of pins.

  The SRAM 101 has a CLK terminal 112, a WEN terminal 113, a REN terminal 114, an ADR terminal 115, a DIN terminal 116, and a DOUT terminal 117, and transmits signals to and from other circuits in the semiconductor device 100 via these terminals. Can do. The CLK terminal 112 is a terminal for inputting an operation clock of the SRAM 101. The WEN terminal 113 is a terminal for inputting a write permission (write enable) signal. The REN terminal 114 is a terminal for inputting a read permission (read enable) signal. In the first embodiment, at the time of write enable or read enable, each is enabled at Low. The ADR terminal 115 is a terminal for inputting an address signal of the SRAM 101, and the SRAM 101 of the first embodiment is assumed to have eight ADR terminals (256 addresses). The DIN terminal 116 is a terminal for inputting write data of the SRAM 101, and the SRAM 101 of the first embodiment is assumed to have 16 DIN terminals 116. The DOUT terminal 117 is a terminal for outputting data written in the SRAM 101, and the SRAM 101 of the first embodiment is assumed to have 16 DOUT terminals. In the first embodiment, it is assumed that data is written at the moment when the write enable signal is asserted and the operation clock of the SRAM 101 changes from High to Low. In the first embodiment, it is assumed that data is output from the moment when the read enable signal is asserted and the operation clock of the SRAM 101 changes from High to Low.

  The mode storage unit 103 stores the operation mode of the semiconductor device 100 and transmits the information to peripheral circuits. The operation mode is roughly divided into a normal mode and a test mode that perform normal functions. For example, the test mode includes a scan mode in which all logic circuits in the semiconductor device 100 are inspected, a burn-in mode in which a higher voltage is applied than in normal operation, and a memory test mode in which the operation of the SRAM is inspected. In the first embodiment, the memory test mode for inspecting the operation of the SRAM is entered. The operation mode is set by, for example, high or low from an external terminal (not shown).

  The test circuit 102 includes a clock control circuit 109, a first latch circuit 110, and a second latch circuit 111. In FIG. 1, the test circuit 102 has a circuit configuration in the memory test mode, and a switching circuit from the normal mode is not shown. The clock control circuit 109 inputs a clock and sends the clock to the first latch circuit 110 and the second latch circuit 111 at a predetermined timing. Each of the first latch circuit 110 and the second latch circuit 111 includes eight flip-flops. In FIG. 1, only one flip-flop of each of the first and second latch circuits 110 and 111 is shown. The first latch circuit 110 and the second latch circuit 111 temporarily store the input from the ADR / DIN external terminal 107. The output of the first latch circuit 110 is connected to the ADR terminal 115 of the SRAM 101, and the output of the second latch circuit 111 is connected to the lower 8 bits of the DIN terminal 116 of the SRAM 101. The ADR / DIN external terminal 107 and the DIN terminal 116 of the SRAM 101 are connected via the test circuit 102.

  In the test circuit 102, when the number of external terminals connected to the pins of the package is larger than the number of input / output terminals of the memory device (SRAM), and in the memory test mode, all the input / output terminals of the memory device are set to a predetermined plural number. Switch to connect directly to external terminal.

Next, a procedure for writing data to the SRAM will be described with reference to FIG.
FIG. 2 is a flowchart for writing data from the external terminal to the SRAM 101 in the memory test mode in the semiconductor device according to the first embodiment of the present invention.

  In FIG. 2, first, in step 201, 8-bit signals are input from the eight ADR / DIN external terminals 107. Next, at step 202, the first latch circuit 110 temporarily stores this signal. At this time, a clock is supplied to the eight flip-flops constituting the first latch circuit 110, and data is simultaneously stored in the eight flip-flops at the timing of the clock change. Next, at step 203, 8-bit signals are input again from the eight ADR / DIN terminals 107.

  In step 204, the second latch circuit 111 temporarily stores this signal. At this time, a clock is supplied to the eight flip-flops constituting the second latch circuit 111, and data is simultaneously stored in the eight flip-flops at the timing of the clock change. Next, at step 205, 8-bit signals are inputted again from the eight ADR / DIN external terminals 107 again. At this timing, the signals to be input are prepared at the ADR terminal 115 and the DIN terminal 116 of the SRAM 101.

  Next, in step 206, the WEN terminal 113 is driven low to make it in the write enable state, and then in step 207, the clock signal is changed from high to low. As a result, in step 208, the data designated by the DIN terminal 116 can be written to the address designated by the ADR terminal 115.

  As described above, according to the first embodiment, the test circuit 102 for testing the SRAM 101 and the plurality of external terminals for transmitting signals to the outside are provided, and the external terminals are written to the SRAM 101 in the memory test mode. A WEN external terminal 105 connected to the enable terminal 113 and an ADR / DIN external terminal 107 for inputting an address signal and a data signal of the SRAM 101 in the memory test mode. The test circuit 102 has the ADR / DIN in the memory test mode. Since the first and second latch circuits 110 and 111 for temporarily storing the address signal and the data signal input from the DIN external terminal 107 are provided, a total of 24 external terminals for the ADR terminal and the DIN terminal are conventionally required. The test of RAM is realized with 8 external terminals. There is an effect that theft can be.

  In the first embodiment of the present invention, an 8-bit signal input from eight ADR / DIN terminals is latched twice in total by the first and second latch circuits, and input to the ADR terminal and the DIN terminal. However, the number of times the signal is latched by the latch circuit is not limited to two. For example, a 4-bit signal input from four ADR / DIN terminals may be latched a total of five times by the first and second latch circuits, and the signals to be input to the ADR terminal and the DIN terminal may be arranged. In this way, the number of ADR / DIN external terminals can be reduced by reducing the amount of data latched in the latch circuit at a time and increasing the number of times of latching.

  In the first embodiment, the SRAM has a data bus width of 16 bits and an address bus width of 8 bits. However, the present invention is not limited to this.

(Embodiment 2)
A semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.
FIG. 3 is a block diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention.

  The semiconductor device 300 according to the second embodiment shown in FIG. 3 is different from the semiconductor device 100 according to the first embodiment shown in FIG. 1 as follows. The same constituent blocks as those in the first embodiment are given the same numbers as in FIG.

  In FIG. 3, the first latch circuit 310 and the second latch circuit 311 are formed of shift registers. Here, in the second embodiment, the first latch circuit 310 and the second latch circuit 311 have a two-stage configuration. For example, the Q output of the first flip-flop of the first latch circuit 310 is connected to the D input of the first flip-flop of the second latch circuit 311.

  The clock control circuit 309 does not need to generate a clock for each latch circuit, and supplies the same clock to both the first latch circuit 310 and the second latch circuit 311.

Next, a procedure for writing data to the SRAM 101 will be described with reference to FIG.
FIG. 4 is a flowchart for writing data from the external terminal to the SRAM 101 in the memory test mode in the semiconductor device according to the second embodiment of the present invention.

  In FIG. 4, first, in step 401, 8-bit signals are input from the eight ADR / DIN external terminals 107. Next, at step 402, the first latch circuit 310 temporarily stores this signal. At this time, a clock is supplied to the eight flip-flops constituting the first latch circuit 310, and data is simultaneously stored in the eight flip-flops at a clock change timing. At the same time, a clock is supplied to the eight flip-flops constituting the second latch circuit 311 to temporarily store the Q output of the first latch circuit 310.

  Next, at step 403, 8-bit signals are input from the eight ADR / DIN external terminals 107 again. Next, in step 404, the first latch circuit 310 temporarily stores the signal input in step 403, and at the same time, the second latch circuit 311 receives the signal input in step 401, that is, the output signal of the first latch circuit 310. Memorize temporarily.

  Next, at step 405, the 8-bit signal is inputted again from the eight ADR / DIN external terminals 107 again. At this timing, the signals to be input are prepared at the ADR terminal 115 and the DIN terminal 116 of the SRAM 101. Next, in step 406, the WEN terminal 113 is driven low to make it in the write enable state, and then in step 407, the clock signal is changed from high to low. As a result, the data designated by the DIN terminal 116 can be written at the address designated by the ADR terminal 115 in step 408.

  As described above, according to the second embodiment, since the first latch circuit 310 and the second latch circuit 311 are configured by shift registers, external terminals for the ADR terminal and the DIN terminal are conventionally provided. This has the effect that a RAM test can be realized with eight external terminals, where a total of 24 are required.

  In addition, since only one clock system is output from the clock control circuit 309, the configuration of the clock control circuit 309 can be simplified.

  In the present invention, the case where the number of times of latching the input from the ADR / DIN terminal is divided into two is described, but it is not limited to two as in the first embodiment. Furthermore, the SRAM has a data bus width of 16 bits and an address bus width of 8 bits, but is not limited to this.

(Embodiment 3)
A semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS.
FIG. 5 shows a configuration of a semiconductor device according to the third embodiment of the present invention.

  In FIG. 5, reference numeral 500 denotes a semiconductor device. The semiconductor device 500 includes an SRAM 101, a test circuit 102, a mode storage unit 103, a CLK external terminal 104, a WEN external terminal 105, a REN external terminal 106, an ADR external terminal 507, a DIN_EVEN external terminal (first external terminal) 508, an external DIN_ODD. A terminal (second external terminal) 509 and a DOUT external terminal 108; The semiconductor device 100 transmits signals to and from an external device via the CLK external terminal 104, WEN external terminal 105, REN external terminal 106, ADR external terminal 507, DIN_EVEN external terminal 508, DIN_ODD external terminal 509, and DOUT external terminal 108. Can do. The CLK external terminal 104 is a terminal for inputting a clock to the SRAM 101 in the RAM test mode. The WEN external terminal 105 is a terminal for inputting a write enable signal to the SRAM 101 in the RAM test mode. The REN external terminal 106 is a terminal for inputting a read permission (read enable) signal to the SRAM 101 in the RAM test mode. The ADR external terminal 507 is a terminal for inputting an address signal to the SRAM 101 in the RAM test mode. The DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509 are terminals for inputting data signals to the SRAM 101 in the RAM test mode. The DOUT external terminal 108 is a terminal for outputting data from the SRAM 101 to the outside in the RAM test mode.

  The SRAM 101 includes a CLK terminal 112, a WEN terminal 113, a REN terminal 114, an ADR terminal 115, a DIN terminal 116, and a DOUT terminal 117, and transmits signals to and from other circuits in the semiconductor device 500 via these terminals. Can do. The CLK terminal 112 is a terminal for inputting an operation clock of the SRAM 101. The WEN terminal 113 is a terminal for inputting a write permission (write enable) signal. The REN terminal 114 is a terminal for inputting a read permission (read enable) signal. The ADR terminal 115 is a terminal for inputting an address signal of the SRAM 101, and the SRAM 101 of the third embodiment is assumed to have eight ADR terminals (256 addresses). The DIN terminal 116 is a terminal for inputting write data of the SRAM 101, and the SRAM 101 of the third embodiment has eight DIN terminals. The DOUT terminal 117 is a terminal for outputting data written in the SRAM 101, and the SRAM 101 of the third embodiment has eight DOUT terminals.

  The mode storage unit 103 stores the operation mode of the semiconductor device 500 and transmits the information to peripheral circuits. The operation mode is roughly divided into a normal mode and a test mode that perform normal functions.

  The test circuit 102 changes the operation mode by the mode storage unit 103. The third embodiment has a circuit configuration in the RAM test mode. After shifting to the test mode by the mode storage unit 103, the CLK external terminal 104 is connected to the CLK terminal 112, the WEN external terminal 105 is connected to the WEN terminal 113, the REN external terminal 508 is connected to the REN terminal 114, and the ADR The external terminal 507 (8 bits) is connected to the ADR terminal 115 (8 bits). The DIN_EVEN external terminal 508 is connected to the even-numbered bits of the DIN terminal 116, DIN (0), DIN (2), DIN (4), and DIN (6). The DIN_ODD external terminal 509 is connected to the odd-numbered bits of the DIN terminal 116, DIN (1), DIN (3), DIN (5), and DIN (7).

  Next, a procedure for writing data to the SRAM will be described with reference to FIGS. As the inspection input data input according to the third embodiment, only “00”, “FF”, “55”, and “AA” data are input to the DIN terminal 116 of the SRAM 101. This is because the data holding state of the SRAM can be changed most by writing the data.

  First, an address signal is input to the SRAM 101 from the ADR external terminal 507 to the ADR terminal 115, the write enable signal is asserted, and data is written at the moment when the operation clock of the SRAM 101 changes from High to Low. In the third embodiment, since the data to be written is input from the DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509, it can be input with 2 bits regardless of the number of bits of the DIN terminal 116 of the SRAM.

  Next, a case where (0, 0) is input to the DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509 in the semiconductor device according to the third embodiment will be described with reference to FIG. In this case, “0” is input to the DIN terminal 116 of the SRAM 101 for both even and odd bits, so “00” is input to the DIN terminal 116 of the SRAM 101.

  In addition, a case where (1, 1) is input to the DIN_EVEN external terminal 508 and the DIN_ODD terminal external 509 in the semiconductor device according to the third embodiment will be described with reference to FIG. In this case, since “0” is input to the DIN terminal 116 of the SRAM 101 for both the even and odd bits, “FF” is input to the DIN terminal 116 of the SRAM.

  In addition, the case where (0, 1) is input to the DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509 in the semiconductor device according to the third embodiment will be described with reference to FIG. In this case, since “0” is input to the DIN terminal 116 of the SRAM 101 for both the even and odd bits, “55” is input to the DIN terminal 116 of the SRAM.

  Further, the case where (1, 0) is input to the DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509 in the semiconductor device according to the third embodiment will be described with reference to FIG. In this case, since “0” is input to the DIN terminal 116 of the SRAM 101 for both even and odd bits, “AA” is input to the DIN terminal 116 of the SRAM.

  As described above, according to the third embodiment, a plurality of external terminals including the DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509 that transmit signals to the outside are provided, and the test circuit 302 that tests the SRAM 101. When the memory test mode is selected, the test circuit 302 connects all the even-numbered terminals of the data input terminal 116 of the SRAM 101 and the DIN_EVEN external terminal 508, and connects the data input terminal 116 of the SRAM 101. Since all the odd-numbered terminals are connected to the DIN_ODD external terminal 509, there is an effect that the inspection data can be input through two signal lines regardless of the number of DIN bits of the SRAM.

(Embodiment 4)
A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS.
FIG. 10 shows a configuration of the semiconductor device according to the fourth embodiment of the present invention.

  In FIG. 10, reference numeral 1000 denotes a semiconductor device. The semiconductor device 1000 includes an SRAM 101, a test circuit 102, a mode storage unit 103, a CLK external terminal 104, a WEN external terminal 105, a REN external terminal 106, an ADR external terminal 507, a DIN external terminal 1008, a DOUT_EVEN external terminal (third external terminal). ) 1009 and DOUT_ODD external terminal (fourth external terminal) 1010. The semiconductor device 100 transmits signals to and from an external device via the CLK external terminal 104, the WEN external terminal 105, the REN external terminal 106, the ADR external terminal 507, the DIN external terminal 1008, the DOUT_EVEN external terminal 1009, and the DOUT_ODD external terminal 1010. Can do. The CLK external terminal 104 is a terminal for inputting a clock to the SRAM 101 in the RAM test mode. The WEN external terminal 105 is a terminal for inputting a write enable signal to the SRAM 101 in the RAM test mode. The REN external terminal 106 is a terminal for inputting a read permission (read enable) signal to the SRAM 101 in the RAM test mode. The ADR external terminal 507 is a terminal for inputting an address signal to the SRAM 101 in the RAM test mode. The DIN external terminal 1008 is a terminal for inputting a data signal to the SRAM 101 in the RAM test mode. The DOUT_EVEN external terminal 1009 and the DOUT_ODD external terminal 1010 are terminals for outputting data from the SRAM 101 to the outside in the RAM test mode.

  The SRAM 101 includes a CLK terminal 112, a WEN terminal 113, a REN terminal 114, an ADR terminal 115, a DIN terminal 116, and a DOUT terminal 117, and transmits signals to and from other circuits in the semiconductor device 1000 via the terminal. Can do. The CLK terminal 112 is a terminal for inputting an operation clock of the SRAM 101. The WEN terminal 113 is a terminal for inputting a write permission (write enable) signal. The REN terminal 114 is a terminal for inputting a read permission (read enable) signal. The ADR terminal 115 is a terminal for inputting an address signal of the SRAM 101, and the SRAM 101 of the fourth embodiment is assumed to have eight ADR terminals (256 addresses). The DIN terminal 116 is a terminal for inputting write data of the SRAM 101, and the SRAM 101 of the fourth embodiment has eight DIN terminals. The DOUT terminal 117 is a terminal for outputting data written in the SRAM 101, and the SRAM 101 of the fourth embodiment has eight DOUT terminals.

  The mode storage unit 103 stores the operation mode of the semiconductor device 1000 and transmits the information to peripheral circuits. The operation mode is roughly divided into a normal mode and a test mode that perform normal functions.

  The test circuit 102 changes the operation mode by the mode storage unit 103. The fourth embodiment has a circuit configuration in the RAM test mode. After shifting to the test mode by the mode storage unit 103, the CLK external terminal 104 is connected to the CLK terminal 112, the WEN external terminal 105 is connected to the WEN terminal 113, the REN external terminal 1008 is connected to the REN terminal 114, and the ADR The external terminal 507 (8 bits) is connected to the ADR terminal 115 (8 bits), and the DIN external terminal 1008 is connected to the DIN terminal 116. The DOUT_EVEN external terminal 1009 is connected to the even-numbered bits of the DOUT terminal 116, DOUT (0), DOUT (2), DOUT (4), DOUT (6) and the even-numbered DOUT determination circuit (first data output circuit) 1011. And connected to the determination bit. The DOUT_ODD external terminal 1010 is connected to the odd-numbered bits of the DOUT terminal 116, DOUT (1), DOUT (3), DOUT (5), DOUT (7) and the odd-numbered DOUT determination circuit (second data output circuit) 1012. And connected to the determination bit.

  As shown in FIG. 11, the even-numbered DOUT determination circuit 1011 is an H-output determination circuit 1100 for even-numbered bits DOUT (0), DOUT (2), DOUT (4), and DOUT (6) of the DOUT terminal 116 of the SRAM 101. The determination result of the L output determination circuit 1101 is selected by the first selector 1103, and the determination result is output by the control circuit 1104.

  The odd-numbered DOUT determination circuit 1012 has the same configuration as the even-numbered DOUT determination circuit 1011. The odd-numbered bits of the DOUT terminal 116 of the SRAM 101, DOUT (1), DOUT (3), DOUT (5), DOUT (7 ) Of the H output determination circuit 1100 and the L output determination circuit 1101 are selected by the second selector 1105, and the determination result is output by the control circuit 1104.

  Next, a procedure for reading data into the SRAM will be described with reference to FIGS. As the inspection input data output by the fourth embodiment, only “00”, “FF”, “55”, and “AA” data input from the DIN external terminal 1108 are input to the DIN terminal 116 of the SRAM 101. In contrast, it shall be output. This is because the data holding state of the SRAM can be changed most by writing the data.

  First, an address signal is input to the SRAM 101 from the ADR external terminal 507 to the ADR terminal 115, the read enable signal is asserted, and data is read from the moment when the operation clock of the SRAM 101 changes from High to Low. Since the data read in the fourth embodiment is output via the even-numbered DOUT determination circuit 1011 and the odd-numbered DOUT determination circuit 1102, it is output in 2 bits regardless of the number of DOUT bits in the SRAM. It is assumed that the even DOUT determination circuit 1011 and the odd DOUT determination circuit 1102 of the fourth embodiment have four input terminals. Since the even-numbered DOUT determination circuit 1011 and the odd-numbered DOUT determination circuit 1102 are connected to the even-numbered bit and the odd-numbered bit of the DOUT terminal 116 as described above, the data input to both DOUT determination circuits is “0”, “ 1 ".

Here, the even-numbered DOUT determination circuit 1011 will be described as an example.
As shown in FIG. 11, the even-numbered DOUT determination circuit 1011 includes an H output determination circuit 1100 and an L output determination circuit 1101, and outputs from the H output determination circuit 1100 and the L output determination circuit 1101 to the control circuit 1104. Is selected by the first selector 1103 and output.

  First, in FIG. 12, when “0” is input to the four inputs of the even-numbered DOUT determination circuit 1011, the L output determination circuit 1101 performs a logical sum calculation. The first selector 1103 of the fourth embodiment selects the result of the L output determination circuit 1101 with 0 input and the result of the H output determination circuit 1100 with 1 input. At this time, the first selector 1103 receives “0” from the control circuit 1104 and outputs “0” from the L output determination circuit 1101.

  Next, in FIG. 13, when “1” is input to the four inputs of the even-numbered DOUT determination circuit 1011, the H output determination circuit 1100 performs a logical product calculation. At this time, the first selector 1103 receives “1” from the control circuit 1104 and outputs “1” from the H output determination circuit 1100.

  Next, in FIG. 14, a case where “0” should be input to the four inputs of the even-numbered DOUT determination circuit 1011, but different data is input will be described. As illustrated in FIG. 14, when “1” is input to one of the four inputs of the even-numbered DOUT determination circuit 1011 instead of “0”, the first selector 1103 receives the control signal from the control circuit 1104. When “0” is input, the result of the L output determination circuit 1101 is selected. At that time, “0” is output from the L output determination circuit 1101, but “1” is output. , Can be determined as defective.

  FIG. 15 illustrates a case where “1” should be input to the four inputs of the even-numbered DOUT determination circuit 1011 but different data is input. As shown in FIG. 15, when “0” is input instead of “1” to one of the four inputs of the even-numbered DOUT determination circuit 1011, the first selector 1103 receives the control signal from the control circuit 1104. When “1” is input, the result of the H output determination circuit 1100 is selected. At that time, “1” is output from the H output determination circuit 1100, but “0” is output. , Can be determined as defective.

  As described above, according to the fourth embodiment, the DOUT_EVEN external terminal 1009 and the DOUT_ODD external terminal 1010 are further included, and the test circuit 102 calculates the logical product of the data output from the even-numbered terminals of the data output terminal 116 of the SRAM 101 and An even-numbered DOUT determination circuit 1011 that selects and outputs a logical sum; and an odd-numbered DOUT determination circuit 1012 that selects and outputs a logical product and logical sum of data outputs from odd-numbered terminals of the data output terminal 116 of the SRAM 101; When the memory test mode is selected, the output of the even DOUT determination circuit 1011 is output to the outside from the DOUT_EVEN external terminal 1009, and the output of the odd DOUT determination circuit 1012 is output from the DOUT_ODD external terminal 1010. Because of the SRAM Regardless OUT number of bits, with two signal lines, there is an effect that it is the expected value comparing the test data.

(Embodiment 5)
A semiconductor device according to Embodiment 5 of the present invention will be described with reference to FIGS. The semiconductor device according to the fifth embodiment has the same configuration as that of the third and fourth embodiments, and has two SRAMs each having a different number of columns. The number of columns represents the vertical size (number of columns) of the memory device.

FIG. 16 shows the configuration of the semiconductor device according to the fifth embodiment of the present invention.
In FIG. 16, reference numeral 1600 denotes a semiconductor device. The semiconductor device 1600 includes a first SRAM 101, a second SRAM 1602, a test circuit 102, a mode storage unit 103, a CLK external terminal 104, a WEN external terminal 105, a REN external terminal 106, an ADR external terminal 507, a DIN_EVEN external terminal 508, and a DIN_ODD. An external terminal 509, a DOUT_EVEN external terminal 1009, and a DOUT_ODD external terminal 1010 are provided. The semiconductor device 1600 receives signals from external devices via the CLK external terminal 104, the WEN external terminal 105, the REN external terminal 106, the ADR external terminal 507, the DIN_EVEN external terminal 508, the DIN_ODD terminal 509, the DOUT_EVEN terminal 1009, and the DOUT_ODD terminal 1010. Can be transmitted. The CLK external terminal 104 is a terminal for inputting a clock to the first SRAM 101 and the second SRAM 1602 in the RAM test mode. The WEN external terminal 105 is a terminal for inputting a write enable signal to the first SRAM 101 and the second SRAM 1602 in the RAM test mode. The REN external terminal 106 is a terminal for inputting a read permission (read enable) signal to the first SRAM 101 and the second SRAM 1602 in the RAM test mode. The ADR external terminal 507 is a terminal for inputting an address signal to the first SRAM 101 and the second SRAM 1602 in the RAM test mode. The DIN_EVEN external terminal 508 and the DIN_ODD external terminal 509 are terminals for inputting data signals to the first SRAM 101 and the second SRAM 1602 in the RAM test mode. The DOUT_EVEN external terminal 1009 and the DOUT_ODD external terminal 1010 are terminals for outputting data from the first SRAM 101 and the second SRAM 1602 to the outside in the RAM test mode.

  The first SRAM 101 includes a first CLK terminal 112, a first WEN terminal 113, a first REN terminal 114, a first ADR terminal 115, a first DIN terminal 116, and a first DOUT terminal 117. Through this, signals can be transmitted to other circuits in the semiconductor device 1600. The first CLK terminal 112 is a terminal for inputting an operation clock of the first SRAM 101. The first WEN terminal 113 is a terminal for inputting a write permission (write enable) signal. The first REN terminal 114 is a terminal for inputting a read permission (read enable) signal. The first ADR terminal 115 is a terminal for inputting an address signal of the first SRAM 101, and the first SRAM 101 of the fifth embodiment has eight ADR terminals (256 addresses). . The first DIN terminal 116 is a terminal for inputting write data of the first SRAM 101, and the first SRAM 101 of the fifth embodiment has eight DIN terminals. The first DOUT terminal 117 is a terminal for outputting data written in the first SRAM 101, and the first SRAM 101 of the fifth embodiment has eight DOUT terminals.

  The second SRAM 1602 includes a second CLK terminal 1612, a second WEN terminal 1613, a second REN terminal 1614, a second ADR terminal 1615, a second DIN terminal 1616, and a second DOUT terminal 1617. Through this, signals can be transmitted to other circuits in the semiconductor device 1600. The second CLK terminal 1612 is a terminal for inputting an operation clock of the second SRAM 1602. The second WEN terminal 1613 is a terminal for inputting a write enable (write enable) signal. The second REN terminal 1614 is a terminal for inputting a read permission (read enable) signal. The second ADR terminal 1615 is a terminal for inputting an address signal of the second SRAM 1602. The second SRAM 1602 of the fifth embodiment is assumed to have eight ADR terminals (256 addresses). The second DIN terminal 1616 is a terminal for inputting the write data of the second SRAM 1602, and the second SRAM 1602 of the fifth embodiment has eight DIN terminals. The second DOUT terminal 1617 is a terminal for outputting data written in the second SRAM 1602, and the second SRAM 1602 of the fifth embodiment has eight DOUT terminals.

  The mode storage unit 103 stores the operation mode of the semiconductor device 1600 and transmits the information to peripheral circuits. The operation mode is roughly divided into a normal mode and a test mode that perform normal functions.

  The first test circuit 102 and the second test circuit 1621 change the operation mode by the mode storage unit 103. The fifth embodiment has a circuit configuration in the RAM test mode. After shifting to the test mode by the mode storage unit 103, the CLK external terminal 104 is connected to the first CLK terminal 112 and the second CLK terminal 1612, and the WEN external terminal 105 is connected to the first WEN terminal 113 and the second CLK terminal. 2, the REN external terminal 106 is connected to the first REN terminal 114 and the second REN terminal 1614, and the ADR external terminal 507 (8 bits) is connected to the first ADR terminal 115 (8 bits). And the second ADR terminal 1615 (8 bits) through the address conversion circuit 1618. The DIN_EVEN external terminal 508 is connected to the even-numbered bits of the first DIN terminal 116 and the second DIN terminal 1616. The DIN_ODD external terminal 509 is connected to the odd-numbered bits of the first DIN terminal 116 and the second DIN terminal 1616. The DOUT_EVEN external terminal 1009 connects the even-numbered bits of the first DOUT terminal 117 and the second DOUT terminal 1617 and the even-numbered DOUT determination circuit 1619, and is connected to the determination bits. The DOUT_ODD external terminal 1010 connects the odd-numbered bits of the first DOUT terminal 117 and the second DOUT terminal 1617 and the odd-numbered DOUT determination circuit 1620, and is connected to the determination bits.

  Next, a procedure for writing data to the SRAM will be described with reference to FIGS. The inspection input data input according to the fifth embodiment is supplied to the first DIN terminal 116 included in the first SRAM 101 and the second DIN terminal 1616 included in the second SRAM 1602 shown in FIG. Only data of “00”, “FF”, “55”, and “AA” are input. This is because the data holding state of the SRAM can be changed most by writing the data.

  FIG. 17 is a diagram illustrating data input to the first SRAM 101 in the semiconductor device according to the fifth embodiment of the present invention. FIG. 18 is a diagram illustrating data input to the first SRAM 101 in the semiconductor device according to the fifth embodiment of the present invention. FIG. 19 is a diagram showing data input to the second SRAM 1602, and FIG. 19 is input to the second SRAM 1602 when the address conversion circuit is used in the semiconductor device according to the fifth embodiment of the present invention. It is the figure which showed data.

  Data writing to the first SRAM 101 shown in FIG. 16 is the same as that in the third embodiment. At that time, the write data to the first SRAM 101 with the column number “8” is incremented by 1 sequentially from address 0 as shown in FIG. 17 and simultaneously “00” and “FF” are written, and after writing eight addresses, Let it be reversed. On the other hand, as shown in FIG. 18, the write data to the second SRAM 1602 with the number of columns “4” is incremented by 1 in order from address 0, and simultaneously “00” and “FF” are written and written for four addresses. Later, it will be inverted. At this time, if the ADR external terminal 507 is connected to the second ADR terminal 1615 as it is, the intended inspection data cannot be input to the second SRAM 1602.

  Therefore, the address of the second SRAM 1602 is written so that four addresses are skipped after writing four addresses as shown in FIG. 19, four addresses are written, and then the data of the skipped four addresses is written. An address conversion circuit 1618 for conversion is provided. As a result, even when there are a plurality of SRAMs having different numbers of columns, all the connections to the DIN terminal and DOUT terminal can use the same configuration as that of the third and fourth embodiments.

  As described above, according to the fifth embodiment, the first SRAM 101 and the second SRAM 1602 are provided, and the first and second test circuits 102 and 1621 are all when the memory test mode is selected. The even-numbered terminals of the data input terminals 116 and 1616 of the memory section are connected to the DIN_EVEN external terminal 508, and the odd-numbered terminals of the data input terminals 116 and 1616 of all the memory sections are connected to the DIN_ODD external terminal 509. The even-numbered terminals of the data output terminals 117 and 1617 of the memory section are connected to the DOUT_EVEN external terminal 1009, and the odd-numbered terminals of the data output terminals 117 and 1617 of all the memory sections are connected to the DOUT_ODD external terminal 1010. Therefore, the two signal lines are used for detection regardless of the number of DIN bits in the SRAM. Can enter use data, regardless of the number of bits DOUT of SRAM, there is an effect that on two signal lines can expected value comparison of the test data.

  Further, according to the fifth embodiment, the second SRAM 1602 having a different number of columns from the first SRAM 101 is provided, and the test circuit 102 converts the address input of the second SRAM 1602 according to the number of columns. Since 1618 is further provided, even when a plurality of SRAMs having different numbers of columns are provided, there is an effect that the memory can be tested with a small number of external terminals.

  The present invention is useful as a system LSI including a test circuit for testing the operation of the mounted RAM.

The figure which shows the structure of the semiconductor device concerning Embodiment 1 of this invention. Schematic flowchart of writing in the memory device of the semiconductor device according to the first embodiment of the present invention. The figure which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. Schematic flowchart of writing in the memory device of the semiconductor device according to the second embodiment of the present invention. The figure which shows the structure of the semiconductor device concerning Embodiment 3 of this invention. The figure which shows the input data of SRAM when 00 is input into DIN_EVEN and DIN_ODD terminal in the semiconductor device concerning Embodiment 3 of this invention. The figure which shows the input data of SRAM when 11 is input into DIN_EVEN and DIN_ODD terminal in the semiconductor device concerning Embodiment 3 of this invention. The figure which shows the input data of SRAM when inputting 01 into DIN_EVEN and DIN_ODD terminal in the semiconductor device concerning Embodiment 3 of this invention. The figure which shows the input data of SRAM when 10 is input into DIN_EVEN and DIN_ODD terminal in the semiconductor device concerning Embodiment 3 of this invention. The figure which shows the structure of the semiconductor device concerning Embodiment 4 of this invention. The figure which shows the circuit structure of the DOUT determination circuit in the semiconductor device concerning Embodiment 4 of this invention. The figure which shows the determination of the DOUT determination circuit when the normal data 00 is output from SRAM in the semiconductor device concerning Embodiment 4 of this invention. The figure which shows the determination of the DOUT determination circuit when the normal data FF is output from SRAM in the semiconductor device concerning Embodiment 4 of this invention. The figure which shows the determination of the DOUT determination circuit when the abnormal data of 00 is output from SRAM in the semiconductor device concerning Embodiment 4 of this invention. The figure which shows the determination of the DOUT determination circuit when the abnormal data of FF is output from SRAM in the semiconductor device concerning Embodiment 4 of this invention. The figure which shows the structure of the semiconductor device concerning Embodiment 5 of this invention. The figure which shows the ADR data and DIN data which are input with respect to SRAM with 8 columns in the semiconductor device concerning Embodiment 5 of this invention. The figure which shows the ADR data and DIN data which are input with respect to SRAM with 4 columns in the semiconductor device concerning Embodiment 5 of this invention The figure which shows the ADR data and DIN data which are input with respect to SRAM of the number of columns 4 at the time of using the address translation circuit in the semiconductor device concerning Embodiment 5 of this invention. The figure which shows the structure of the semiconductor device of a prior art example

Explanation of symbols

100, 300, 500, 1000, 1600 Semiconductor device 101 SRAM
102, 302 Test circuit 103 Mode storage unit 104 CLK external terminal 105 WEN external terminal 106 REN external terminal 107 ADR / DIN external terminal 108 DOUT external terminal 109 Clock control circuit 110 First latch circuit 111 Second latch circuit 112 CLK terminal 113 WEN terminal 114 REN terminal 115 ADR terminal 116 DIN terminal 117 DOUT terminal 118 Package selection external terminal 507 ADR external terminal 508 DIN_EVEN terminal 509 DIN_ODD terminal 1008 DIN external terminal 1009 DOUT_EVEN terminal 1010 DOUT_ODD terminal 1011 Odd DOUT determination circuit 1012 1100 H output determination circuit 1101 L output determination circuit 1103, 1104 selector 1602 SRAM
1612 CLK terminal 1613 WEN terminal 1614 REN terminal 1615 ADR terminal 1616 DIN terminal 1617 DOUT terminal 1618 Address conversion circuit 1619 Even DOUT determination circuit 1620 Odd DOUT determination circuit 1621 Test circuit

Claims (7)

An electrically rewritable volatile memory section;
An operation mode storage unit for storing a plurality of operation modes including a memory test mode for testing the operation of the memory unit;
A test circuit for testing the memory unit;
A plurality of external terminals for transmitting signals with the outside,
The external terminal has a WEN external terminal connected to the write enable terminal of the memory unit in the memory test mode, and an ADR / DIN external terminal for inputting an address signal and a data signal of the memory unit in the memory test mode,
The test circuit includes a latch circuit that temporarily stores an address signal and a data signal input from the ADR / DIN external terminal in the memory test mode.
A semiconductor device. The semiconductor device according to claim 1,
The latch circuit is composed of a shift register.
A semiconductor device. An electrically rewritable volatile memory section;
An operation mode storage unit for storing a plurality of operation modes including a memory test mode for testing the operation of the memory unit;
A first external terminal and a second external terminal for transmitting signals with the outside;
A test circuit for testing the memory unit,
When the memory test mode is selected, all even-numbered terminals of the data input terminals of the memory section are connected to the first external terminals, and all odd-numbered data input terminals of the memory section are connected. Connecting the second terminal and the second external terminal,
A semiconductor device. The semiconductor device according to claim 3.
Further comprising a third external terminal and a fourth external terminal for transmitting a signal with the outside,
The test circuit includes:
A first data output circuit that selects and outputs a logical product and a logical sum of data outputs from even-numbered terminals of the data output terminals of the memory unit;
A second data output circuit for selecting and outputting a logical product and a logical sum of data outputs from odd-numbered terminals of the data output terminals of the memory unit;
When the memory test mode is selected, the output of the first data output circuit is output to the outside from the third external terminal, and the output of the second data output circuit is output to the fourth external Output from the terminal to the outside,
A semiconductor device. The semiconductor device according to claim 4.
Including one or more memory units;
When the memory test mode is selected, all the even-numbered terminals of the data input terminals of the memory section and the first external terminal are connected, and all the odd-numbered terminals of the data input terminals of the memory section are connected. Connecting the second external terminal, connecting all even-numbered terminals of the data output terminals of the memory unit and the first data output circuit, and connecting all odd-numbered terminals of the data output terminals of the memory unit; Connecting the terminal and the second data output circuit;
A semiconductor device. The semiconductor device according to claim 5.
A second memory unit having a different number of columns from the memory unit;
The test circuit further includes an address conversion circuit that converts an address input of the second memory unit based on the number of columns.
A semiconductor device. In the semiconductor device according to claim 1,
A package selection external terminal for inputting package information;
When the number of external terminals connected to the pins of the package is larger than the number of input / output terminals of the memory unit, and in the memory test mode, all the input / output terminals of the memory unit are directly connected to a plurality of predetermined external terminals. Switch,
A semiconductor device.

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