JP2005038526A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem associated with an increase in the wiring area which becomes a load for a chip layout when a fuse box is provided external to a RAM so as to realize a redundant RAM where the fuse and the RAM main body are separated and wiring of redundant relief address data wires are required between the RAM main body and the fuse box. <P>SOLUTION: A multiplexer 103 is provided to receive normal address signals and redundant relief address signals and to selectively output these signals and address terminals 104 of a redundant RAM101 and the input terminals of the redundant relief address signals are commonly used. Thus, the signal wiring for the dedicated redundant relief address signals between the redundant RAM101 and the fuse box 102 is eliminated, the area of an LSI chip is reduced and design efficiency is improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit configuration of a semiconductor memory device that suppresses a wiring area in a system LSI on which a memory having a redundant function is mounted and enables a redundant function test to be easily performed.

  A configuration of a conventional semiconductor memory device is shown in FIG. In FIG. 18, 201 is a redundant RAM, 202 is a fuse box, 204 is an address terminal, 205 is a data input terminal, 206 is a write control terminal, 207 is a clock terminal, 208 is a fuse information input terminal, 209 is a data output terminal, Reference numeral 210 denotes a fuse box reset terminal, and 211 denotes a fuse information output terminal.

  FIG. 19 shows a timing chart of the conventional semiconductor memory device.

  The configuration and operation of this conventional semiconductor memory device will be described with reference to FIGS.

A redundant RAM 201 having a redundant relief circuit obtains redundant relief address information for switching a failed memory cell to a relief memory cell from the fuse information input terminal 208 when a normal memory cell has failed, and performs a redundant relief operation. It is configured to do. Redundant relief address information is generated from a fuse box 202 in which a plurality of fuse circuits are arranged in a concentrated manner. The fuse box 202 includes a fuse circuit and a reset signal terminal 210 for resetting the fuse circuit. When the fuse circuit is reset by the reset terminal 210, multi-value information is sent from the fuse information output terminal 211 depending on the cutting state of an arbitrary fuse. Output. The amount of information value of the redundant relief address is determined by the redundant memory array scale and the failure relief configuration, but since it is multivalued, the number of information signal dedicated lines is plural. Therefore, a plurality of redundant relief address signal dedicated lines are connected to the fuse information input terminal 208 of the redundant RAM 201 from the fuse information output terminal 211 of the fuse box 202.
Japanese Patent Laid-Open No. 11-134870 (page 3, FIG. 2)

  However, in the above conventional example, the redundant RAM 201 and the fuse box 202 are usually arranged separately on the LSI chip, and there are a plurality of information signal lines between the fuse box 202 and the redundant RAM 201 and long wiring. The routing of the signal wiring causes a problem of increasing the area of the LSI chip. In particular, in recent years, a plurality of redundant RAMs typified by SRAM and the like are often mounted, and there is a problem that a fuse box is arranged for each redundant RAM, and routing of signal wiring between them facilitates an increase in chip area. . In addition, a means for quickly confirming signal line disconnection or short-circuit between the redundant RAM 201 and the fuse box 202 has not been established, and signal line short-circuit or disconnection can be confirmed until the entire memory space is inspected. Therefore, the inspection time was increased.

  In order to solve the above problems, an object of the present invention is to provide a semiconductor memory device capable of reducing signal lines between a redundant RAM and redundant relief address signal setting means such as a fuse box.

  According to a first aspect of the present invention, there is provided a semiconductor memory device having an address input terminal for inputting a normal address signal, a RAM having a redundancy repair function for repairing a failed memory cell based on the redundancy repair address signal, and a RAM. Redundant relief address signal setting means for outputting a redundant relief address signal to be applied, a normal address signal and a redundant relief address signal are input, and in the redundancy relief address information fetch mode, the redundancy relief address signal is output to the address input terminal, and the redundancy relief address is output. First selection means for outputting a normal address signal to an address input terminal when not in the information capture mode, and latching the redundant relief address signal input to the address input terminal in the redundant relief address information capture mode in the RAM The latch circuit is provided.

  According to the first aspect of the present invention, the first selecting means for inputting and selecting and outputting the normal address signal and the redundant relief address signal is provided, and the address input terminal of the RAM is also used as the input terminal of the redundant relief address signal. Therefore, it is possible to reduce the signal line dedicated to the redundant relief address signal between the RAM and the redundant relief address signal setting means, and it is possible to reduce the chip area.

  According to a second aspect of the present invention, there is provided a semiconductor memory device having a data input terminal for inputting a normal data signal and having a redundancy repair function for repairing a failed memory cell based on a redundancy repair address signal, and the RAM. Redundant relief address signal setting means for outputting a redundant relief address signal, a normal data signal and a redundant relief address signal are input, and a redundant relief address signal is output to the data input terminal in the redundant relief address information capture mode, thereby providing redundant relief address information. A latch for latching a redundant relief address signal input to the data input terminal in the redundant relief address information capture mode; and a first selection means for outputting a normal data signal to the data input terminal when not in the capture mode. A circuit is provided.

  According to the second aspect of the present invention, the first selecting means for inputting and selecting and outputting the normal data signal and the redundant relief address signal is provided, and the data input terminal of the RAM is also used as the input terminal of the redundant relief address signal. Therefore, it is possible to reduce the signal line dedicated to the redundant relief address signal between the RAM and the redundant relief address signal setting means, and it is possible to reduce the chip area.

  According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the redundancy relief address signal setting means is a redundancy set in accordance with a cut / non-cut state of a built-in fuse. The fuse box is provided with a plurality of fuse circuits for outputting a relief address signal.

  According to the configuration of the third aspect, the same effect as that of the first or second aspect can be obtained.

  According to a fourth aspect of the present invention, in the semiconductor memory device of the third aspect, the fuse box includes a reset terminal for resetting a plurality of fuse circuits, and resets the fuse circuit by giving a reset signal to the reset terminal. After the reset, the fuse circuit outputs a redundant relief address signal, and the first selection means and the RAM latch circuit are set to the redundant relief address information fetch mode.

  According to the configuration of the fourth aspect, the same effect as that of the third aspect can be obtained.

  The semiconductor memory device according to claim 5 is the semiconductor memory device according to claim 3, wherein the fuse box generates a reset terminal for inputting an external reset signal, and two one-shot pulses serially connected to the reset terminal. A first-stage one-shot pulse generation circuit connected in series is provided as a reset signal to a plurality of fuse circuits, and the output pulse of the second-stage one-shot pulse generation circuit is redundantly relieved. It is characterized in that it is output to the first selection means and the RAM as a signal indicating that it is an address information fetch mode.

  According to the fifth aspect of the present invention, in addition to the effect of the third aspect, it is possible to generate the reset signal of the fuse circuit and the signal indicating the redundant relief address information take-in mode by giving the external reset signal. Only with this, it becomes possible to perform a redundant relief operation.

  The semiconductor memory device according to claim 6 is the semiconductor memory device according to any one of claims 1 to 5, wherein the RAM has a data output terminal, and a normal data signal and a latch circuit are provided inside the RAM. The latched redundancy relief address signal is input, the redundancy relief address signal is output to the data output terminal in the redundancy relief address information capture mode, and the normal data signal is output to the data output terminal in other than the redundancy relief address information capture mode. A second selection means is provided.

  According to the sixth aspect of the present invention, in addition to the effect of any one of the first to fifth aspects, the redundant relief address signal is output from the data output terminal to confirm whether the redundant relief address signal is correctly input. Thus, it is possible to inspect whether there is no error in the redundant relief address signal or whether there is a failure in the wiring path.

  According to a seventh aspect of the present invention, in the semiconductor memory device according to the third aspect, the fuse box has a third selection means for inputting a test redundant relief address signal and an output signal of the fuse circuit from the outside. And the third selecting means selectively outputs the test redundant relief address signal in the test mode, and selectively outputs the output signal of the fuse circuit in other than the test mode.

  According to the configuration of the seventh aspect, since the fuse box can output the test redundant relief address signal inputted externally in the test mode, the redundancy relief function can be obtained by setting the test mode before cutting the fuse of the fuse circuit. It becomes possible to inspect about.

  The semiconductor memory device according to claim 8 is the semiconductor memory device according to claim 1 or 2, wherein the redundancy relief address signal setting means is a redundancy relief address generation circuit that generates a redundancy relief address signal without using a fuse. It is characterized by being.

  According to the configuration of the eighth aspect, the same effect as that of the first or second aspect can be obtained.

  According to a ninth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of the RAM according to the first or second aspect and a first selection unit corresponding thereto, wherein the built-in fuse is in a cut / non-cut state. A plurality of fuse circuit groups that output redundant relief address signals set in accordance with the RAM are provided corresponding to each RAM, and one RAM that is arbitrarily selected from the outputs of the plurality of fuse circuit groups by a RAM selection signal And a fuse box provided with second selection means for selecting the output of the fuse circuit group corresponding to and outputting to the redundant relief address signal output terminal, the first selection corresponding to the redundant relief address signal output terminal and each RAM The redundant relief address signal input terminal is connected to the RAM selected by the selection signal and the first selection means corresponding thereto is connected to the redundant relief address. So that to information capture mode.

  According to the ninth aspect of the present invention, in the configuration including a plurality of RAMs, the normal address signal or the normal data signal and the redundant relief address signal are input and selectively output as in the first or second aspect. The redundant relief between each RAM and the fuse box which is the redundant relief address signal setting means is provided by providing one selection means and sharing the address input terminal or the data input terminal of each RAM as the redundant relief address signal input terminal. Signal lines dedicated to address signals can be reduced, and the chip area can be reduced. In addition, a fuse circuit group for setting redundant relief addresses of a plurality of RAMs is installed in the fuse box, and the second selection means can select and output a redundant relief address signal for an arbitrary RAM. Redundant relief addresses of a plurality of RAMs can be supplied from a box through a set of bus lines, and signal wiring in the LSI chip can be reduced.

  The semiconductor memory device according to claim 10 is the semiconductor memory device according to claim 9, wherein there are n RAMs (n is a plurality), and the fuse box is provided with a reset terminal for inputting an external reset signal and a reset terminal. (N + 1) one-shot pulse generation circuits connected in series are provided, and an output pulse of the first-stage one-shot pulse generation circuit connected in serial is given as a reset signal to a plurality of fuse circuit groups. The RAM selected by the selection signal and the first selection corresponding to the output pulse of the one-shot pulse generation circuit of the second and subsequent stages as a signal indicating the redundant relief address information fetch mode corresponding to each RAM Output to the means.

  According to the structure of claim 10, in addition to the effect of claim 9, by providing an external reset signal, it is possible to generate a reset signal for the fuse circuit group and a signal indicating the redundant relief address information fetch mode, and the external reset A redundant relief operation can be performed only by a signal.

  As described above, according to the present invention, signal wiring between the redundant RAM and the fuse box can be reduced, and the chip area can be reduced and the design efficiency at the time of chip design can be improved. In addition, it is possible to provide a semiconductor memory device that facilitates the inspection of the redundancy relief function and the connection inspection of the redundancy relief address signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an overall configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, 101 is a redundant RAM having a redundant relief circuit, 102 is a fuse box, 103 is a multiplexer, 104 is an address terminal, 105 is a data input terminal, 106 is a write control terminal, 107 is a clock terminal, and 108 is a redundant setting. Reference numeral 109 denotes a data output terminal, 110 denotes a reset terminal of the fuse box, 111 denotes a fuse information output terminal, and 117 denotes a logic circuit that generates a normal address signal to be supplied to the redundant RAM 101.

  In the first embodiment, in the redundant RAM 101, the address terminal 104 for inputting a normal address signal is also used as an input terminal for a redundant relief address signal output from the fuse information output terminal 111 of the fuse box 102. The fuse information output terminal 111 of the fuse box 102 and the normal address signal of the logic circuit 117 are connected to the multiplexer 103, and the output of the multiplexer 103 is connected to the address terminal 104 of the redundant RAM 101. The multiplexer 103 selects a redundant relief address signal output from the fuse box 102 when a control signal (not shown) input thereto indicates the redundant relief address information fetch mode, and outputs from the logic circuit 117 otherwise. The normal address signal to be output is selected and output.

  In many cases, the logic circuit 117 for generating the normal address signal and the redundant RAM 101 are separated and arranged far away, and the fuse box 102 and the redundant RAM 101 are also separated and arranged far away. The multiplexer 103 is arranged as close as possible to the logic circuit 117, and the signal wiring from the output of the multiplexer 103 to the address terminal 104 of the redundant RAM 101 is arranged as a long wiring.

  FIG. 2 is a configuration diagram of the redundant RAM 101. The redundant RAM 101 includes an address terminal 104, a clock terminal 107, a redundant setting terminal 108, and a latch circuit 112 that latches a redundant relief address signal. The latch circuit 112 includes an AND circuit 113 that decodes a clock signal from the clock terminal 107 and an input signal from the redundancy setting terminal 108 to generate a latch pulse, and a latch flip-flop circuit (hereinafter referred to as FF) 114. Yes. The latch output holding the redundancy relief address data of the latch circuit 112 is configured to rescue the failed memory cell by the redundancy relief circuit. The redundant repair circuit is a memory provided in the redundant RAM 101 and repairing a defective memory.

  FIG. 3 is a configuration diagram of the fuse box 102. The fuse box 102 includes a plurality of fuse circuits 115 each including a fuse 116 and a latch transistor, and a reset signal for latching each fuse circuit 115 is supplied from a reset terminal 110.

  Further, the operation of the semiconductor memory device according to the first embodiment will be described with reference to FIG. FIG. 4 is an operation timing chart of the semiconductor memory device according to the first embodiment.

  As an initial setting, any fuse 116 in the fuse box 102 is cut according to the redundant relief address information. An H level reset signal is input from the reset terminal 110 of the fuse box 102, the fuse circuit is reset, and after releasing the reset, a desired redundant relief address signal is output from the fuse information output terminal 111.

  The redundancy setting terminal 108 of the redundant RAM 101 is a control signal input terminal for controlling the redundancy relief address signal of the redundancy RAM to be held in the latch circuit 112, and the redundancy setting terminal 108 is set to H (high) level (redundancy relief address information capturing mode). As a result, the FF circuit 114 in the latch circuit 112 latches the redundant relief address signal at the rising edge of the clock signal, and latches the redundant relief address signal even after the redundancy setting terminal 108 returns to the L (low) level. The circuit 112 continues to hold, and the redundant relief operation of the redundant RAM 101 is continued. In this state, normal memory operation is performed.

  Note that the same signal as the input signal of the redundancy setting terminal 108 can be used as the control signal of the multiplexer 103. The multiplexer 103 is a circuit that selects either the redundant relief address signal of the fuse box 102 or the input signal to the redundant RAM from the normal logic circuit 117 and outputs the selected signal to the redundant RAM 101. The redundant RAM 101 receives the redundant relief address signal. At the same time, the redundancy setting terminal 108 is set to H level.

  As described above, according to the first embodiment, the multiplexer 103 for inputting and selecting and outputting the normal address signal and the redundant relief address signal is provided, and the address terminal 104 is also used as the redundant relief address signal input terminal. Therefore, the signal wiring dedicated to the redundant relief address signal between the redundant RAM 101 and the fuse box 102 can be reduced, the area of the LSI chip can be reduced, and the design efficiency at the time of chip design can be improved.

(Embodiment 2)
FIG. 5 is a configuration diagram of a redundant RAM of the semiconductor memory device according to the second embodiment of the present invention. In the second embodiment, the redundant RAM 121 in FIG. 5 is used instead of the redundant RAM 101 in the first embodiment, and the other configurations are the same as those in the first embodiment. The redundant RAM 121 includes an address terminal 104, a clock terminal 107, a redundant setting terminal 108, and a latch circuit 112 that latches a redundant relief address signal. The latch circuit 112 includes an AND circuit 113 that decodes a clock signal from the clock terminal 107 and an input signal from the redundancy setting terminal 108 to generate a latch pulse, and a latch flip-flop circuit (hereinafter referred to as FF) 114. Yes. The above configuration is the same as that of the redundant RAM 101 of the first embodiment.

  Further, in the redundant RAM 121 of the second embodiment, the output terminal selector 122 is connected to the data output terminal 109, and the output terminal selector 122 is a normal data output or latch data of the latch circuit 112 according to a signal of the redundancy setting terminal 108. One of the redundant relief address data is selectively output. That is, when the signal of the redundancy setting terminal 108 indicates the redundancy relief address information fetch mode, the redundancy relief address data that is the latch data of the latch circuit 112 is selectively output, and otherwise the normal data output is selectively output.

  According to the second embodiment, in addition to the effects of the first embodiment, when the redundant relief address data is taken into the redundant RAM 121, it becomes possible to output redundant relief address data from the data output terminal 109 at the same time. By inspecting the value, it is possible to inspect and diagnose whether there is an error in the redundant relief address data or whether there is a failure in the wiring path.

(Embodiment 3)
FIG. 6 is a configuration diagram of the fuse box of the semiconductor memory device according to the third embodiment of the present invention. In the third embodiment, the fuse box 131 of FIG. 6 is used instead of the fuse box 102 in the first embodiment, and the other configurations are the same as those of the first embodiment. The fuse box 131 includes a pulse generation circuit 132 in addition to a plurality of fuse circuits 115 similar to those in FIG. The reset terminal 110 is input to the pulse generation circuit 132. The pulse generation circuit 132 is configured by serially connecting the one-shot pulse generation circuit in two stages, and the output pulse of the first-stage one-shot pulse generation circuit is received. It is configured to output as a reset signal 134 of the fuse circuit 115 and to output the output pulse of the second-stage one-shot pulse generation circuit from the redundancy setting control terminal 133. The output pulse output from the redundancy setting control terminal 133 is a redundancy setting signal (redundancy relief address information acquisition mode signal) indicating the redundancy relief address information acquisition mode, and is input to the multiplexer 103 as its control signal. At the same time, it is input to the redundancy setting terminal 108 of the redundancy RAM 101.

  Further, the operation of the semiconductor memory device according to the third embodiment will be described with reference to FIG. FIG. 7 is an operation timing chart of the semiconductor memory device according to the third embodiment.

  An H level reset signal is input from the reset terminal 110, and the reset signal 134 of the fuse circuit 115 is generated by the first-stage pulse generation circuit of the first stage of the pulse generation circuit 132. Thereafter, a redundancy setting signal is generated by the second-stage one-shot pulse generation circuit.

  According to the third embodiment, in addition to the effects of the first embodiment, the control signal input to the redundancy setting terminal 108 of the redundant RAM 101 and the control signal of the multiplexer 103 and the control signal of the redundant RAM 101 which are required to be externally input in the first embodiment are externally transmitted. It is possible to generate without supplying more.

  The same effect can be obtained even if the fuse box 131 of the third embodiment is similarly applied to the semiconductor memory device of the second embodiment.

(Embodiment 4)
FIG. 8 is a configuration diagram of the semiconductor memory device according to the fourth embodiment of the present invention. In the fourth embodiment, the redundant relief address generation circuit 141 of FIG. 8 is used instead of the fuse box 102 in the first embodiment, and the other configuration is the same as that of the first embodiment. The redundant relief address generation circuit 141 is not configured to use a fuse or the like, and has a configuration in which a redundant relief address signal is held and generated by a plurality of flip-flops, latch circuits, nonvolatile memories, and the like. The output of the multiplexer 103 is connected to the address terminal 104 of the redundant RAM 101, and a normal address signal generated from the logic circuit 117 and a redundant relief address signal generated from the redundant relief address generation circuit 141 and output from the output terminal 142 thereof. Are selected by the multiplexer 103 in the same manner as in the first embodiment and input to the redundant RAM 101. In many cases, the logic circuit 117 that generates the normal address signal to be supplied to the RAM 101 and the redundant RAM 101 are separated and arranged far away, but the multiplexer 103 is arranged as close as possible to the logic circuit 117, and the redundant RAM 101 is output from the output of the multiplexer 103. The signal wirings to the address terminals 104 are arranged so as to be long wirings.

  According to the fourth embodiment as described above, the signal wiring between the redundant RAM 101 and the redundant relief address generation circuit 141 can be reduced, and the area of the LSI chip can be reduced and the design efficiency at the time of chip design can be improved.

  The same effect can be obtained even if the redundant relief address generation circuit 141 of the fourth embodiment is similarly applied to the semiconductor memory device of the second embodiment.

(Embodiment 5)
FIG. 9 is an overall configuration diagram of the semiconductor memory device according to the fifth embodiment of the present invention. In FIG. 9, reference numeral 151 denotes a redundant RAM, 118 denotes a logic circuit for generating a normal data signal to be given to the redundant RAM 151, and the other components similar to those in FIG.

  In the fifth embodiment, in the redundant RAM 151, the data input terminal 105 for inputting a normal data signal is also used as an input terminal for a redundant relief address signal output from the fuse information output terminal 111 of the fuse box 102. The fuse information output terminal 111 of the fuse box 102 and the normal data signal of the logic circuit 118 are connected to the multiplexer 103, and the output of the multiplexer 103 is connected to the data input terminal 105 of the redundant RAM 151. The multiplexer 103 selects a redundant relief address signal output from the fuse box 102 when a control signal (not shown) input thereto indicates the redundant relief address information capture mode, and outputs from the logic circuit 118 otherwise. Select the normal data signal to be output. When the redundant RAM 151, the logic circuit 118, and the fuse box 102 are arranged separately, the multiplexer 103 is arranged in the vicinity of the logic circuit 118 and the fuse box 102, and the output of the multiplexer 103 is sent to the data input terminal 105 of the redundant RAM 151. The signal wirings are arranged so as to be long wirings.

  FIG. 10 is a configuration diagram of the redundant RAM 151. The redundant RAM 151 is provided with a latch circuit 112 similar to that in FIG. 2 at the data input terminal 105, and when the redundant relief address information fetch mode is set by the control signal input from the redundancy setting terminal 108, the data input terminal A memory which latches a redundant relief address signal from 105 and performs a redundant relief operation in accordance with the redundant relief address signal.

  According to the fifth embodiment, the redundant RAM 151 and the fuse box 102 are the same as the first embodiment except that the data input terminal 105 can be used also as the redundant relief address signal input terminal instead of the address terminal 104. The signal wiring between them can be reduced, the area of the LSI chip can be reduced, and the design efficiency at the time of chip design can be improved.

  In the second to fourth embodiments, similarly, instead of the address terminal 104, the data input terminal 105 may also be used as the redundant relief address signal input terminal.

(Embodiment 6)
FIG. 11 is an overall configuration diagram of the semiconductor memory device according to the sixth embodiment of the present invention. In the sixth embodiment, the fuse box 160 is used in place of the fuse box 102 in the first embodiment, and other configurations are the same as those in the first embodiment. The fuse information output terminal 111 of the fuse box 160 and the normal address signal of the logic circuit 117 are connected to the multiplexer 103. In many cases, the logic circuit 117 for generating a normal address signal to be supplied to the redundant RAM 101 and the redundant RAM 101 are separated and disposed far away. At that time, the multiplexer 103 is arranged as close as possible to the logic circuit 117 and the fuse box 160, and is arranged so that the signal wiring from the output of the multiplexer 103 to the address terminal 104 of the redundant RAM 101 becomes a long wiring.

  FIG. 12 is a configuration diagram of the fuse box 160. A plurality of fuse circuits 115, a reset terminal 110, a fuse information output terminal 111, a multiplexer 162 that selects and outputs a fuse circuit output signal and a signal of the test terminal 163, and a test control terminal 161 that controls the multiplexer 162 are the same as in FIG. I have. That is, the fuse box 160 has a configuration in which a multiplexer 162, a test control terminal 161, and a test terminal 163 are added to the fuse box 102 of FIG. This additional configuration can be similarly applied to embodiments using the fuse box 102 of FIG. 3 or the fuse box 131 of FIG. 6 other than the first embodiment.

  According to the sixth embodiment, in addition to the effects of the first embodiment, by using the fuse box 160 of FIG. 12, the test control terminal 161 is connected by an external test circuit before the fuses of the plurality of fuse circuits 115 are cut. Is supplied with a test mode signal (H level signal) so that the multiplexer 162 selects and outputs the signal of the test terminal 163, and a redundant relief address signal for test is input to the test terminal 163, whereby the fuse information output terminal Since a redundant relief address signal for testing can be output from 111, the redundant relief function can be inspected before the fuse is cut. When no test mode signal is input to the test control terminal 161, the multiplexer 162 selects a signal from the fuse circuit 115 and outputs it to the fuse information output terminal 111.

(Embodiment 7)
FIG. 13 is an overall configuration diagram of the semiconductor memory device according to the seventh embodiment of the present invention. In the seventh embodiment, a plurality of memories are provided, and one fuse box is provided for the plurality of memories. For example, in FIG. 13, one fuse box 170 is provided for the first and second redundant RAMs 101A and 101B. The multiplexer 103A connected to the address terminal 104A of the redundant RAM 101A receives the normal address signal A input from the logic circuit 117A and the redundant relief address signal from the fuse information output terminal 111 of the fuse box 170. Similarly, the normal address signal B input from the logic circuit 117B and the redundant relief address signal from the fuse information output terminal 111 of the fuse box 170 are input to the multiplexer 103B connected to the address terminal 104B of the redundant RAM 101B.

  In many cases, the logic circuits 117A and 117B and the redundant RAMs 101A and 101B for generating the normal address signal to be supplied to the redundant memory are separated and disposed far away. However, the multiplexers 103A and 103B are connected to the logic circuits 117A and 117B as much as possible. Arranged in the vicinity so that the signal wiring from the outputs of the multiplexers 103A and 103B to the address terminals 104A and 104B of the redundant RAMs 101A and 101B is a long wiring. That is, the relationship between the logic circuit 117A, the multiplexer 103A, and the redundant RAM 101A and the configuration thereof are the same as those of the logic circuit 117, the multiplexer 103, and the redundant RAM 101 in the first embodiment, and the logic circuit 117B, the multiplexer 103B, and the redundant RAM 101B The same applies to the relationships and their configuration.

  FIG. 14 shows the configuration of the fuse box 170 of the seventh embodiment. The fuse box 170 is composed of a plurality of fuse circuit groups for a plurality of memories, and each fuse circuit group corresponding to each memory is composed of a plurality of fuse circuits. In this embodiment, the fuse circuit group A 173 for the first RAM and the fuse circuit group B 174 for the second RAM are configured. The multiplexer 171 selects the output of the fuse circuit group A 173 for the first RAM or the output of the fuse circuit group B 174 for the second RAM and outputs it from the fuse output terminal 111. The reset signal of the latch of each fuse circuit 115 (the internal configuration is the same as in FIG. 3) is supplied from the reset terminal 110.

  Further, the operation of the semiconductor memory device according to the seventh embodiment will be described with reference to FIG. FIG. 15 is an operation timing chart of the semiconductor memory device according to the seventh embodiment.

  As an initial setting, an arbitrary fuse in the fuse box 170 is cut according to the redundant relief address information. In this embodiment, the redundant relief address information for the first redundant RAM 101A is set by the fuse of the fuse circuit group A173, and the redundant relief address information for the second redundant RAM 101B is set by the fuse of the fuse circuit group B174. Shall. An H level reset signal is input from the reset terminal 110 of the fuse box 170, the fuse circuit 115 is reset, and after releasing the reset, for example, a selection signal for the first redundant RAM is given to the RAM selection terminal 172, so that the fuse The redundant repair address information for the first redundant RAM 101A output from the circuit group A 173 is selected by the multiplexer 171 and a desired redundant repair address signal of the first redundant RAM 101A is output from the fuse information output terminal 111. By switching the selection output of the multiplexer 103A to the signal of the fuse information output terminal 111 and setting the redundancy setting terminal 108A of the redundant RAM 101A to the H level, the redundant relief address information is taken into the redundant RAM 101A at the rising edge of the clock signal.

  Similarly, by supplying a selection signal for the second redundant RAM to the RAM selection terminal 172, the redundant relief address signal for the second redundant RAM 101B is selected by the multiplexer 171 and output from the fuse information output terminal 111. By switching the selection output of the multiplexer 103B to the signal of the fuse information output terminal 111 and setting the redundancy setting terminal 108B of the redundant RAM 101B to the H level, the redundant relief address information is taken into the redundant RAM 101B at the rising edge of the clock signal.

  Since the redundancy setting terminals 108A and 108B are returned to the L level and the redundancy repair of the RAM is continued, a normal memory operation is performed.

  According to the seventh embodiment as described above, the integrated fuse box 170 can further reduce the signal wiring between the redundant RAMs 101A and 101B and the fuse box 170, reduce the area of the LSI chip, and design efficiency when designing the chip. Can be improved.

(Embodiment 8)
FIG. 16 is a configuration diagram of the fuse box of the semiconductor memory device according to the eighth embodiment of the present invention. In the eighth embodiment, the fuse box 170 in FIG. 16 is used in place of the fuse box 170 in the seventh embodiment, and other configurations are the same as those in the seventh embodiment. The fuse box 180 includes a plurality of fuse circuit groups 183 and 184 (corresponding to 173 and 174 in FIG. 14) and a multiplexer 181 (corresponding to 171 in FIG. 14) similar to FIG. Yes.

  That is, the fuse box 180 is composed of a plurality of fuse circuit groups for a plurality of memories, and each fuse circuit group corresponding to each memory is composed of a plurality of fuse circuits. In this embodiment, the fuse circuit group A 183 for the first RAM and the fuse circuit group B 184 for the second RAM are configured. The multiplexer 181 selects the output of the first RAM fuse circuit group A 183 or the output of the second RAM fuse circuit group B 184 and outputs the selected output to the fuse output terminal 111.

  In the eighth embodiment, the reset terminal 110 is connected to the pulse generation circuit 185. The pulse generation circuit 185 is configured by serially connecting three stages of one-shot pulse generation circuits. The output of the first-stage one-shot pulse generation circuit is a fuse reset signal 134, and the reset pulse of the fuse circuit 115 is output. Is generated. The output pulse of the second-stage one-shot pulse generation circuit is output from the first redundancy setting control terminal 187 for the first redundancy RAM. The output pulse of the third-stage one-shot pulse generation circuit is output from the second redundancy setting control terminal 188 for the second redundancy RAM. The output pulse output from the first redundancy setting control terminal 187 is a redundancy setting signal (redundancy relief address information acquisition mode signal) indicating the redundancy relief address information acquisition mode, and is input to the multiplexer 103A as its control signal. At the same time, it is input to the redundancy setting terminal 108A of the first redundancy RAM 101A. The output pulse output from the second redundancy setting control terminal 188 is a redundancy setting signal (redundancy relief address information capture mode signal) indicating the redundancy relief address information capture mode, and the control signal is sent to the multiplexer 103B. As well as being input to the redundancy setting terminal 108B of the second redundancy RAM 101B.

  Further, the operation of the semiconductor memory device according to the eighth embodiment will be described with reference to FIG. FIG. 17 is an operation timing chart of the semiconductor memory device according to the eighth embodiment.

  As an initial setting, an arbitrary fuse in the fuse box 180 is cut according to the redundant relief address information. In the present embodiment, redundant relief address information for the first redundant RAM 101A is set with a fuse of the fuse circuit group A183, and redundant relief address information for the second redundant RAM 101B is set with a fuse of the fuse circuit group B184. Shall. When an H level reset signal is input to the reset terminal 110 of the fuse box 180, a reset pulse is generated in the fuse reset signal 134 by the first-stage one-shot pulse generation circuit of the pulse generation circuit 185. The fuse circuit 115 can be reset by this pulse. Further, the second-stage one-shot pulse generation circuit 186 generates a redundant relief setting control pulse for the first redundant RAM and outputs it from the control terminal 187. Further, a redundant relief setting control pulse for the second redundant RAM is generated by the third-stage one-shot pulse generation circuit 186 and output from the control terminal 188.

  After releasing the reset, for example, by supplying a selection signal of the first redundant RAM to the RAM selection terminal 182, redundant relief address information for the first redundant RAM 101 A output from the fuse circuit group A 183 is selected by the multiplexer 181, and the fuse is selected. A desired redundant relief address signal of the first redundant RAM 101A is output from the information output terminal 111. The multiplexer 103A selectively outputs the signal of the fuse information output terminal 111, and the redundant RAM 101A takes in the redundant relief address information at the rising edge of the clock signal.

  Similarly, by supplying a selection signal for the second redundant RAM to the RAM selection terminal 182, redundant relief address information for the second redundant RAM 101 B output from the fuse circuit group B 184 is selected by the multiplexer 181, and the fuse information is output. A desired redundant relief address signal of the second redundant RAM 101B is output from the terminal 111. The multiplexer 103B selectively outputs the signal of the fuse information output terminal 111, and the redundant RAM 101B takes in the redundant relief address information at the rising edge of the clock signal.

  According to the eighth embodiment as described above, in addition to the effects of the seventh embodiment, the control signals from the multiplexers 103A and 103B and the redundant setting terminals 108A of the redundant RAMs 101A and 101B, which require a control input from the outside in the seventh embodiment. , 108B can be generated without generating and supplying the control signal from the outside.

  In the seventh and eighth embodiments, instead of the address terminals 104A and 104B of the redundant RAMs, the data input terminals 105A and 105B may also be used as redundant redundant address signal input terminals. .

1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. 1 is a configuration diagram of a main part of a redundant RAM of a semiconductor memory device according to a first embodiment of the present invention. 1 is a main part configuration diagram of a fuse box of a semiconductor memory device according to a first embodiment of the present invention. Operation Timing Chart of Semiconductor Memory Device of Embodiment 1 of the Present Invention FIG. 3 is a main part configuration diagram of a redundant RAM of a semiconductor memory device according to a second embodiment of the present invention. FIG. 5 is a main part configuration diagram of a fuse box of a semiconductor memory device according to a third embodiment of the present invention. Operation Timing Chart of Semiconductor Memory Device of Embodiment 3 of the Present Invention Configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention Configuration diagram of a semiconductor memory device according to a fifth embodiment of the present invention Configuration diagram of main part of redundant RAM of semiconductor memory device according to embodiment 5 of the present invention Configuration diagram of a semiconductor memory device according to a sixth embodiment of the present invention FIG. 10 is a main part configuration diagram of a fuse box of a semiconductor memory device according to a sixth embodiment of the present invention. Configuration diagram of a semiconductor memory device according to a seventh embodiment of the present invention FIG. 9 is a main part configuration diagram of a fuse box of a semiconductor memory device according to a seventh embodiment of the present invention. Operation Timing Chart of Semiconductor Memory Device of Embodiment 7 of the Present Invention FIG. 9 is a configuration diagram of a main part of a fuse box of a semiconductor memory device according to an eighth embodiment of the present invention. Operation Timing Chart of Semiconductor Memory Device of Embodiment 8 of the Present Invention Configuration diagram of conventional semiconductor memory device Operation Timing Chart of Conventional Semiconductor Memory Device

Explanation of symbols

101 ... Redundant RAM
DESCRIPTION OF SYMBOLS 102 ... Fuse box 103 ... Multiplexer 104 ... Address terminal 105 ... Data input terminal 106 ... Write control terminal 107 ... Clock terminal 108 ... Redundancy setting terminal 109 ... Data output terminal 110 ... Reset terminal 111 ... Fuse information output terminal 112 ... Latch circuit 113 ... AND circuit 114 ... FF circuit 115 ... Fuse circuit 116 ... Fuse 117 ... Logic circuit 118 ... Logic circuit 121 ... Redundant RAM
122… Output terminal selector 131… Fuse box 132… Pulse generation circuit 133… Redundancy setting control terminal 134… Fuse reset signal 135… Delay INV (inverter)
136 ... Delay INV (inverter)
141 ... Redundant relief address generation circuit 142 ... Redundant relief address information output terminal 151 ... Redundant RAM
160 ... fuse box 161 ... test control terminal 162 ... multiplexer 163 ... test terminal 170 ... fuse box 171 ... multiplexer 172 ... RAM selection terminal 173 ... fuse circuit group A
174 ... Fuse circuit group B
180 ... fuse box 181 ... multiplexer 182 ... RAM selection terminal 183 ... fuse circuit group A
184 ... Fuse circuit group B
185 ... Pulse generation circuit 186 ... One shot pulse generation circuit 187 ... First redundancy setting control terminal 188 ... Second redundancy setting control terminal 201 ... Redundancy RAM
202 ... fuse box 204 ... address terminal 205 ... data input terminal 206 ... write control terminal 207 ... clock terminal 208 ... fuse information input terminal 209 ... data output terminal 210 ... reset terminal 211 ... fuse information output terminal

Claims (10)

A random access memory (hereinafter referred to as RAM) having an address input terminal for inputting a normal address signal and having a redundancy relief function for relief of a failed memory cell based on the redundancy relief address signal;
Redundant relief address signal setting means for outputting a redundant relief address signal to be applied to the RAM;
The normal address signal and the redundant relief address signal are input, the redundant relief address signal is output to the address input terminal in the redundant relief address information capture mode, and the normal address signal is output in a mode other than the redundancy relief address information capture mode. First selection means for outputting to the address input terminal,
A semiconductor memory device in which the RAM is provided with a latch circuit for latching a redundant relief address signal input to the address input terminal in the redundant relief address information fetch mode. A RAM having a data input terminal for inputting a normal data signal and having a redundant relief function for relieving a failed memory cell based on a redundant relief address signal;
Redundant relief address signal setting means for outputting a redundant relief address signal to be applied to the RAM;
The normal data signal and the redundant relief address signal are input, the redundant relief address signal is output to the data input terminal in the redundant relief address information capture mode, and the normal data signal is output in a mode other than the redundant relief address information capture mode. First selection means for outputting to the data input terminal,
A semiconductor memory device in which the RAM is provided with a latch circuit for latching a redundant relief address signal input to the data input terminal in a redundant relief address information fetch mode.   The redundant relief address signal setting means is a fuse box including a plurality of fuse circuits for outputting a redundant relief address signal set in accordance with a cut / non-cut state of a built-in fuse. Item 3. The semiconductor memory device according to Item 1 or 2.   The fuse box has a reset terminal for resetting the plurality of fuse circuits, and resets the fuse circuit by giving a reset signal to the reset terminal. After the reset is completed, the fuse circuit outputs a redundant relief address signal. 4. The semiconductor memory device according to claim 3, wherein the first selection means and the latch circuit of the RAM are set in a redundant relief address information fetch mode.   The fuse box includes a reset terminal for inputting an external reset signal, and two one-shot pulse generation circuits connected in series to the reset terminal, and generates the first-stage one-shot pulse connected in serial An output pulse of the circuit is provided as a reset signal to the plurality of fuse circuits, and an output pulse of the second-stage one-shot pulse generation circuit is used as a signal indicating the redundant relief address information capturing mode as the first selection means and 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device outputs the data to the RAM.   The RAM has a data output terminal, and a normal data signal and a redundant relief address signal latched by the latch circuit are input into the RAM, and the redundant relief address signal is input to the RAM in the redundant relief address information capture mode. 6. The second selection means for outputting to the data output terminal and outputting the normal data signal to the data output terminal when not in the redundant relief address information fetch mode. The semiconductor memory device described in 1.   The fuse box includes third selection means for inputting a test redundant relief address signal and an output signal of the fuse circuit from the outside, and the third selection means is a test redundant relief address signal in a test mode. 4. The semiconductor memory device according to claim 3, wherein the output signal of the fuse circuit is selectively output in a mode other than the test mode.   3. The semiconductor memory device according to claim 1, wherein the redundancy relief address signal setting means is a redundancy relief address generation circuit that generates a redundancy relief address signal without using a fuse. Each of the RAM according to claim 1 or 2 and a plurality of first selection means corresponding thereto are provided,
A plurality of fuse circuit groups that output redundant relief address signals set according to the cut / non-cut state of the built-in fuses are provided corresponding to each RAM, and from among the outputs of the plurality of fuse circuit groups, A fuse box provided with second selection means for selecting an output of the fuse circuit group corresponding to one RAM arbitrarily selected by a selection signal of the RAM and outputting it to a redundant relief address signal output terminal;
Connecting the redundant relief address signal output terminal and a terminal for inputting a redundant relief address signal of the first selection means corresponding to each RAM;
A semiconductor memory device in which the RAM selected by the selection signal and the first selection means corresponding thereto are set in a redundant relief address information fetch mode. There are n RAMs (n is a plurality),
The fuse box includes a reset terminal for inputting an external reset signal, and (n + 1) one-shot pulse generation circuits serially connected to the reset terminal, and the first stage one connected to the serial is connected. In this mode, the output pulse of the shot pulse generation circuit is given as a reset signal to the plurality of fuse circuit groups, and each output pulse of the one-shot pulse generation circuit after the second stage is a redundant relief address information fetch mode corresponding to each RAM. 10. The semiconductor memory device according to claim 9, wherein a signal indicating this is output to said RAM selected by said selection signal and said first selection means corresponding thereto.

Images