JP2001035187A - Semiconductor memory and its redundant relieving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory and its redundant relieving method which can perform a test of a pseudo relieving state being equivalent to a state after successive redundant relieving by feeding back a result of a probe test, in a probe test process before redundant relieving. SOLUTION: This device is a redundant relieving circuit section included in a DRAM, and comprises a memory cell array 1 consisting of plural memory cells, a relieving circuit 2 for replacing a defective line selecting an arbitrary memory cell in this memory cell array 1 by a redundant line and the like. The relieving circuit 2 a fault position indicating circuit 11 indicating a fault position based on a test result of the memory cell array 1, a pseudo relieving information circuit 12 making pseudo relieving information based on this information, a selecting circuit 13 supplying this information to the memory array 1 and performing a pseudo relieving state being a state after redundant, relieving, a fuse circuit 14 for replacing a defective line corresponding to a fault position by a redundant line based on pseudo relieving information, and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technique for a semiconductor device, and more particularly to a semiconductor device suitable for performing a test in a pseudo inspection state equivalent to that after a redundancy relief before a redundancy relief in a probe inspection process, and a redundant device for the same. It relates to effective technology applied to remedies.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a redundancy repair technique such as a DRAM as an example of a semiconductor device, a probe test is performed to test the electrical characteristics of an integrated circuit formed on a semiconductor wafer. After that, based on the test result, the fuse corresponding to the failure position is cut by laser processing to perform a redundancy rescue process. After the redundancy rescue process, a test of the same electrical characteristics as in the probe test is performed again. A method of determining a non-defective / defective product based on a test result of a probe test after redundancy repair is generally used.

[0003] As for such a redundancy repair technique for a semiconductor device, for example, “Advanced Electronics I-Issu” published by Baifukan Co., Ltd. on November 5, 1994.
9 super LSI memory "on page 181 to P183.

[0004]

In the above-described semiconductor device redundancy repair technology, the processing is performed in the order of a probe test, a redundancy repair process, and a probe test. It is necessary to perform two probe tests, and it is necessary to perform a redundancy repair process after extracting the test result of the first probe test to the outside, which leads to an increase in test time. That is, at the time of the first probe inspection, since the memory cell test for the redundancy relief of the memory cell array is not performed, it is necessary to determine the non-defective / defective product by performing the second probe inspection after the laser processing. .

Therefore, an object of the present invention is to pay attention to the necessity of two probe tests before and after the redundancy repair processing, and to devise the configuration of the repair circuit, so that the redundancy test is performed in the probe test process before the redundancy repair. It is an object of the present invention to provide a semiconductor device capable of feeding back a result of a probe test before rescue and subsequently performing a test of a pseudo rescue state equivalent to that after the redundancy rescue, and a redundancy rescue method thereof.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor device according to the present invention supplies a predetermined test information to the memory cell array as a rescue circuit for replacing a defective line for selecting an arbitrary memory cell in the memory cell array with a redundant line to perform a test. A fault location indicating circuit for determining a fault location based on the test result; a pseudo relief information circuit for generating pseudo relief information based on fault location information by the fault location indicating circuit;
The dummy repair information circuit includes a selection circuit that switches the pseudo repair information from the test information and supplies the same to the memory cell array, and performs a test of a pseudo relief state equivalent to that after the redundancy relief before the redundancy relief.

In this configuration, there is further provided a fuse circuit comprising a cuttable fuse for replacing a defective line corresponding to a failure position with a redundant line based on the pseudo-repair information by the pseudo-repair information circuit. If the test result is determined to be non-defective, the fuse corresponding to the redundant line of the fuse circuit is cut to perform a redundancy repair process to determine a non-defective product. Alternatively, a non-volatile memory circuit capable of storing the rescue address information is provided, and the redundancy rescue process is performed by using the rescue address information corresponding to the redundant line of the non-volatile memory circuit, thereby obtaining a non-defective product. On the other hand, when the test result in the pseudo remedy state is determined to be defective, the defective product is determined to be defective without performing the redundancy repair processing.

Further, in the method for repairing redundancy of a semiconductor device according to the present invention, a test is performed by supplying predetermined test information to a memory cell array as a probe test step for testing an electrical characteristic of an integrated circuit formed on a semiconductor wafer. Then, based on the test result, a fault location is pointed out, pseudo rescue information is created based on the fault location information, the pseudo rescue information is switched from the test information and supplied to the memory cell array, and the redundancy repair is performed before the redundancy repair. A test of a pseudo rescue state equivalent to that after the remedy is performed, and if the test result in the pseudo rescue state is determined to be a non-defective product, a redundant remedy process is performed to determine a non-defective product,
Each process includes a step of determining a defective product without performing a redundancy repair process and determining that the product is defective.

Therefore, according to the semiconductor device and the redundancy repair method therefor, after performing the test of the memory cell array, the pseudo-relief information is fed back to the memory cell array, and the test of the memory cell array is continuously performed, so that a chip which becomes a non-defective product is obtained. By performing redundant relief processing only on
Since the probe test after the redundancy repair can be omitted, the test time can be reduced. Further, for a defective chip which does not become a non-defective product even after performing the redundancy repair (for example, when the redundancy repair memory cell is out of order), the redundancy repair process becomes unnecessary.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1) FIG. 1 is a functional block diagram showing a main part (redundant relief circuit section) of a semiconductor device according to Embodiment 1 of the present invention, and FIG. FIG. 3 is a functional block diagram showing a fault repair information circuit, FIG. 3 is a functional block diagram showing a pseudo repair information circuit, and FIG. 4 is a flowchart showing a redundant repair method.

First, referring to FIG. 1, an example of the configuration of the redundancy repair circuit section of the semiconductor device of the first embodiment will be described.

The redundancy repair circuit portion of the semiconductor device according to the first embodiment includes, for example, a memory cell array 1 including a plurality of memory cells (RAM cells) included in a DRAM and an arbitrary memory cell in the memory cell array 1. A relief circuit 2 for replacing a defective line to be selected with a redundant line;
In the probe inspection process, it is possible to perform a test of a pseudo relief state equivalent to that after the redundancy relief before the redundancy relief.

The DRAM includes, in addition to the memory cell array 1 and the rescue circuit 2, an address buffer and an address decoder (not shown) for designating any row / column address, and data input / output. A well-known semiconductor manufacturing device is provided with a sense amplifier, a main amplifier, an input / output buffer, a timing generation circuit for generating a control signal for an internal circuit, an internal voltage generation circuit for generating an operation voltage of the internal circuit, and the like. It is formed on one semiconductor chip by technology.

The memory cell array 1 is provided with regions of a regular memory cell array 1a and a memory cell array 1b for redundancy repair, for example, a regular memory cell array 1a.
If there is a defect in any of the memory cells, or a word line and a bit line for selecting this memory cell, the defective line of this regular memory cell array 1a is passed through the row / column relief circuit 2 Are replaced by the redundancy lines of the memory cell array 1b for redundancy relief. The memory cell array 1 is divided into a plurality of mat units.

The repair circuit 2 supplies a predetermined test information to the memory cell array 1 to perform a test, and based on the test result, a fault position indicating circuit 11 for indicating a fault position.
A pseudo rescue information circuit 12 for generating pseudo rescue information based on the failure position information; and switching the pseudo rescue information from the test information to the memory cell array 1 so that the pseudo rescue information is equivalent to that after the redundancy rescue before the redundancy rescue. A selection circuit 13 for testing a pseudo relief state, a fuse circuit 14 for replacing a defective line corresponding to a failure position with a redundant line based on the pseudo relief information by the pseudo relief information circuit 12, and the like are provided.

As shown in FIG. 2, for example, the fault position indicating circuit 11 receives an output of a memory cell and an expected value as inputs, and performs an exclusive OR circuit 11a for performing this comparison for each bit, and an exclusive OR circuit 11a. A logical sum circuit 11b that performs a logical sum of all pass / fail information of each bit from the logical sum circuit 11a, and an encoder circuit 11c that encodes the pass / fail information of each bit to generate fault position information And a pass / fail register 11d for holding the ORed pass / fail information, a fail bit register 11e for holding the encoded fault position information, and a fail for holding the fault position information based on the read address of the memory cell. Word register 11f and control logic 1 for controlling each of registers 11d, 11e, 11f
1g and the like, and fault position information is created based on a test result based on the test information supplied to each memory cell of the memory cell array 1.

As shown in FIG. 3, for example, the pseudo relief information circuit 12 includes a pass / fail register 11d, a fail bit register 11e,
It is composed of a failure position information conversion unit 12a that receives the failure position information of the fail word register 11f and converts the failure position information into desired fuse cutting information, a relief information register 12b that holds the converted fuse cutting information, and the like. On the basis of the fault position information from the fault position indicating circuit 11, pseudo relief information of the fuse cutting information is created.

The selection circuit 13 is controlled by a rescue control signal for switching between pseudo rescue information and test information. When performing a test of the pseudo rescue state, the pseudo rescue information is selected by the rescue control signal and is supplied to the memory cell array 1. Supplied,
The probe test is performed in a state equivalent to the state after the redundancy repair in which the fuse of the corresponding fuse circuit 14 for replacing the defective line with the redundant line is cut.

The fuse circuit 14 is composed of a fuse that can be cut by, for example, laser processing. The signal can be switched by cutting the fuse. If the test result in the pseudo relief state is determined to be good, the fuse circuit 14 is connected to the redundant line. The corresponding fuse is cut to perform a redundancy repair process, and is selected as a non-defective chip. On the other hand, if it is determined to be a defective product, it is selected as a defective chip without performing the redundancy repair process.

Next, the operation of the first embodiment will be described with reference to FIG. This redundancy remedy method is performed in a probe inspection process for testing the electrical characteristics of an integrated circuit formed on a semiconductor wafer.

In the probe inspection process, first, predetermined test information is supplied to the memory cell array 1 to test the electrical characteristics (step 401). In the electrical characteristic test, for example, a semiconductor probe after wafer processing is used to test electrical characteristics such as a DC test and an AC test by bringing a probe needle into contact with a pad of each chip by a wafer prober.

Further, the fault location of the memory cell array 1 is pointed out based on the test result of step 401 (step 402). The indication of the failure position indicates, for example, a defect in an arbitrary memory cell in the normal memory cell array 1a or a word line and a bit line for selecting the memory cell.

Then, pseudo rescue information is created based on the fault location information pointed out in step 402 (step 403). In the creation of the pseudo relief information, for example, relief address information for replacing a defective line of the indicated memory cell in the normal memory cell array 1a with a redundant line of the redundant relief memory cell array 1b is generated.

Subsequently, the pseudo rescue information created in step 403 is switched from the test information by the rescue control signal in the selection circuit 13 and supplied to the memory cell array 1 so that the pseudo rescue information is equivalent to the pseudo remedy before the redundancy remedy and after the redundancy remedy. A state test is performed (step 404). In the test in the pseudo relief state, an electrical characteristic test similar to that in step 401 is performed in a state equivalent to the state after the redundancy relief in which the corresponding fuse for replacing the defective line with the redundant line is cut.

If the test result in the pseudo rescue state in step 404 is determined to be non-defective, a redundant remedy process is performed to obtain a non-defective chip (step 405). In this redundancy repair processing, the fuse of the fuse circuit 14 corresponding to the redundant line for replacing the defective line is cut by laser processing, and is selected as a good chip.

On the other hand, if it is determined that the chip is defective, the chip is determined as a defective chip without performing the redundancy repair processing (step 4).
06). This defective chip is a chip that does not become a non-defective product even when the redundancy repair processing is performed, such as when the memory cell for redundancy repair has failed, and thus the redundancy repair processing is unnecessary.

As described above, in the probe inspection process, processing up to selection of good / defective chips is completed, and thereafter, the semiconductor wafer is cut into chips using a dicing saw. By incorporating only the chip into a package or the like, a DRAM semiconductor device can be manufactured.

Therefore, according to the semiconductor device of the first embodiment, the fault location indicating circuit 11, the pseudo repair information circuit 12,
A rescue circuit 2 including a selection circuit 13, a fuse circuit 14, and the like is provided. After performing a test of the memory cell array 1 in a probe test process, pseudo relief information is fed back to the memory cell array 1 to continuously test the memory cell array 1. By performing the redundancy repair processing only on the chips that become good products, the test of the probe inspection after the redundancy repair can be omitted. In other words, by feeding back the pseudo relief information, it is possible to make the same as the state where the fuse processing has been performed in a pseudo manner, so that the necessity of the second probe inspection is eliminated. Therefore, two tests have been performed so far, but one test is sufficient, so that the test time can be reduced.

(Embodiment 2) FIG. 5 is a functional block diagram showing a main part (redundant relief circuit section) of a semiconductor device according to Embodiment 2 of the present invention.

The redundancy repair circuit portion of the semiconductor device according to the second embodiment is included in the DRAM as in the first embodiment.
It comprises a memory cell array 1 composed of a plurality of memory cells, a relief circuit 2 for replacing a defective line for selecting an arbitrary memory cell in the memory cell array 1 with a redundant line, and the like. Is the fuse circuit 14
Is that a non-volatile memory circuit is used instead.

That is, in the repair circuit 2 of the semiconductor device according to the second embodiment, in addition to the fault location indicating circuit 11, the pseudo repair information circuit 12, and the selection circuit 13, the pseudo repair is performed as in the first embodiment. Non-volatile memory 21 capable of storing relief address information for replacing a defective line corresponding to a failure position with a redundant line based on pseudo relief information by information circuit 12
And so on.

The non-volatile memory 21 is, for example, a ROM or the like. When the test result in the pseudo remedy state is determined to be non-defective, a redundant rescue process is performed using the rescue address information corresponding to the redundant line, and a non-defective chip is obtained. Is sorted out,
On the other hand, when it is determined that the chip is defective, the chip is selected as a defective chip without performing the redundancy repair processing.

Therefore, in the probe inspection step of the semiconductor device according to the second embodiment, a test of the memory cell array 1 is executed with the nonvolatile memory 21 initialized, and the test result is fed back to the memory cell array 1. Then, the test is executed in a pseudo rescue state with the signal of the pseudo rescue information circuit 12, and if the test is determined to be non-defective, the information of the pseudo rescue information circuit 12 in that state is written to the nonvolatile memory 21 by a predetermined instruction. The defective address line of the specified memory cell in the normal memory cell array 1a is replaced with the redundant line of the redundant memory cell array 1b by the repair address information written in the nonvolatile memory 21.

Therefore, according to the semiconductor device of the second embodiment, the nonvolatile memory 21 is provided instead of the fuse circuit 14, so that the memory cell array 1 , The pseudo repair information is fed back to the memory cell array 1, the memory cell array 1 is continuously tested, and the redundant repair processing is performed only on the non-defective chips. Since the test can be omitted, one test can be performed instead of the two tests so far, so that the test time can be reduced.

Further, as compared with the first embodiment, it is not necessary to cut the fuse, so that a DRAM which can be automatically relieved at the stage when the probe test is completed can be constituted.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, D
Although the case where the present invention is applied to a RAM has been described, the present invention is not limited to this, and the present invention can be applied to other semiconductor devices including a RAM cell having a redundancy relief function such as an SRAM. In this case, a semiconductor device having a large logic scale and a large number of mounted RAMs requires a long test time, and the effect of the present invention is also enhanced.

In the second embodiment, a mask ROM or the like can be used as a nonvolatile memory circuit.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) As a rescue circuit for replacing a defective line for selecting an arbitrary memory cell in a memory cell array with a redundant line, a fault location indicating circuit, a pseudo rescue information circuit, a selection circuit, and the like are included. In the probe inspection process, pseudo rescue information created based on the test result of the memory cell array is supplied to the memory cell array, and a test of a pseudo rescue state equivalent to that after the redundancy remedy is performed before the redundancy remedy, and is determined to be good. In such a case, since a good product can be obtained by performing the redundancy repair processing, it is possible to omit the probe test test after the redundancy repair.

(2) According to the above (1), DRAM, SRAM
In a semiconductor device equipped with a memory cell having a redundancy relief function such as that described above, in a probe inspection step before the redundancy relief, a result of the probe inspection before the redundancy relief is fed back, and a pseudo relief state equivalent to that after the redundancy relief is continued. Can be performed, leading to a reduction in test time and a reduction in cost.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram showing a main part (redundant relief circuit unit) of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a functional configuration diagram showing a fault location indicating circuit.

FIG. 3 shows a semiconductor device according to the first embodiment of the present invention;
It is a functional block diagram which shows a pseudo relief information circuit.

FIG. 4 shows a semiconductor device according to the first embodiment of the present invention;
It is a flowchart which shows a redundancy relief method.

FIG. 5 is a functional configuration diagram illustrating a main part (redundant relief circuit unit) of the semiconductor device according to the second embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 memory cell array 1a regular memory cell array 1b memory cell array for redundancy rescue 2 rescue circuit 11 fault location circuit 11a exclusive OR circuit 11b OR circuit 11c encoder circuit 11d pass / fail register 11e fail bit register 11f fail word register 11g Control logic 12 Pseudo rescue information circuit 12a Fault location information converter 12b Relief information register 13 Selection circuit 14 Fuse circuit 21 Non-volatile memory

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G11C 11/34 371D (72) Inventor Shigeru Nakahara 6-16, Shinmachi, Shinmachi, Ome City, Tokyo 3 Hitachi, Ltd. F term in device development center (reference) 2G032 AA07 AB01 AE08 AF01 5B018 GA03 GA06 HA21 KA13 KA16 MA32 NA02 NA03 QA13 RA13 5B024 AA15 BA18 BA29 CA17 CA27 EA02 5L106 AA01 AA02 CC04 CC09 CC12 CC13 CC14 CC17 DD08 DD22 DD23 DD25 DD25

Claims (5)

[Claims] A memory cell array including a plurality of memory cells; and a rescue circuit for replacing a defective line for selecting an arbitrary memory cell in the memory cell array with a redundant line. A test is performed by supplying predetermined test information to the memory cell array, and a fault position indicating circuit that points out a fault position based on the test result, and pseudo relief information is created based on the fault position information by the fault position indicating circuit. A pseudo rescue information circuit, and a selection circuit for switching pseudo rescue information by the pseudo rescue information circuit from the test information and supplying the pseudo rescue information to the memory cell array and testing a pseudo rescue state equivalent to that after the redundancy rescue before the redundancy rescue. A semiconductor device comprising: 2. The semiconductor device according to claim 1, comprising a cuttable fuse for replacing a defective line corresponding to the failure position with a redundant line based on pseudo-repair information by the pseudo-repair information circuit. A fuse circuit, and when the test result in the pseudo relief state is determined to be non-defective,
A semiconductor device characterized in that a fuse corresponding to the redundant line of the fuse circuit is cut and a redundancy repair process is performed to obtain a non-defective product. 3. The semiconductor device according to claim 1, wherein relief address information for replacing a defective line corresponding to the failure position with a redundant line based on the pseudo relief information by the pseudo relief information circuit can be stored. Has a non-volatile memory circuit,
If the test result in the pseudo remedy state is determined to be non-defective, a redundant remedy process is performed by using rescue address information corresponding to the redundant line of the nonvolatile memory circuit, and the semiconductor device is determined to be non-defective. 4. The semiconductor device according to claim 1, wherein when the test result in the pseudo relief state is determined to be defective, the semiconductor device is determined to be defective without performing redundancy repair processing. Semiconductor device. 5. A probe inspection step for testing an electrical characteristic of an integrated circuit formed on a semiconductor wafer, wherein the probe inspection step performs a test by supplying predetermined test information to a memory cell array. A step of pointing out a failure position based on a test result; a step of creating pseudo relief information based on the failure position information; and switching the pseudo relief information from the test information to supply to the memory cell array, A step of testing a pseudo remedy state equivalent to that after the redundancy remedy before, and a case where the test result of the pseudo remedy state is determined to be a good product by performing a redundancy remedy process to determine a non-defective product and a defective product. Forming a defective product without performing the redundancy repair processing.