JPH06223597A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the time testing the simultaneous write and the different data write in the direction of adjacent row, column by selecting a common logic data input route and a different logic data input route to two pieces of data input lines of test data. CONSTITUTION:When a test input part 170 is set to L, write lines 141-144 become the same data as decoder outputs 131-134, and the first input part of route selection circuits 151-158 is selected. Then, the first input part is incorporated in a writable memory cell line by an X decoder 130. Further, the data are written in only a cell connected to two pieces of input parts selected by a data input designation switching circuit 107 through the route selection circuit. When the part 170 is set to H and the lines 141-144 are made L, the write to all cells become possible, and the second input part of the circuits 151-158 is selected, and the write control becomes possible only by the parts 101, 102. Thus, the different data write is performed in the cell in the direction of adjacent row, column en bloc and simultaneously, and the data with data inversion logic are written by the data inversion of the input part 102 as well similarly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for facilitating testing of a semiconductor device having a memory cell array.

[0002]

2. Description of the Related Art A conventional semiconductor device is shown in FIG.
An X-decoder that makes a memory cell column writable according to an address signal, a data input designation switching circuit that writes desired data to a memory cell designated by the address signal in the memory cell column, and a plurality of memory cells collectively. By having a memory cell collective selection circuit for making data writable and having one data input line in each memory cell row, the memory cell column is selected by the X decoder and included in the memory cell column. And a first writing method of writing data of the data input line to a memory cell corresponding to one word, and making all memory cells writable by the memory cell batch selection circuit so that all memory cells have the same logic The second writing method for writing the above data was used.

[0003]

However, in the above-mentioned prior art, when performing an interference test for writing different data to the memory cells adjacent to each other in the row and column directions, the memory cells adjacent to each other in the row direction are subjected to an interference test. It is possible to write different data all at once, but it is impossible for adjacent memory cells in the column direction. Therefore, when writing, the interference test is performed by a method of writing the memory cells in the even columns at the first time and the memory cells in the odd columns at the second time, and the test time becomes long.

Therefore, the present invention solves such a problem, and the object of the present invention is to solve the above problems.
It is an object of the present invention to provide a semiconductor device which enables the second writing method and the third writing method of simultaneously writing data of different logics simultaneously in memory cells adjacent to each other in the row direction and the column direction.

[0005]

In order to solve the above problems, a semiconductor device having a memory cell array of the present invention is
An X-decoder that makes a memory cell column writable according to an address signal, a data input designation switching circuit that writes desired data to a memory cell designated by the address signal in the memory cell column, and a plurality of memories of the memory cell array. A memory cell batch selection circuit that makes it possible to write cells collectively, two data input lines for each memory cell row of the memory cell array, and the adjacent memory cells in the memory cell row have the two The two data input lines are alternately connected to different data input lines, and the two data input lines have a path for transmitting the two input data in positive logic and a different path from the input data. A route selection circuit for selecting a route for transmitting the test data, the test data having a common logic to the two data input lines. Data input designation switching among the memory cell columns writable by the X-decoder by being configured by a logic selection circuit that selects a path for inputting data and a path for inputting data of different logics. A first writing method for writing desired data in a memory cell designated by a circuit, and a first writing method for writing a plurality of memory cells in the memory cell batch selection circuit, and writing a common logic data in the plurality of memory cells at the same time. 2 and the memory cell batch selection circuit enables writing of a plurality of memory cells, and the data of different logics are collectively written simultaneously to the memory cells adjacent to each other in the row direction and the column direction in the plurality of memory cells. It has a third writing method for writing.

[0006]

According to the above configuration of the present invention, in addition to the writing of each memory cell by the first writing method, the simultaneous writing of the same logical data to all memory cells by the second writing method and the first writing method are performed. According to the writing method of No. 3, different logical data can be simultaneously written to the memory cells adjacent in the row direction and the column direction at the same time, and the interference test between the memory cells can be performed in a short time.

[0007]

1 shows a 2-bit memory cell array and its peripheral circuit diagram in the present invention. In FIG. 1, the memory cell array 100 includes input units 101 to 104 and output units 111 to 104.
Data is input and output by 114. In the data input, the data input to the memory cell external input unit 105 is input to the data input designation switching circuit 107 via the input buffer 106, and according to the Y address input unit 122, two of the input units 101 to 104 are input. Transmitted to the department. For data output, read lines 61-64
Then, the data of the memory cells are output from the data output lines 51 to 54 to the output units 111 to 114, two of them are selected by the output selection circuit 115, and the memory cells are externally output via the output buffer 114. It is configured to be output to the section 117. At this time,
In the output selection circuit 115, the output is selected by the output selection signal input unit 118. The write lines 141 to 144 are selected by the X decoder 130 according to the X address input unit 121. Outputs 131 to 13 of the X decoder 130
4 is connected to the write lines 141 to 144 via the memory cell collective selection circuit 140. The input units 101 to 104 respectively input the data input lines 11, 12, 21, 22, 31, 32, 41, 42 via the route selection circuits 151 to 158.
Connected to. The route selection circuits 151 to 158 have a function of selecting one from the two inputs by the test input unit 170, and the test input unit of these two input units is
The input section selected by L'is defined as the first input section, and the input section selected by'H 'is defined as the second input section. At this time, the input units 101 to 104 have the route selection circuits 151 to 158, respectively.
Of the data input line 1
1, 12, 21, 22, 31, 32, 41, 42. Further, the input units 101 and 102 are route selection circuits 152, 154, and 1 through the test logic selection circuit circuit 160.
With respect to the input unit 102, the second input units of 56 and 158 are also connected to the second input units of the route selection circuits 151, 153, 155, and 157. The test input section 170 is connected to the path selection circuits 151 to 158, the memory cell batch selection circuit 140, and the input data switching circuit 10.
7, the test input section 170 is set to “H”, and the memory cell batch selection circuit 140 forms all memory cell column write states and the path selection circuits 151 to 1 are connected.
The second input section is selected by 58, and the input sections 101 and 102 are selected by the input data switching circuit 107.
Memory cells 13-16, 23-26, 33-36, 43
Two data input lines are provided in each of the memory cell rows constituted by ˜46. The data input line 11 includes the memory cells 13 and 15, and the data input line 12 includes the memory cell 1.
4, 16 and memory cells 24, 2 on the data input line 21.
6, data input line 22 has memory cells 23 and 25, data input line 31 has memory cells 33 and 35, data input line 32 has memory cells 34 and 36, and data input line 41 has memory cells 44 and 46. Memory cells 43 and 45 are connected to the data input line 42, respectively. Also, memory cell 1
3 to 16 include a data output unit 51 and memory cells 23 to 26.
To the data output section 52, the memory cells 33 to 36 to the data output section 53, and the memory cells 43 to 46 to the data output section 54.

With the above circuit configuration, the test input section 17
When 0 is set to'L ', the write lines 141 to 144 have the same data as the decoder outputs 131 to 134, respectively, and the first input parts of the route selection circuits 151 to 158 are selected, and the input part 101 is the data input line 11 , 12 are the same data, the input unit 102 is the same data as the data input lines 21 and 22, the input unit 103 is the same data as the data input lines 31 and 32, and the input unit 104 is the same data as the data input lines 41 and 42. Therefore, data is stored only in the memory cells that are included in the memory cell column that is writable by the X decoder 130 and that are connected to the two input sections selected by the data input designation switching circuit 107 through the path selection circuit. Written.

If the test input section is set to "H",
The write lines 141 to 144 become'L ', and all the memory cells become writable, and at the same time, the path selection circuit 151
~ 158 second input is selected, input 101,10
Only 2 allows write control of all memory cells. At this time, when the input unit 101 is set to'L ', the second input unit of the route selection circuit causes the route selection circuits 151, 153, 155, 15 to operate.
7, the desired data of the input unit 102, 152, 154,
At 156 and 158, the data is the normal logic of the input unit 102 selected by the test logic selection circuit 160. Therefore, the input unit 102 is set to “H” to write all the memory cells “H”, and the input unit 102 is set to “L” to all the memory cells “L”.
You can write in batches at the same time. When the input unit 102 is set to “H”, the second input unit of the route selection circuit becomes 1
51, 153, 155, and 157 are the data of the input unit 102, and 152, 154, 156, and 158 are the data of the inverted logic of the input unit 102 selected by the test logic selection circuit 160. Therefore, the data input lines 11, 21, 3
1, 41 are data of the input unit 102, 12, 22, 32,
42 becomes the inverted logic data of the input section 102. Due to the data of these data input lines and the connection between the memory cells and the two data input lines, different data can be written simultaneously in the memory cells adjacent to each other in the row direction and the column method all at once. This can be done, and the data of the inversion logic of this data can be written in the same manner as above by inverting the data of the input unit 102.

As described above, by providing the two data input lines in the memory cell row, the interference test between the memory cells adjacent in the row direction and the column direction can be performed in a short time. In FIG. 1, the input units 101 and 102 also serve as the data control unit at the time of the interference test, but this part can also serve as another input unit.

[0011]

As described above, according to the present invention, in a semiconductor device having a memory cell array, simultaneous writing to all memory cells forming the memory cell array and simultaneous operation of memory cells adjacent to each other in the row and column directions are performed. A test for writing different data can be performed in a short time.

[Brief description of drawings]

FIG. 1 is a diagram of a 2-bit memory cell array of the present invention and its peripheral circuit.

FIG. 2 is a conventional memory circuit diagram.

[Explanation of symbols]

11, 12, 21, 22, 31, 32, 41, 42 ...
Data input lines 51, 52, 53, 54 ... Data output lines 61, 62, 63, 64 ... Read lines 13-16, 23-26, 33-36, 43-46 ...
-Memory cell 100 ... Memory cell array 101-104 ... Input section 105 ... Memory cell external input section 106 ... Input buffer 107 ... Data input designation switching circuit 111-114 ... Output section 115 Output selection circuit 116 Output buffer 117 Memory cell external output unit 118 Output selection signal input unit 121 X address input unit 122 Y address input unit 130 X decoder 131-134 ... X decoder output 140 ... Memory cell batch selection circuit 141-144 ... Write line 151-158 ... Path selection circuit 160 ... Test logic selection circuit 170 ... Test Input unit 200 ... Memory cell array 201-204 ... Input unit 205 ... Memory cell external input unit 206. Input buffer 207 ... Data input designation switching circuit 210 ... Memory cells 211 to 214 ... Output unit 215 ... Output selection circuit 216 ... Output buffer 217 ... Memory cell external output unit 218. .. Output selection signal input unit 221 ... X address input unit 222 ... Y address input unit 230 ... X decoder 231 to 234 ... Read line 240 ... Memory cell batch selection circuit 241-244 ... .... Writing line 270 ... Test input section

Claims (1)

[Claims] 1. An X-decoder in which a plurality of memory cells are arranged in a matrix to form a memory cell array, and a memory cell column can be written according to an address signal, and a memory designated by the address signal in the memory cell column. In a semiconductor device having a data input designation switching circuit for writing desired data in a cell and a memory cell batch selection circuit for collectively writing the memory cells, two memory cell rows are provided for each memory cell row. Data input lines of the memory cell row, adjacent memory cells are alternately connected to another data input line of the two data input lines in the memory cell row,
Each of the two data input lines has a path for transmitting desired input data in two positive logic and a path selection circuit for selecting a path for transmitting test data different from the input data. The data is constituted by a test logic selection circuit that selects a path for inputting data of common logic to the two data input lines and a path for inputting data of different logic.