JP2974219B2 - Test circuit for semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor memory device, and more particularly to a circuit built in a semiconductor memory device for testing whether or not the semiconductor memory device is normal. .

[0002]

2. Description of the Related Art Dynamic random access memory (hereinafter referred to as DRAM) has been increasing its integration density almost four times every three years. Currently, 4 Mbit DRAMs are in mass production, and 16 Mbit and even 64 Mbit DRAMs are under development. On the other hand, DRA
As the storage capacity of M increases, the time for testing whether the DRAM is normal or not has increased significantly, and the resulting increase in product cost has become insignificant.
Therefore, bit information is simultaneously written into a plurality of memory cells of the DRAM, the plurality of written bit information is simultaneously read, a logical operation is performed on the read bit information at the same time, and the result of the logical operation is output. A test circuit for testing whether writing or reading has been correctly performed based on a value has been incorporated in a semiconductor memory device. With this test circuit, a plurality of memory cells can be tested at the same time, so that the test time can be greatly reduced.

A DRA incorporating a test circuit as described above
One example of M is shown in FIG. The DRAM shown in FIG. 12 is disclosed in U.S. Pat. No. 4,860,259.
When operating in the normal mode, the test enable signals TE and / TE are set to L level and H level, respectively. When operating in the test mode, the test enable signal T
Let E and / TE be H level and L level respectively.

Various methods have been proposed for switching the test mode by setting the test enable signals TE and / TE to H level and L level, respectively. For example, WCBR (/ WE, / CAS before) as shown in FIG. / RAS) at a timing referred to as a row address strobe signal / RAS and a column address strobe signal / RAS.
In some cases, when the CAS and the write enable signal / WE change, the test mode is entered from the normal mode. That is, the test mode is entered when the column address strobe signal / CAS and the write enable signal / WE are set to L level before the row address strobe signal / RAS falls. In the normal mode, the column address strobe signal / CAS and the write enable signal / WE are not both set to the L level before the row address strobe signal / RAS falls. At this time, the test enable signal TE output from the clock generator 14 goes high and the test enable signal / TE goes low.

On the other hand, CBR (/ CA) as shown in FIG.
When the row address strobe signal / RAS and the column address strobe signal / CAS change at a timing called (S before / RAS), the mode returns from the test mode to the normal mode. That is, the write enable signal / WE
Is at H level, and row address strobe signal / R
Column address strobe signal / C before AS falls
When AS goes low, the test enable signal TE output from the clock generator 14 goes low and the test enable signal / TE goes high.

Next, the operation of the semiconductor memory device shown in FIG. 12 will be described.

(1) Operation in Normal Mode In the semiconductor memory device shown in FIG. 12, reading and writing are performed in the normal mode as follows.

First, at the time of reading, the address signal Add is
(Including row address signal and column address signal)
Is supplied to the decoder 1. Decoder 1 decodes, for example, the most significant bit of the row address signal and the most significant bit of the column address signal among applied address signals Add, and outputs, for example, four on / off control signals. These on / off control signals are output from the transistor 4a
To 4d, and these transistors 4a
To 4d are turned on. On the other hand, decoder 1 decodes the remaining row address signal and column address signal, and supplies the decoded output to memory cell array 5. Memory cell array 5 includes a plurality of memory cells arranged in a matrix. The memory cell array 5 is divided into a plurality of sub-arrays, that is, four sub-arrays 5a to 5d in FIG. Decoder 1
, Bit information is read from the memory cells corresponding to each other in sub-arrays 5a-5d, and applied to read amplifiers 6a-6d, respectively. As described above, only one of the transistors 4a to 4d is on. Therefore, only one of the four pieces of bit information read from each of subarrays 5a to 5d is transmitted to node N6 via one of read amplifiers 6a to 6d. In the normal mode, as described above, since test enable signal / TE is at H level and test enable signal TE is at L level, transistor 8 is on and transistor 9 is off. Therefore, the bit information transmitted to the node N6 is output to the external output pin _DOUT via the output buffer 7.

At the time of writing, 4 output from decoder 1
With one on / off control signal (the most significant bit of the row address signal and the most significant bit of the column address signal are decoded and output), only one of the transistors 2a to 2d is turned on. At this time, since the test enable signal TE is at L level, the transistor 3a
3d are all in the off state. Therefore, the bit information input from the external input pin D _IN is supplied to one of the sub-arrays 5a to 5d via the input buffer 10 activated by the signal W which becomes H level at the time of writing. On the other hand, in each of sub-arrays 5a to 5d, one corresponding memory cell is selected by the decode output supplied from decoder 1. Therefore, the bit information is written to the selected memory cell of the subarray to which the bit information is supplied.

(2) Operation in test mode
The semiconductor memory device shown in FIG. 2 operates as follows in the test mode.

First, at the time of writing in the test mode, the test enable signal TE goes high, so that all the transistors 3a to 3d are turned on. Therefore, the bit information input from the external input pin D _IN is supplied to all of the sub-arrays 5a to 5d via the input buffer 10. In each of the sub-arrays 5a to 5d, the supplied bit information is simultaneously written into the memory cell selected by the decode output of the decoder 1, that is, the corresponding four memory cells.

At the time of reading, the bit information stored from the corresponding four memory cells of each of subarrays 5a to 5d selected by the decode output of decoder 1 is simultaneously read. The bit information read from the selected memory cell of each of sub-arrays 5a to 5d is applied to read amplifier 6a, respectively.
Through 6d to one input terminals of exclusive OR gates 12a to 12d. The 4-bit information read at this time is the information written simultaneously to the corresponding memory cells of each of sub-arrays 5a to 5d. On the other hand, expected value data having the same logic as the write data when the 4-bit information is written is input to the external input pin D _IN . The expected value data is supplied to the other input terminals of the exclusive OR gates 12a to 12d via the input buffer 11 activated by the signal R which becomes H level at the time of reading. Therefore, if the written information is correctly read, the outputs of exclusive OR gates 12a to 12d all become L level. Exclusive OR gates 12a to 12d
Are further input to the OR gate 13. Therefore, if the written information is correctly read,
The output of the OR gate 13 also becomes L level. here,
Since test enable signal / TE is at L level and test enable signal TE is at H level, transistor 8
Are off, and the transistor 9 is on.
Therefore, the output of the OR gate 13 is connected to the external output pin D
Output to _OUT . That is, when the semiconductor memory device is operating normally, an L-level signal is output to the external output pin D _OUT . If at least one of the memory cells corresponding to each of the sub-arrays 5a to 5d has inverted data, at least one output of the exclusive OR gates 12a to 12d becomes H level, and the output of the OR gate 13 also becomes It becomes H level. Therefore, when the semiconductor memory device malfunctions, an H-level signal is output to the external output pin D _OUT .

As described above, in the test mode, the memory operation of a plurality of bits can be simultaneously tested by determining the level of the output signal of the external output pin D _OUT .

However, in the test circuit shown in FIG. 12, it is only known that one of the corresponding memory cells of each of the sub-arrays 5a to 5d has an abnormality. There was a problem that it could not be determined.

Therefore, a test circuit capable of solving the above-mentioned problems is disclosed in Japanese Patent Application Laid-Open No. 63-241791. In the test circuit disclosed in this publication, outputs corresponding to the exclusive OR gates 12a to 12d shown in FIG. 12 are input in parallel to a shift register circuit, and are temporarily sent to each latch circuit constituting the shift register circuit. It is stored. Thereafter, the latch circuits are connected in series and sequentially shift the information stored and held. The serial output of the shift register circuit is supplied to an external output pin. Therefore, the exclusive OR gates 12a to 12d in FIG.
Is output serially.

[0016]

Problems to be Solved by the Invention JP-A-63-2417
The test circuit disclosed in JP-A-91-91 serially outputs the test determination result of each sub-array from an external output pin, and thus can know which of the sub-arrays has an abnormality in the memory cell. However, in the test circuit disclosed in JP-A-63-241791, the test result of each sub-array must be temporarily latched by each latch circuit of the shift register circuit, so that the output of the test result is delayed by that amount. There was another problem that it would. Also, JP-A-63-241791
In the test circuit disclosed in the publication, after each latch circuit constituting the shift register circuit takes in the test determination result of each sub-array, the connection of each latch circuit must be changed in series. Therefore, a switch circuit for switching the connection state must be provided at the input terminal of each latch circuit. Therefore, there is a problem that the configuration becomes complicated and the operation becomes complicated for controlling each switch circuit.

Therefore, it is an object of the present invention to obtain more detailed test result data from a single output pin, output test results at a high speed, and perform a complicated control operation with a simple structure. An object of the present invention is to provide a test circuit for a semiconductor memory device that is not required.

[0018]

A test circuit for a semiconductor memory device according to a first aspect of the present invention is a circuit for testing a semiconductor memory device having a memory cell array divided into a plurality of sub-arrays. Means, read means, logical operation means, a single output node, a plurality of switch means, and switch control means. The writing means writes the bit information of the same logic to the memory cells corresponding to each other in each subarray. The arithmetic unit reads stored information in parallel from the memory cells corresponding to each other in each sub-array to which writing has been performed by the writing unit. The logical operation means is
A predetermined logical operation process is performed on the storage information of the memory cells corresponding to each other in the sub-arrays read by the reading means, and a plurality of logical operation results of a plurality of bits smaller than the number of the ab arrays are output in parallel. The bit of the logical operation result indicates a good / bad test result of the memory cell from which the storage information has been read by the reading means. The single output node outputs each bit of the multi-bit logical operation result output by the logical operation means to the outside. The plurality of switch means are interposed between each of the plurality of bits output by the logical operation means and a single output node. The switch control means sequentially turns on the plurality of switch means and sequentially applies the multi-bit logical operation result of the logic operation means to a single output node. A test circuit for a semiconductor memory device according to a second aspect of the present invention is a circuit for testing a semiconductor memory device including a memory cell array divided into a plurality of sub-arrays. Means, a single output node, a plurality of switch means, and switch control means. The writing means writes the same logical bit information to each of the memory cells corresponding to each other in each subarray. The reading means reads stored information in parallel from the memory cells corresponding to each other in each of the sub-arrays which have been written by the writing means. Each of the plurality of determination means is provided corresponding to at least two of the plurality of sub-arrays and less than all of the plurality of sub-arrays, and stores the memory cells read from the corresponding sub-array among the memory cells read in parallel by the reading means. Judgment of information match / mismatch is performed, and information representing the result of the judgment is output in parallel with each other. The number of the determination means is smaller than the number of the subarrays and is two or more. The single output node outputs each bit of the determination result of the plurality of bits output by the determination means to the outside. The plurality of switch means are interposed in parallel with each other between the plurality of determination means and the single output node. The switch control means sequentially turns on the switch means and applies serially the multi-bit determination results of the plurality of determination means to a single output node.

[0019]

According to the present invention, the switch control means sequentially and selectively turns on each switch means, so that the logical operation means outputs a plurality of bits of parallel data.
Serially applied to a single output pin.

Therefore, a more detailed test result can be obtained from the output node corresponding to a single output pin than the test result obtained in the conventional semiconductor memory device shown in FIG. At this time, the result of the pass / fail judgment of the memory cell is shown in units of a plurality of sub-arrays, and the information for specifying the sub-array in which the completely defective memory exists is not impaired. The sub-array in which the defective memory cell exists can be specified in units, and similarly, a more detailed test result can be obtained than in the configuration of the conventional semiconductor memory device. At this time, since the degenerate data is output from the switch means, the number of judgment result data or test result data to be read is reduced, the time for reading the judgment result data from the test result data is reduced, and the test result is reduced. Time is reduced. The output of the logical operation means or the judgment means does not need to be temporarily latched in the latch circuit of the shift register circuit as in the test circuit disclosed in Japanese Patent Application Laid-Open No. Can be output. Further, since a switch circuit for switching the connection state of each latch circuit included in the shift register circuit is not required, the configuration is simple and the control operation is also simplified.

[0021]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. The configuration of the embodiment shown in FIG.
The configuration is the same as that of the conventional semiconductor memory device shown in FIG. 12 except for the following points. Corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

The embodiment shown in FIG. 1 is different from the conventional semiconductor memory device shown in FIG. 12 in that at the time of reading in a test mode, on / off of transistors 18a to 18d is controlled by the output of shift register 15, The point is that the outputs of the exclusive OR gates 12a to 12d are serially output to the external output pin D _OUT . The operation of the shift register 15 is controlled by a shift register reset circuit 16 and a shift clock generator 17. The shift register reset circuit 16 generates a reset signal SRR based on a column address strobe signal / CAS and a row address strobe signal / RAS input from the outside, and supplies the reset signal SRR to each latch circuit in the shift register 15. The shift clock generator 17
Externally applied column address strobe signal / C
Based on AS and test enable signal TE provided from clock generator 14, shift clock signal φ,
/ Φ is generated and supplied to the shift register 15. Shift register 15 performs a shift operation in synchronization with shift clock signals φ and / φ supplied from shift clock generator 17.

In the embodiment shown in FIG. 1, in the normal mode, the clock generator 14 sets the test enable signal TE to the L level based on the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal / WE. Set the test enable signal / TE to H
Level, and the write operation and the read operation are described in FIG.
2 is performed similarly to the conventional semiconductor memory device shown in FIG.

On the other hand, in the test mode, clock generator 14 sets test enable signal TE to H level and test enable signal / TE based on row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE. Is set to L level.
At the time of writing in the test mode, each of the sub-arrays 5a to 5a is similar to the conventional semiconductor memory device shown in FIG.
The same logic bit information is written to the corresponding memory cell of 5d.

In the embodiment shown in FIG. 1, at the time of reading in the test mode, like the conventional semiconductor memory device shown in FIG. 12, bit information is read from corresponding memory cells of each of sub-arrays 5a to 5d, and these read-out are performed. A match / mismatch between the bit information and expected value information (information of the same logic as the bit information written to each memory cell selected at that time) input from the external input pin D _IN is determined by each exclusive logic. The determination is made by the sum gates 12a to 12d. At this time, first, the first output N1 of the shift register 15 becomes H level, whereby the transistor 18a is turned on. Therefore, the output of the exclusive OR gate 12a is supplied to the transistor 9 via the transistor 18a. Next, the second output N2 of the shift register 15 becomes H level by the shift operation, whereby the transistor 18b is turned on. Therefore, the output of the exclusive OR gate 12b is supplied to the transistor 9 via the transistor 18b. Hereinafter, similarly, the outputs of the exclusive OR gates 12c and 12d are sequentially output to the transistor 9
Supplied to In the test mode, the transistor 9 is on because the test enable signal TE is at the H level. Therefore, each exclusive OR gate 1
The outputs 2a to 12d are serially output to the external output pin D _OUT via the transistor 9.

The shift register 15 is configured, for example, as shown in FIG. As shown in FIG. 2, the shift register 15 includes eight ratio-type latch circuits L1 to L8, and these latch circuits L1 to L8 are connected in series with each other via transistors 19 to 26. Of these transistors 19 to 26, transistor 19,
The shift clock signal φ is supplied from the shift clock generator 17 to each gate of 21, 23, and 25, and the shift clock signal / φ is supplied from the shift clock generator 17 to each gate of the transistors 20, 22, 24, and 26. Is done. Also, the even-numbered latch circuits L2, L4, L6, L
8 are connected to inverters IN1, IN2, IN3, IN
4 are supplied to the gates of the transistors 18a to 18d in FIG. 1 as first to fourth outputs N1 to N4 of the shift register 15. Transistors 40 to 4 whose respective gates are supplied with the reset signal SRR from the shift register reset circuit 16 are provided on the input sides of the odd-numbered latch circuits L1, L3, L5, L7.
3 is connected to one of the conduction terminals. Latch circuit L1
The other conduction terminal of the transistor 40 connected to is connected to ground. The other conduction terminals of the transistors 41 to 43 connected to the other latch circuits L3, L5, L7 are connected to the power supply voltage Vcc.

The shift register reset circuit 16 in FIG. 1 is configured, for example, as shown in FIG. As shown in FIG. 3, the shift register reset circuit 16
It includes a flip-flop 46 formed by cross-connecting D gates 44 and 45, AND gates 47 and 48, a delay circuit 49, and an inverter 50. The AND gate 48 receives a row address strobe signal / RAS and a column address strobe signal / CAS. The output of the AND gate 48 is directly applied to one input terminal of the NAND gate 45 and the delay circuit 4
9, after being delayed by the inverter 50,
The signal is supplied to one input terminal of the AD gate 44. The output of NAND gate 45 and the output of AND gate 48 are applied to AND gate 47. The output of the AND gate 47 is the output of the shift register reset circuit 16.

In the shift register reset circuit shown in FIG. 3, when the output of NAND gate 44 is at L level and NA
Consider an operation when the row address strobe signal / RAS and the column address strobe signal / CAS are both at the H level while the output of the ND gate 45 is at the H level. In this case, the output of the AND gate 48 becomes H level and is input to the NAND gate 45. However, the output of the H level of the AND gate 48 is
9, the output of the inverter 50 is still at the H level. Therefore, the output of NAND gate 44 remains at L level and the output of NAND gate 45 remains at H level. Therefore, an H level signal is supplied to the AND gate 47 from the NAND gate 45 and the AND gate 48, and the output of the AND gate 47 is at the H level. After that, the output of the inverter 50 becomes L level. Accordingly, the output of NAND gate 45 goes low, and as a result, the output of AND gate 47 goes low. Therefore, row address strobe signal / RA
When the S, column address strobe signal / CAS goes high, the output of the AND gate 47, that is, the output of the shift register reset circuit 16, goes high for a predetermined time. That is, row address strobe signal / RA
When the S, column address strobe signal / CAS goes high, the reset signal SRR is activated for a predetermined time.

The shift clock generator 17 in FIG.
Is configured, for example, as shown in FIG. The shift clock generator 17 shown in FIG.
A D gate 52 and an inverter 53 are provided. NAN
A test enable signal TE is supplied to one input terminal of the D gate 52 from the clock generator 14 in FIG. The other input terminal of the NAND gate 52 is supplied with an inverted signal of the column address strobe signal / CAS from the inverter 51. The output of NAND gate 52 is supplied to shift register 15 shown in FIGS. 1 and 2 as shift clock signal / φ. The output of the NAND gate 52 is supplied to the shift register 15 shown in FIGS. 1 and 2 as a shift clock signal φ after being inverted by the inverter 53. In the test mode, test enable signal TE is at H level, so that when column address strobe signal / CAS is at H level, NAN
The output of D gate 52, that is, shift clock signal / φ goes high, and the output of inverter 53, ie, shift clock signal φ goes low. Conversely, when column address strobe signal / CAS is at L level, shift clock signal / φ is at L level and shift clock signal φ is at H level.

FIG. 5 is a timing chart showing the operation in the test mode of the embodiment shown in FIG. FIG. 6 is a timing chart showing a more detailed operation of the read operation (the portion marked as READ in FIG. 5) in the test mode. Since the feature of the present invention lies in the read operation in the test mode, this operation will be described in detail below with reference to the timing charts of FIGS. As described above, when both the column address strobe signal / CAS and the row address strobe signal / RAS become H level, the shift register reset circuit 16
The reset signal SRR is set to an active level (H level) for a predetermined time. The shift clock generator 17 sets the shift clock signal / φ to the H level and the shift clock signal φ to the L level when the column address strobe signal / CAS is at the H level, and sets the column address strobe signal /
When CAS is at L level, shift clock signal / φ is
The level and shift clock signal φ are set to H level.

When both row address strobe signal / RAS and column address strobe signal / CAS attain H level, shift register reset circuit 16 sets reset signal SRR to active level (H level) as described above. The activated reset signal SRR is supplied to each gate of the transistors 40 to 43 shown in FIG. Therefore, the transistors 40 to 43 are turned on, and an L-level signal is supplied to the input side of the latch circuit L1 and an H-level signal is supplied to the input sides of the other latch circuits L3, L5, and L7. At this time, since column address strobe signal / CAS is at the H level, shift clock signals φ and / φ generated from shift clock generator 17 are provided.
Are at L level and H level, respectively. Therefore, transistors 20, 22, 24, 26 in FIG.
Is on. Therefore, the latch circuit L
2, L4, L6, and L8 are latch circuits L1, L2, respectively.
The data held in L3, L5, and L7 is fetched.
Therefore, the output of the latch circuit L2 goes low and the outputs of the latch circuits L4, L6, L8 go high. Therefore, the output N1 of the inverter IN1 goes high and the outputs N2 to N4 of the other inverters IN2 to IN4 go low. Therefore, the transistor 18a in FIG. 1 is turned on.

Next, row address strobe signal / RA
When S falls to L level, row address signal 27 (see FIGS. 5 and 6) is taken into decoder 1, and when column address strobe signal / CAS falls to L level, column address signal 28 (see FIG. 5, see Figure 6)
Is taken.

At this time, in response to the fall of column address strobe signal / CAS, shift clock signal φ goes high and / φ goes low. Therefore, the transistors 19, 21, 23, and 25 in FIG. 2 are turned on, and the transistors 20, 22, 24, and 26 are turned off. As a result, the inverted signal of the output of the latch circuit L8, that is, the signal of L level is output to the output terminal of the latch circuit L1, the inverted signal of the output of the latch circuit L2, that is, the signal of H level is output to the output terminal of the latch circuit L3, and the latch circuit L4 Of the latch circuit L
5, an inverted signal of the output of the latch circuit L6, that is, an L-level signal is latched at the output terminal of the latch circuit L7. At this time, transistors 20, 22,
Since inverters 24 and 26 are off, inverters IN1 to IN1
The outputs N1 to N4 of IN4 do not change.

Therefore, the output of the exclusive OR gate 12a, that is, the test decision result of the selected memory cell in the subarray 5a is turned on because the test enable signal TE is at the H level. ) Is output to the external output pin _DOUT . At this time, the external output pin D _O
The test determination result output to the _UT is indicated by reference numeral 30 in FIGS.

Next, a column address strobe signal / C
When AS rises to the H level, the shift clock signal φ
Changes to the L level and / φ changes to the H level, the transistors 20, 22, 24, and 26 are turned on, and the transistors 19, 21, 23, and 25 are turned off. Therefore, an inverted signal of the output of the latch circuit L1, that is, a signal at the H level is output to the output terminal of the latch circuit L2.
3, the inverted signal of the output of the latch circuit L5, the inverted signal of the output of the latch circuit L5, the inverted signal of the output of the latch circuit L6, and the inverted signal of the output of the latch circuit L7. That is, the H-level signal is latched at the output terminal of the latch circuit L8.
As a result, the output N2 of the inverter IN2 goes high, and the outputs N1, N3, N4 of the other inverters IN1, IN3, IN4 go low. That is, the H-level signal is shifted by one stage. As a result, the transistors 18a, 18c, and 18d are turned off, and the transistor 18b is turned on. As a result, the output of the exclusive OR gate 12b is output to the external output pin D _OUT as indicated by reference numeral 31 in FIGS. Similarly, each time the column address strobe signal / CAS rises to the H level, the output of the exclusive OR gates 12c and 12d is output from the external output pin D _OUT (reference numerals 32 and 33 in FIGS. 5 and 6). Signal).

FIG. 7 is a block diagram showing the configuration of the second embodiment of the present invention. The second embodiment differs from the first embodiment shown in FIG. 1 in that the outputs of the exclusive OR gates 12a and 12b are input to the OR gate 35 and the exclusive Logical OR gate 12
By inputting the outputs of c and 12d to the OR gate 36, the test determination results of the sub-arrays 5a and 5b are reduced to one and the test determination results of the sub-arrays 5c and 5d are reduced to one. . That is, if any of the memory cells in the sub-arrays 5a or 5b has an abnormality, the output of the OR gate 35 goes high, and if any of the memory cells in the sub-arrays 5c and 5d has an abnormality,
The output of the OR gate 36 becomes H level.

The outputs of the OR gates 35 and 36 are connected to the transistors 37 and 38 controlled by the outputs N7 and N8 of the shift register 34, the transistor 9 controlled by the test enable signal TE, and the output buffer 7. It is supplied to the external output pin D _OUT through the external output pin D _OUT .

As the shift register 34 in FIG. 7, for example, a two-stage shift register as shown in FIG. 8 is used. Other configurations of the embodiment shown in FIG. 7 are the same as those of the embodiment shown in FIG. 1, and the corresponding parts are denoted by the same reference numerals and description thereof will be omitted.

FIG. 9 is a timing chart showing a read operation in the test mode of the embodiment shown in FIG.
As is clear from FIG. 9, the embodiment shown in FIG.
The operation is basically the same as that of the embodiment shown in FIG. 1 except that the number of stages of the shift register is reduced. In FIG. 9, a signal indicated by reference numeral 391 is a test judgment result output of the sub-arrays 5a and 5b, and a signal indicated by reference numeral 40.
A signal indicated by 1 is a test determination result output of the sub-arrays 5c and 5d.

In the embodiment shown in FIG. 7, the amount of information of test decision result data output to the outside is smaller than that in the embodiment shown in FIG. 1 is shorter than that of the embodiment shown in FIG.

FIG. 10 is a block diagram showing the configuration of the third embodiment of the present invention. The embodiment shown in FIG. 10 differs from the embodiment shown in FIG. 1 in the following points. That is, in the embodiment shown in FIG. 10, the outputs of the read amplifiers 6a and 6b, that is, the bit information read from the sub-arrays 5a and 5b are input to the exclusive OR gate 135, and the outputs of the read amplifiers 6c and 6d, that is, the sub-array 5c, The bit information read from 5d is input to the exclusive OR gate 136. That is, in the embodiment shown in FIG.
The exclusive OR gates 135 and 136 determine the coincidence / mismatch of the logics of the bit information read at the same time, so that the test is performed, and the expected value data is not used. The outputs of the exclusive OR gates 135 and 136 are connected to the external output pin D via transistors 37 and 38 controlled by the outputs N7 and N8 of the shift register 34, the transistor 9 controlled by the test enable signal TE, and the output buffer 7. Supplied to _OUT . In addition,
The configuration of the shift register 34 is similar to the configuration of the shift register 34 in FIG. 7, and for example, is configured as shown in FIG. Other configurations of the embodiment shown in FIG.
This embodiment is the same as the embodiment shown in FIG. 1, and the corresponding parts are denoted by the same reference numerals and the description thereof will be omitted.

FIG. 11 is a timing chart showing a read operation in the test mode of the embodiment shown in FIG. As is apparent from FIG. 11, the read operation in the test mode of the embodiment shown in FIG. 10 is performed in the same manner as in FIG. 7 except that expected value data is not input from external input pin D _IN .
Is exactly the same as that of the embodiment shown in FIG.

In the embodiment shown in FIG. 10, as in the embodiment shown in FIG. 7, the information amount of the test decision result data extracted to the outside is smaller than that in the embodiment shown in FIG. The time required for reading is shorter than that of the embodiment shown in FIG. 1 by the reduced amount of information of the test determination result data. Further, in the embodiment shown in FIG. 10, since it is not necessary to input expected value data from the outside in the test mode, control in the test mode is simplified.

In the three embodiments described above, the memory cell array is divided into four sub-arrays. However, the number of divisions is not limited to four, and can be arbitrarily changed according to the situation. In each of the above embodiments, the present invention is applied to a DRAM.
, But is not limited to this,
The present invention can be applied to a test of a semiconductor memory device other than a DRAM.

[0045]

As described above, according to the present invention, a predetermined logical operation is performed on the storage information read from the selected memory cell of each subarray, and the result of the logical operation is simply and serially obtained. Since the data is supplied to one output pin, more detailed test determination result data can be obtained than in the conventional semiconductor memory device shown in FIG.

Further, according to the present invention, when outputting the result of the logical operation means or the judgment means, that is, the test judgment result data, the respective switch means are sequentially and selectively turned on, thereby providing a single output pin. (Output node)
The test decision result data can be output at a higher speed than a conventional test circuit that temporarily latches the test decision result data in the shift register circuit and then shifts out the data,
A test circuit having a simple configuration and a simple control can be obtained. The number of output bits of the logical operation or determination means is smaller than the number of subarrays and is two or more, and a plurality of memory cell good / defective data are degenerated, and the number of test determination result data to be output is reduced. This is reduced compared to the configuration using a conventional shift register circuit, and the time required for test data reading can be reduced. Further, since the test result data is not degenerated into 1-bit data, the information for specifying the sub-array in which the defective memory cell is present is not completely damaged, and the sub-array in which the defective memory cell is present is identified in units of this degenerate data bit. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a more detailed configuration of a shift register in FIG. 1;

FIG. 3 is a circuit diagram showing a more detailed configuration of a shift register reset circuit in FIG. 1;

FIG. 4 is a circuit diagram showing a more detailed configuration of a shift clock generator in FIG. 1;

FIG. 5 is a timing chart showing an operation in a test mode of the embodiment shown in FIG. 1;

FIG. 6 is a timing chart showing a read operation in a test mode of the embodiment shown in FIG. 1 in more detail;

FIG. 7 is a block diagram showing a configuration of a second embodiment of the present invention.

8 is a circuit diagram illustrating a more detailed configuration of a shift register in FIG. 7;

9 is a timing chart showing in detail a read operation in a test mode of the embodiment shown in FIG. 7;

FIG. 10 is a block diagram showing a configuration of a third embodiment of the present invention.

11 is a timing chart showing in detail a read operation in a test mode of the embodiment shown in FIG. 10;

FIG. 12 is a block diagram showing an example of a configuration of a conventional semiconductor memory device having a built-in test circuit.

13 is a timing chart showing a switching operation from a normal mode to a test mode in the conventional semiconductor memory device shown in FIG.

14 is a timing chart showing a switching operation from a test mode to a normal mode in the conventional semiconductor memory device shown in FIG.

[Explanation of symbols]

1 is a decoder, 2a to 2d, 3a to 3d, 4a to 4d are transistors, 5 is a memory cell array, 5a to 5d are subarrays, 12a to 12d, 135, and 136 are exclusive OR gates, 18a to 18d, 37, and 38 Denotes a transistor for outputting a test determination result, 15 and 34 denote shift registers, and 17 denotes a shift clock generator.

Claims (2)

(57) [Claims] 1. A circuit for testing a semiconductor memory device having a memory cell array divided into a plurality of sub-arrays, wherein a write circuit for writing bit information of the same logic to each of the memory cells corresponding to each other in each of said sub-arrays. Writing means; reading means for reading stored information in parallel from memory cells corresponding to each other in each of the sub-arrays written by the writing means; and reading means corresponding to each of the sub-arrays read by the reading means. Logic operation means for performing a predetermined logical operation process on the storage information of the memory cell and outputting in parallel a plurality of bits of the logical operation result smaller than the number of the sub-arrays, wherein the logical operation result bit is A test result of the memory cell from which the storage information is read by the read means, and A single output node for outputting each bit of the logical operation result of the bit to the outside, and a plurality of bits respectively interposed between each bit of the plurality of bits output by the logical operation means and the single output node Switch means, and switch control means for serially applying the multi-bit parallel logical operation result of the logical operation means to the single output node by sequentially turning on each of the switch means, Test circuit for semiconductor memory device. 2. A circuit for testing a semiconductor memory device having a memory cell array divided into a plurality of sub-arrays, wherein a write circuit for writing bit information of the same logic to each of the memory cells corresponding to each other in each of the sub-arrays. Reading means for reading stored information in parallel from the memory cells corresponding to each other in each of the sub-arrays which have been written by the writing means, each of which is smaller than all of the plurality of sub-arrays and at least two or more. Of the memory cells read from the sub-array corresponding to the storage information of the memory cells read in parallel by the read means, and determines whether or not the bits representing the determination result are identical to each other. A plurality of judging means smaller than the number of the sub-arrays output in parallel; and a plurality of bits output by the plurality of judging means. A single output node for outputting each bit of the fixed result to the outside; a plurality of switch means interposed between each of the determination means and the single output node; and A switch control unit for serially applying a plurality of bit determination results from the plurality of determination units to the single output node as an on-state as an alternative, and a switch control unit.