KR920005164A - Test circuit of semiconductor memory - Google Patents

Abstract

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Description

Test circuit of semiconductor memory

As this is a public information case, the full text was not included.

1 is a block diagram showing the configuration of a first embodiment of this invention;

2 is a diagram showing a more detailed configuration of a shift register in FIG.

3 is a circuit diagram showing a more detailed configuration of a shift transistor reset circuit in FIG.

4 is a circuit diagram showing a more detailed configuration of a shift clock generator in FIG.

5 is a timing chart showing an operation in the test mode of the embodiment shown in FIG.

6 is a timing chart showing the read operation in more detail in the test mode of the embodiment shown in FIG.

7 is a block diagram showing the construction of a second embodiment of this invention;

8 is a circuit diagram showing a more detailed configuration of a shift register in FIG.

9 is a timing chart showing in detail the read operation in the test mode of the embodiment shown in FIG.

Fig. 10 is a block diagram showing the construction of the embodiment of Fig. 3 of this invention.

FIG. 11 is a timing chart showing in detail the read operation in the test mode of the embodiment shown in FIG.

12 is a block diagram showing an example of the configuration of a conventional semiconductor memory device incorporating a test circuit.

FIG. 13 is a timing chart showing the switching operation from the normal mode to the test mode in the conventional semiconductor memory device shown in FIG.

FIG. 14 is a timing chart showing the switching operation from the test mode to the normal mode in the conventional semiconductor memory device shown in FIG.

* Explanation of symbols for main parts of the drawings

1: Decoder 2a ~ 2d, 3a ~ 3d, 4a ~ 4d: Transistor

5: Memory Cell Array 5a ~ 5d: Sub Array

12a ~ 12d, 135,136: exclusive logic gate

18a ~ 18d, 37,38: Transistor for output of test judgment result

15,34: shift register 17: shift clock generator

Claims (3)

A circuit for testing a semiconductor memory device having a memory array divided into sub-arrays of claim, comprising: writing means for writing bit information of the same logic into memory cells corresponding to each of the electric sub-arrays; Predetermined logical operations are performed on the reading means for reading the storage information from the memory cells of each of the electrically sub arrays to be rewritten, and the storage information of the memory cells of each of the electric sub arrays read by the electric reading means. Test results, and output the test results as parallel data of a plurality of bits; a single output pin for outputting the test result output of the electrical calculation means to the outside, and each bit of the output data of the electrical logic calculation means; A plurality of switch means sandwiched between a single electrical output pin and each electrical switch And a switch control means for sequentially and selectively turning on the means to apply the parallel data output of the electric logic operation means serially to an electric single output pin. The electric logic calculating means is a test circuit of the semiconductor memory device of claim 1, which outputs an electric test result output for each electric sub array. The test circuit of the semiconductor memory device according to claim 1, wherein the electric logic calculating means reduces the output of the electric test result to a plurality of numbers smaller than the number of the electric sub arrays. ※ Note: The disclosure is based on the initial application.