JP2913693B2 - Random access memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a random access memory formed on a semiconductor substrate.

[Prior art] Conventionally, this kind of random access memory (hereinafter simply referred to as
FIG. 6 is a circuit diagram of a RAM (abbreviated as Random Access Memory). FIG. 7 shows a decoder for selecting a cell in the memory cell array. A0 to An (A0 to Ak, Am to An) are addresses, Q0 to Qn are input / output data, are read signals, W is a write signal, and P is a precharge signal. 611 and 612 are decoders for selecting a memory cell array, and show a circuit diagram of the decoder 611 or 612 shown in FIG. 613 and 614 are P-channel transistors for precharge, 615 and 616 are N-channel transistors for selection by a signal from the decoder 612,
617 and 620 are P-channel transistors for write selectors, 618 and 619 are N-channel transistors for write selectors, 621 and 622 are P-channel transistors for read selectors, 623 and 624 are N-channel transistors for selecting memory cells, It is selected by a signal from the decoder 611. 625 and 626 are memory cell inverters, 631 and 632 are write selector inverter gates, 627 is a write selector NOR gate, and 628 is a write selector NAND gate.
29,630 is an inverter gate.

The operation method of this circuit will be described. First, when the precharge signal P is at the low level "0", the P-channel transistors 613 and 614 are turned on, and the output line of the RAM is in the precharge state and is at the high level "1". At this time, when the read signal and the write signal W are at the high level “1”, writing to the data RAM cell becomes possible. At this time, the outputs of the decoders 611 and 612 are all low level "0" (because the precharge signal P is input to the NAND gates (721 to 723)). Next, when the precharge signal P is at the high level "1", the decoders 611 and 612 depend on the address.
Is selected, the N-channel transistors 615 and 616 are turned on and the input data is sent to the data line of the memory cell, and the N-channel transistors 623 and 624 of the RAM cell are turned on and the input data on the data line is stored in the RAM.
Written to the inverter gate 625,626 of the cell. Next, when the write signal W is at the low level “0”, when the read signal changes from the high level “1” to the low level “0”, the data is written to the memory cell corresponding to the decoder that outputs the high level “1”. Data is output from RAM.

Here, in order to check for interference between adjacent cells, different data is written in a checkerboard pattern in adjacent memory cells to check for interference. In order to write the held data, in the decoder having the conventional configuration as shown in FIG. 7, only one output of the decoder outputs a high level "1" corresponding to the address. Was writing.

[Problems to be Solved by the Invention] In a test at the time of manufacture of a RAM, in order to eliminate a defect due to interference between cells adjacent to each other, a RAM is checked so that adjacent memory cells hold different data. It is necessary to confirm that the pattern is correctly written. In the above-described conventional RAM, in order to write the checkerboard pattern, it is necessary to write data while inverting the data to be written for each memory cell. Therefore, if you have a large amount of RAM, the time required to write this checkerboard is
The time required for writing to one memory cell is twice as large as the RAM capacity, so that the inspection time becomes extremely long and the cost required for the inspection becomes enormous.
This is disadvantageous in that as the memory capacity of the RAM increases, the test time increases significantly, and the test cost becomes very large.

[Differences of the Invention from the Prior Art] The present invention is different from the conventional RAM described above in that the output lines from the decoders for selecting the cells among the memory cells are simultaneously selected every other line, whereby the RAM is selected. Irrespective of the memory capacity of the memory cell, a checkerboard pattern can be written in all memory cells in a short time to check for interference failure between cells adjacent to the memory cell.

Means for Solving the Problems The gist of the present invention includes a memory cell array in which a plurality of memory cells are arranged in a matrix, and a decoder for selecting a memory cell in the memory cell array based on an address signal. Control means for controlling the decoder to simultaneously select the memory cells every other row or every other column in response to a control signal and the address signal, and an adjacent memory in the memory cell array. In order to make cell data different from each other, a first memory cell group selected simultaneously in every other row, a second memory cell group selected simultaneously in every other column, And a write circuit for writing data to the third memory cell group at the intersection selected simultaneously every other column.

Example Next, the present invention will be described with reference to the drawings. First
FIG. 2 is a circuit diagram of a RAM to which the present invention is applied, and FIG. 2 is a circuit diagram of a decoder according to the first embodiment of the present invention. A0
AnAn (A0〜Ak, Am〜An) are addresses, Q0〜Qn are output data, S1 and S2 are input signals for controlling the decoder, and S1 is an input signal for controlling the decoder 111. , S2
Is an input signal for controlling the decoder 112, is a read signal, W is a write signal, and P is a precharge signal. 111 and 112 are decoders for selecting cells in the memory cell array of the present invention, and FIG.
It is a circuit diagram of 1 or 112. 113 and 114 are P-channel transistors for precharge, 115 and 116 are N-channel transistors for selection by a signal from the decoder 112, 117 and 120 are P-channel transistors for write selector, and 118 and 119 are N-channel transistors for write selector Transistors 121 and 122 are P-channel transistors for read selector, and 12
Reference numerals 3 and 124 denote N-channel transistors for selecting memory cells, which are selected by a signal from the decoder 111. 125 and 126 are memory cell inverters, and 13
Reference numerals 1 and 132 denote inverters for the write selector, 127 denotes a transfer gate for the write selector, 128 denotes a NAND gate for the write selector, and 129 and 130 denote inverter gates.

In normal use, the decoder control input signals S1 and S2 in FIG. 1 are at high level "1", and when the outputs of the decoders 111 and 112 are at high level "1", the selection transistors 115, 116,
The 123 and 124 are turned on, and data is written to the inverter gate of the RAM cell composed of the inverters 125 and 126.

Next, at the time of inspection, writing is performed in the following procedure.
First, by inputting low level “0” to the input signals S1 and S2 for controlling the decoder and inputting high level “1” to all the addresses A0 to Ak, all the input signals to the logic circuit 220 in FIG. High level “1”. Therefore, the outputs of the logic circuit 220 are all high level "1", and the outputs (D0 to Dn) of the decoder are all high level "1". Thus, all the memory cells in the RAM are in the selected state, and writing can be performed at the same time.

Next, while the control input signals S1 and S2 of the decoder remain at the low level “0”, A0 of the addresses A0 to Ak is set to the low level “0”, and the other addresses (A1 to Ak) are set to the high level “1”. Then, since the low level “0” is input to the inputs to the NAND gates 221 and 223 in the logic circuit 220, the NAND gates 221 and 223 output the high level “1”. Therefore, the outputs of the decoder D0 and Dm (m is an even number) are low level "0", and D1 and Dn (n is an odd number) are high level "1". In this way, only the memory cells in the RAM connected to D1 and Dn are simultaneously selected and data can be written.

In the present invention, a checkered pattern is written in the following procedure. First,
The input signals S1 and S2 for controlling the decoder are set to low level “0”, and the addresses A0 to Ak and Am to An are all set to high level “1”.
By inputting, all memory cells are set to “0” or
The same data (initial data) of "1" is written (see FIG. 3A).

Next, the data to be written is set to the inverted data of the initial data, and all the addresses Am to An are input to the high level “1” while the input signals S1 and S2 for controlling the decoder remain at the low level “0”, and the address A0 The data is written to the memory cells on the odd-numbered output lines on the decoder 111 side by inputting A0 of A.about.Ak to a low level "0" and inputting a high level "1" for other addresses (A1 to Ak). Fig. (B).

Next, with the setting of the write data as it is,
All the addresses A0 to Ak are input to the high level “1” while the input signals S1 and S2 for controlling the decoder remain at the low level “0”, and Am of the addresses Am to An (Am is the least significant of the Am to An) Address is low level “0” and other addresses (Am + 1 to A
n) is a decoder 1 by inputting a high level “1”.
Data is written to the memory cells on the odd-numbered output lines on the twelfth side (see FIG. 3C).

Finally, the write data is set as inverted data (initial data) of the data, and the input signals S1, S
2 is kept at the low level “0”, A0 and Am of the addresses A0 to Ak and Am to An are set to the low level “0”, and the other addresses (A1 to Ak, Am +
1 to An) write data to memory cells on odd-numbered output lines of the decoders 111 and 112 by inputting a high level "1" (see FIG. 3D).

By arranging the decoder output signal line optimally with respect to the arrangement of the memory cells in the above procedure, the decoders 111 and 112 are each checked twice to check for interference failure between adjacent cells in a total of four write operations. Is completed.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram of a decoder according to a second embodiment of the present invention.

Low level “0” for the input signals S1 and S2 for controlling the decoder
Is input, A0 of the addresses A0 to Ak is input at a low level “0”, and the other addresses (A1 to Ak) are input at a high level “1”. As a result, since the low level “0” is input to the inputs to the NAND gates 421 and 423 in the logic circuit 420 in FIG. 4, the NAND gates 421 and 423 output the high level “1”. As for the output values of the decoder, D0 and Dm (m is an even number) become low level "0", and D1 and Dn (n is an odd number) become high level "1". Thus, only the memory cells of the RAM connected to D1 and Dn are selected and written simultaneously.

Next, the input to the NAND gates 422 and 423 in the logic circuit 420 is performed by inputting the high level “1” to all the addresses A0 to Ak while the input signals S1 and S2 for controlling the decoder remain at the low level “0”. , A low level “0” is input to the NAND gates 422 and 424, and the NAND gates 422 and 424 output a high level “1”. As for the output values of the X decoder, D0 and Dm (m is an even number) are at a high level "1", and D1 and Dn (n is an odd number) are at a low level "0". Thus, only the memory cells of the RAM connected to D0 and Dm are selected and simultaneously written.

In the present invention, a checkered pattern is written in the following procedure. First,
The input signals S1 and S2 for controlling the decoder are set to low level “0”, and the addresses A0 to Ak and Am to An are all set to high level “1”.
By inputting the data, data is written to the memory cells on the even-numbered output lines of the decoders 111 and 112 (see FIG. 5A).

Next, the input signals S1 and S2 for controlling the decoder are set to low level "0", A0 and Am of the addresses A0 to Ak and Am to An are set to low level "0", and the other addresses A1 to Ak and Am + 1 to An ) Is set to the high level “1”, thereby writing data to the memory cells on the odd-numbered output lines of the decoders 111 and 112 (see FIG. 5B).

Next, the input signals S1 and S2 for controlling the decoder are set to low level “0”, and all the addresses A0 to Ak are set to high level “1”.
Input, and Am of addresses Am to An is set to low level “0”,
By setting the other addresses (Am + 1 to An) to high level “1”, data is written to the memory cells on the even-numbered output lines of the decoder 111 and the odd-numbered output lines of the decoder 112 (FIG. 5 ( c)).

Next, the input signals S1 and S2 for controlling the RAM are set to low level “0”.
By inputting all of the addresses Am to An to a high level “1”, setting A0 of the addresses A0 to Ak to a low level “0” and setting the other addresses (A1 to Ak) to a high level “1”,
On the odd-numbered output lines of the decoder 111 and the decoder 112
Is written to the memory cells on the even-numbered output lines (see FIG. 5 (d)).

With the above procedure, a checkerboard pattern can be written.

[Effects of the Invention] As described above, the present invention conventionally requires a very long inspection time to write a checkerboard pattern for checking for interference failure between memory cells adjacent to a RAM, and also requires an inspection cost. The output line from the decoder for selecting the memory cell is selected simultaneously by the input signal input to the decoder for selecting the cell in the memory cell array. By setting the state, regardless of the memory capacity, a checkered pattern can be written to all the memory cells in a short time,
The inspection time can be greatly reduced, and the cost required for the inspection can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a RAM to which the present invention is applied, FIG. 2 is a circuit diagram of a decoder according to a first embodiment of the present invention, and FIG. 3 shows contents of a memory cell array in the first embodiment. FIG. 4 is a conceptual diagram showing a decoder circuit according to the second embodiment, FIG. 5 is a conceptual diagram showing the contents of a memory cell array in the second embodiment, FIG. 6 is a circuit diagram of a conventional RAM, FIG. 7 is a circuit diagram of a conventional decoder. 111,112,611,612 …… Decoder, 113,114, 613,614 …… P-channel transistor for precharge, 115,116, 123,124, 615,616, 623,624 …… N-channel transistor for decoder signal selector, 117,120, 617,620 …… P-channel type for write selector Transistors, 118, 119, 618, 619 ... N-channel transistors for write selectors, 121, 122, 612, 622 P-channel transistors for read selectors, 125, 126, 625, 626 ... Inverter gates of RAM cells, 129-132, 255-228, 411, 425-432 , 629,630-632, 711-714, 724-726 …… Inverter gate, 128,211-214, 221,222-224, 412-413, 421-424,628, 721-723 …… NAND gate, 119,619 …… NOR gate, S1, S2 … RAM control input signal, A0 to Ak, Am to An… Address, Q0 to Qn… I / O data,… Read signal, W… Write signal, P… Precharge signal, 210, 220, 410, 420, 710, 720 …… Logic circuit.

Claims (1)

(57) [Claims] A random access memory having a memory cell array in which a plurality of memory cells are arranged in a matrix and a decoder for selecting a memory cell in the memory cell array based on an address signal; Control means for controlling the decoder to simultaneously select the memory cells every other row or every other column in response to the address signal; and making the data of adjacent memory cells in the memory cell array different from each other. Therefore, the first memory cell group selected simultaneously every other row, the second memory cell group selected simultaneously every other column, and the intersection selected simultaneously every other row and every other column And a writing circuit for writing data to the third memory cell group.