JPS6364692A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To function a semiconductor memory device as a shift register by providing gate circuits between adjacent bit lines in memory cells in the direction of a word line and sequentially impressing control signals. CONSTITUTION:The gate circuits 40-4n are provided between adjacent inversed bit lines, the inverses of BLj and BLj+1, in the memory cells Mi,1-Mi,n in the direction of the word line WLi in a memory cell array 1, between a data input terminal 2 and an initial bit line BL1, and between a final inversed bit line, the inverse of BLn and an output terminal BLn. These circuits 40-4n sequentially respond to the control signals from a control signal supply circuit 5, and input data from the terminal 2 is sequentially outputted from the terminal 3 through the memory cells Mi,1-Mi,n. A semiconductor memory device functioning as a shift register as well is attainable.

Description

[Detailed Description of the Invention] [Summary] A semiconductor memory device in which a data input terminal (2) and a first bit line (BLI) are connected between adjacent bit lines between memory cells adjacent in the word line direction. Gate circuits (40, 43, . . . , 41) are provided between the line (BL1) and the data output terminal (3), and control signals (Sn , Sn,・
..., S7), it can be used not only in the normal RAM mode but also as a shift register.

[Industrial application field]

The present invention relates to semiconductor memory devices, and more particularly to semiconductor memory fabrication with a memory cell array having SRAM (static random access memory) cells at intersections of a plurality of word line and bit line pairs.

[Prior art and problems to be solved by the invention]

-i, when reading data from each memory cell in a semiconductor memory device, a word line is selected and the data of a plurality of cells connected to the word line are read from complementary bit lines connected to each of the cells. The signal is taken out through the pair and further through the sense amplifier. In this case, the data of a plurality of cells connected to the selected word line are output simultaneously, that is, in parallel.

Therefore, for example, when testing whether each memory cell operates normally, in one embodiment, a word line is first selected and the first memory cell connected to the word line is selected. It is necessary to write data in the first cell, and then test whether the written data is successively outputted normally. Moreover, such a test is also performed for each cell from the second cell onwards. There was a need. In another form, a word line is selected, data is written to a plurality of cells connected to the word line, and then the written data is transmitted in parallel via a complementary bit line pair and a sense amplifier. By extracting the extracted data one bit at a time via a shift register, for example, it is tested whether the data written in each memory cell has been read normally.

In other words, when testing each memory cell in a conventional semiconductor memory device, the former method requires time and effort, which is disadvantageous in terms of work efficiency, and the latter method is disadvantageous in terms of work efficiency. The present invention has been created in view of the above-mentioned problems in the conventional type, and has a relatively simple configuration. In addition to simplifying the work when testing memory cells, the original R
The object of the present invention is to provide a semiconductor memory device that can be used not only in AM mode but also as a shift register.

[Means for solving problems]

FIG. 1 shows a basic block diagram of a semiconductor memory device according to the present invention.

In FIG. 1, reference numeral 1 denotes a memory cell array, which includes a plurality of word lines WL1, WL1, . . . , WLm and bit line pairs BL1, 1. ..., BL1, TT.

It has an SRAM cell Mi+j at the intersection of the two. 2 is a terminal for inputting data from the outside, and 3 is a terminal for outputting data to the outside.

40, 4. , . . . , 41 is a gate circuit, and the gate circuit 4 is provided between adjacent bit lines between memory cells adjacent in the word line direction in the above-mentioned memory cell array 1.
0, 4□, ..., or 41, -+ are connected, and a gate circuit 40 is connected between the input terminal 2 and the first bit line BL.
A gate circuit 4 is connected between the final bit line BL1 and the output terminal 3. 5 is a control signal supply circuit which sequentially controls the gate circuits in accordance with the arrangement order of the gate circuits 40 to 4; II! Signals So, S+,
-, S-.

[For production]

In the semiconductor memory snow making of the present invention, the gate circuit 40 is
.about.4fi operate sequentially, thereby shifting the data of the memory cell or the data from the input terminal 2 in the word line direction so that the output signal of one of the adjacent gate circuits becomes the input signal of the other.

In this way, the device of the invention can be used as a shift register in addition to the original RAM mode, so that it can be used, for example, in the word line direction written in the normal RAM mode, without the need for additional circuitry. By serially extracting data from a plurality of cells one bit at a time using a shift register function, it is possible to easily test whether each memory cell is normal or not.

〔Example〕

FIG. 2 shows a circuit diagram of a semiconductor memory device as an embodiment of the present invention.

In the figure, 1 is a memory cell array, which has multiple SRs.
AM cell Mi,j (i=1 to 5.j=1 to 4) is 5
word lines WL, in a matrix of rows and four columns.

WLz, ......, WLm and bit line pair B
L+.

Ding τ1. ..., BL4. It is arranged at the intersection of BL and BL. FIG. 3 shows an equivalent circuit of each memory cell Mi, j. That is, data can be written or read into each memory cell M 1 + j by selecting the word line WL and turning on the N-channel transistors 31 and 32 for transfer gates. The signals appearing on each bit line pair BL and BL have levels that are inverted from each other due to inverters 33 and 34 interposed therebetween having mutually opposite directions.

Returning to FIG. 2, 20 is a row address decoder;
Based on the decoding of the address signal ADD, the word line 'vV
Select one from L+ to WL. 21 to 25 are drivers for activating the words yAW L l to W L s, respectively, and only the driver corresponding to the word line selected by the row address decoder 20 functions. Reference numeral 26 denotes a sense amplifier circuit, which amplifies the signal appearing on the bit line pair, that is, quickly pulls up the signal on the bit line on the high level side to the level of the power supply voltage, e.g. It has the function of quickly pulling down the line signal to, for example, zero level.

2 and 3 are terminals for inputting data from the outside and terminals for outputting data to the outside, respectively. A gate circuit 40 is connected between the data input terminal 2 and the bit line BL, and this gate circuit 40 includes an inverter 4a and an inverting tri-state buffer 4b. This inverting tri-state buffer 4b has a control terminal C0 for inputting a control signal s0, and when the control signal s0 is at a high level, the level of the input signal is inverted and output, and the control signal S0 is at a low level. It has the function of cutting off the input side and output side and putting the output side in a high impedance state when the level is high.

Therefore, when data of "1" is input to input terminal 2 when control signal S0 is at high level, bit line BL is set to "1".
” appears.Similarly, between !BL and the focus line BL2, between the bit line τ2 and the bit line BL,
between bit line BL) and bit line BL, and.

Between the output terminal τ4 and the output terminal 3, inverting tri-state buffers 41°4□, 45. are provided as gate circuits, respectively.
and 44 are connected. These tri-state buffers 4 and 44 receive control signals S+ and Sz, respectively.
, S3 and S4 for inputting control terminals C,,C2
, C3 and C4, and similarly to the inverting tri-state buffer 4b, the level of the input signal is inverted (ON operation) or the input side and the output side are A cutoff (OFF operation) is performed between.

Gate circuit 4. The reason why an inverted tri-state buffer is used as 44 is that the signals appearing on adjacent bit lines have mutually inverted levels and are returned to their original levels.

5 is a circuit for supplying control signals 80 to S4.

In this circuit, 51 is an input terminal for a shift clock SCK, and 52 is an input terminal for a switching signal between RAM mode and shift register mode, and this switching signal is at a high level when the shift register mode is selected. terminal 5
1 is connected to one input terminal of the AND gate 53 and also to the input terminal of the inverter 54 . Terminal 52 is connected to the other input end of AND gate 53 and to one input end of AND gate 55 . The output terminal of the inverter 54 is connected to the other input terminal of the AND gate 55. and gate 53
The output of becomes the control signal S0゜S2 and S4, while
The outputs of the AND gate 55 become control signals S1 and Sn.

If the normal RAM mode is selected at =i shown in FIG. S4 all go to low level, which puts all tri-state buffers in a high impedance state, and each bit line BL, ~B
L4 operates independently.

On the other hand, when the shift register mode is selected, that is, when a high level switching signal is applied to the terminal 52,
AND gate 5 according to the level of shift clock SCK
3 and 55 open their gates alternately, the control signals Sn, S2 and S4 or the control signals SI and Sn go high accordingly, thereby causing the tristate buffers 4b, 4z and 44 or the tristate buffers 4. and 4. opens each gate. When the shift register mode is selected, the normal RAM mode is prohibited, that is, in the configuration example shown in FIG. 2, the connection between the memory cell array 1 and the sense amplifier circuit 26 is cut off, and instead, the selected RAM cells connected to any word line can be serially connected through each tri-state buffer. Therefore, the data input from input terminal 2 is shifted by the shift clock SC.
Tri-state buffer 4b in response to X with K or D
, 41, 4□, 43 and 44 are every other 0N10F
By repeating the F operation, the data is sequentially shifted one bit at a time in the direction of the word line and output from the terminal 3.

In this way, a relatively simple circuit can be added to a normal SRAM device.
That is, gate circuits 40, 4+, 4□, 43 and 44
and a control signal S to the gate circuit. , S +, S z
.

By adding Sn and a circuit 5 for supplying Sn, the device can also be used as a shift register.

Therefore, by selecting an arbitrary word line and writing arbitrary data into a plurality of cells connected to the word line in the normal RAM mode, the written data is sequentially transferred one bit using the shift register function. - By serially taking out each memory cell from the output terminal 3, it is possible to simply test whether each memory cell is normal or not. For example, in FIG. 2, 4 bits of data can be stored per word line, but when reading out these 4 bits of data serially, if the 2nd and 1st bit data, that is, the memory cell When the data in M l + x is different from the originally written data, the corresponding memory cell M il 3
It can be determined that there is an abnormality.

〔Effect of the invention〕

As described above, the semiconductor memory device of the present invention has a relatively simple configuration, simplifies the work when testing memory cells, and can be used not only as a normal RAM mode but also as a shift register. Can be done.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 2 is an equivalent circuit diagram of the memory cell M t j shown in the figure. (Explanation of symbols) 1...Memory cell array, 2...Data input terminal, 3...Data output terminal, 40-4n...Gate circuit (tri-state buffer), 5...Control signal supply circuit , WL, -WL, ... word line, B Ll, B L1, ~, B Ln, B L
I, . . . bit line pair, Mi, j . . . memory cell,
s0 to s1, . . . control signals.

Claims (1)

[Claims] A plurality of word lines (WL_1, WL_2, ..., WL_
m) and bit line pairs (BL_1, @BL@_1,...
・, BL_n, @BL@_n) A memory cell array (
1), a terminal for inputting data from the outside (2), a terminal for outputting data to the outside (3), and the input terminal between the adjacent bit lines between the memory cells adjacent in the word line direction. (2) and the first bit line (BL
_1) and between the final bit line (@BL@_n and the output terminal (3)).
4_1, ..., 4_n), and a circuit (5) that sequentially supplies control signals (S_0, S_1, ..., S_n) to the gate circuits according to the arrangement order of the gate circuits, and The data of the memory cell or the input terminal (2
) in a semiconductor memory device in which data from the source is shifted in the word line direction.