KR100212141B1 - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The circuit includes precharge means for precharging bit line pairs in response to a precharge control signal, a plurality of memory cells selected by a word line select signal and connected between the bit line pairs, the bit line pairs and data Generating a first control signal in response to column select transistors for controlling data transfer to / from the plurality of memory cells between a line pair, a low level inverting chip select signal and a low level output enable signal, Control signal generating means for generating a second control signal in response to the low level inverting chip selection signal and a high level output enable signal, and generating data input signals in response to the first control signal; A plurality of write drivers for transmitting to the plurality of data line pairs in response to the second control signal It consists of a plurality of sense amplifiers for amplifying the signal from and outputting it as data output signals.

Therefore, the read and write operations can be performed in response to the inverted chip select signal and the output enable signal, and the chip size can be reduced by simplifying the circuit configuration.

Description

Data input / output circuit and semiconductor memory device using same

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of controlling data input and output operations by an output enable signal.

A data input / output circuit of a conventional semiconductor memory device is composed of a write driver for writing data to a memory cell and a sense amplifier for reading data from the memory cell. The write driver stores input data in the memory cell in response to the control signal wden, and the sense amplifier outputs data output from the memory in response to the control signal saen. Since the write operation and the read operation are not performed at the same time, the sense amplifier does not operate when the write driver operates, and the write driver does not operate when the sense amplifier operates.

FIG. 1 shows a structure of a conventional semiconductor memory device, and includes NMOS transistors N1, N2, N3, N4, and N5, memory cells 10, a sense amplifier 20, and a write driver 30. have.

The NMOS transistors N1, N2, and N3 precharge the pair of bit lines BL and BLB in response to the control signal PC. The memory cells 10 are enabled in response to the signal WL generated by decoding the row address signal to store data from the bit line pairs BL and BLB, or store data from the bit line pairs BL and BLB. send. The NMOS transistors N4 and N5 transfer data from one bit line pair to the data line pair BL and DLB in response to the signal Y generated by decoding the column address signal, or the data line pair DL. The data from the DLB is transmitted to the bit line pairs BL and BLB. The sense amplifier 20 outputs data from the data line pairs DL and DLB as an output signal DO in response to the sense amplifier enable signal saen. The write driver 30 outputs the input signal DI as data line pairs DL and DLB in response to the control signal wden.

FIG. 2 is a circuit diagram of the write driver shown in FIG. 1 and includes NAND gate 32, inverter 34, and NMOS transistors 36 and 38. As shown in FIG.

The NAND gate 32 inverts and outputs the input signal DI when the control signal wden is at a high level. The inverter 34 inverts the output signal of the NAND gate 32. The transfer gates 36 and 38 output the output signals of the inverter 34 and the NAND gate 32 to the data line pairs DL and DLB, respectively.

3 is a circuit diagram of the sense amplifier shown in FIG. 1, which includes the PMOS transistors 40, 42, 58, NMOS transistors 44, 46, 48, 60, inverters 50, 54, and NAND gate 52. FIG. ) And a NOR gate 56.

The configuration of the PMOS transistors 40 and 42 and the NMOS transistors 44 and 46 has a configuration of a differential amplifier and is enabled when the control signal saen applied to the NMOS transistor 48 is at a high level. The difference between the signals transmitted from the data line pairs DL and DLB is amplified and output. Thus, when the high level signal is output from the drain electrode of the NMOS transistor 44, the output signal of the inverter 50 becomes low level, and when the low level signal is output, the output signal of the inverter 50 becomes high level. Becomes The inverter 50 inverts the high level control signal saen and outputs a low level signal. The NAND gate 52 and the NOR gate 56 invert and output the output signal of the inverter 50 in response to the high and low level control signals saen, respectively. The PMOS transistor 50 and the NMOS transistor 62 output a high level signal as an output signal DO when the output signal of the NAND gate 52 is low level, and the output signal of the NOR gate 56 is high. In the case of a level, a low level signal is output as an output signal DO. If the output signals of the NAND gate 52 and the NOR gate 56 are low level and high level, respectively, the PMOS transistor 58 and the NMOS transistor 60 are turned on so that the output signal DO is in a high impedance state. do. That is, when the memory cell writes, the output signal DO is brought into the high impedance state. This can be insecure because it does not hold the output to one level. In addition, there is a problem that the circuit configuration is complicated and the chip size also becomes large.

That is, the conventional semiconductor memory device requires two pins for inputting control signals wden and saen for controlling the write driver and the sense amplifier, and has a problem in that the chip size occupied by these circuits is large.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of controlling data input and output operations by an output enable signal and having a write driver and a sense amplifier as one.

The semiconductor memory device of the present invention for achieving the above object is a pre-charge means for precharging the bit line pairs in response to the precharge control signal, a plurality of selected by the word line selection signal and connected between the pair Memory cells, column select transistors for controlling data transfer to / from the plurality of memory cells between the bit line pairs and data line pairs, a low level inverted chip select signal and a low level output enable signal. A control signal generating means for generating a first control signal in response, generating a second control signal in response to the low level inverting chip selection signal and a high level output enable signal, and in response to the first control signal. A plurality of write drivers for transmitting data input signals to the plurality of data line pairs, and the second control And a plurality of sense amplifiers for amplifying signals from the plurality of data line pairs in response to the signal and outputting the signals to the data output signals.

1 shows the structure of a conventional semiconductor memory device.

2 is a circuit diagram of the write driver shown in FIG.

3 is a circuit diagram of the sense amplifier shown in FIG.

4 shows the configuration of the semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram of the write driver and sense amplifier shown in FIG.

FIG. 6 shows the results of the operation simulation of the circuit shown in FIG.

The semiconductor memory device of the present invention will be described with reference to the accompanying drawings as follows.

FIG. 4 shows the structure of the semiconductor memory device of the present invention and is composed of NMOS transistors N1, N2, N3, N4, N5, memory cell 10, and a write driver and sense amplifier 70. FIG.

The NMOS transistors N1, N2, and N3 precharge the pair of bit lines BL and BLB in response to the control signal PC. The memory cells 10 are enabled in response to the signal WL generated by decoding the row address signal to store data from the bit line pairs BL and BLB, or store data from the bit line pairs BL and BLB. send. The NMOS transistors N4 and N5 transfer data from one bit line pair to the data line pair DL and DLB in response to the signal Y generated by decoding the column address signal, or the data line pair DL. The data from the DLB is transmitted to the bit line pairs BL and BLB. The write driver and the sense amplifier 70 are inverted chip select signals. Is low level and the operation enable signal OE is low level, the input signal DI is transmitted to the data line pair DL and DLB, and the inverting chip select signal is transmitted. Is low level, and the output enable signal OE is high level, the signal from the data line pair DL and DLB is output as the output signal DO.

FIG. 5 is a circuit diagram of the write driver and the sense amplifier shown in FIG. 4 and includes a sense amplifier 100 including PMOS transistors N2, N4, and N6, NMOS transistors 78, 80, and 82, and an inverter 84. FIG. , PMOS transistor 94, NMOS transistor 96, write driver 200 composed of inverters 98, 99, and PMOS transistor 88, NMOS transistor 92, inverter 88, and a NOR gate ( 70 is composed of a control circuit 300 composed of.

The sense amplifier 100 includes a PMOS transistor 72 having a source electrode to which a power supply voltage is applied, a PMOS transistor 74 having a source electrode to which a power supply voltage is applied and a drain electrode connected to the drain electrode of the PMOS transistor 72. PMOS transistor 76 having a gate electrode and a drain electrode connected to a source electrode and a gate electrode of the PMOS transistor 74 to which a voltage is applied, a gate electrode connected to the data line DL, and a drain electrode of the PMOS transistor 74. NMOS transistor 78 having a drain electrode, a drain electrode connected to the drain electrode of the PMOS transistor 76, a source electrode connected to the source electrode of the NMOS transistor 78, and a NMOS transistor having a gate electrode connected to the inversion data line DLB. 80, an NMOS transistor having a drain electrode connected to the source electrode of the NMOS transistor 80 and a source electrode connected to the ground voltage Consists of 82, a PMOS transistor and an inverter 84 having an output terminal for outputting the input terminal and the output signal (DO) connected to drain electrodes of the (N4).

The write driver 200 has an inverter 98 for inverting an output enable signal, and a gate to which the output signal of the inverter 98 and the PMOS transistor 94 having the gate electrode to which the output enable signal OE is applied are applied. NMOS transistor 96 having an electrode is configured as a transfer gate for transferring the data input signal DI to the data line DL. The inverter 99 is configured to invert the data input signal DI transmitted through the PMOS transistor N4 and the NMOS transistor 96 and transmit the inverted data line DL to the inverted data line DL.

The control circuit 300 is an inverting chip select signal In response to the PMOS transistor 86 for transmitting the output enable signal OE, the inverter 88 for inverting the signal transmitted through the PMOS transistor 86, and an inverting chip select signal. In response, the NMOS transistor 92 and the inverting chip select signal for applying a power supply voltage to the gate electrode of the PMOS transistor 94. And a NOR gate 90 for irrationally combining the output signal of the inverter 88 to the gate electrode of the NMOS transistor 82 and the PMOS transistor 72.

The operation of the circuit described above is divided into a write operation and a read operation as follows.

First, the write operation is the inversion chip select signal. Is low level and the output enable signal OE becomes low level, the transfer gate composed of the PMOS transistor 94 and the NMOS transistor 96 transmits the data input signal DI to the data line DL. . At this time, since the output signal of the NOR gate 90 becomes a high level, the NMOS transistor 82 is turned off, so that the sense amplifier 100 does not operate. Invert chip select signal Is low level and the output enable signal OE becomes high level, the NMOS transistor 92 is turned on and a power supply voltage is applied to the gate electrode of the PMOS transistor 94 so that the transfer gate is turned off. As a result, the output terminal of the transfer gate is brought into a high impedance state. At this time, the output signal of the NOR gate 90 becomes a high level, the sense amplifier 100 is enabled. That is, the write driver maintains a high impedance state during the read operation.

Next, the read operation is performed as described above. Is low level and the output enable signal OE becomes high level, the output signal of the NOR gate 90 becomes high level and the sense amplifier 100 is enabled. Then, the sense amplifier 100 amplifies and outputs a difference between signals from the data line DL and the inverted data line DLB. That is, if the signal from the data line DL is high level, the output signal DO of high level is output, and if the signal from the inversion data line DLB is high level, the low level output signal DO is output. do.

That is, the write driver and the sense amplifier of the present invention can control the write operation and the read operation by controlling the output enable signal, and the chip size can be reduced by simply configuring the write driver and the sense amplifier as one circuit. have.

6 is a waveform showing the operation simulation result of the circuit shown in FIG.

Input condition is inverting chip select signal Enabled memory cells up to 148ns and no memory cells from 149ns. The output enable signal OE inputs a low level up to 79 ns to perform a write operation, and a high level input from 80 ns performs a read operation. That is, the data input signal DI is input only up to 79ns, and becomes meaningless from 80ns.

A high level signal is stored in a memory cell connected to the word line WLO, and a low level signal is stored in a memory cell connected to the word line WLI.

The control signal PC for precharging is allowed to float for 3 ns before the word line is enabled to precharge the bit line pairs BL and BLB to write data to the memory cells or to read data from the memory cells.

That is, it writes a high level from 10ns to 29ns and a low level from 50ns to 69ns. This leads to a high level from 90 ns, which is the word line (WLO) RRK high level. This is because the high level signal stored in the memory cell is read. Next, at 130ns when the word line WL1 becomes high, the low level is read by reading the low level stored in the memory cell.

Invert chip select signal Becomes high at 149 ns and the output signal DO remains low when no memory cell is used.

That is, in the present invention, the write driver and the sense amplifier control the circuits by using the inverting chip select signal and the output enable signal which are input from the outside without using the control signals waen and saen input from the outside. The control signal input pin for controlling the sense amplifier can be reduced.

The chip size can be reduced by simply configuring the write driver and sense amplifier of the present invention into one circuit.

Therefore, the semiconductor memory device of the present invention can reduce the pin for inputting the sense amplifier enable signal (saen) by enabling the write driver and the sense amplifier by the output enable signal, and the write driver and the sense amplifier are one. By simply configuring the circuit, the chip area can be reduced at the time of integration.

Claims (4)

Precharge means for precharging the pair of bit lines in response to the precharge control signal; A plurality of memory cells selected by a word line selection signal and coupled between the bit line pairs; Column select transistors for controlling data transfer to / from the plurality of memory cells between the bit line pairs and data line pairs; A first control signal is generated in response to the low level inversion chip select signal and the low level output enable signal, and a second control signal is generated in response to the low level inverted chip select signal and the high level output enable signal. Generating control signal generation means; A plurality of write drivers for transmitting data input signals to the plurality of data line pairs in response to the first control signal; And a plurality of sense amplifiers for amplifying a signal from the plurality of data line pairs and outputting the data as data output signals in response to the second control signal. 2. The apparatus of claim 1, wherein the control signal generating means comprises: a first PMOS transistor for transmitting the output enable signal in response to the low level inverting chip select signal; A first NMOS transistor for transmitting a high level signal in response to the high level inversion chip select signal; A first inverter for inverting a signal transmitted through the first PMOS transistor; And a NOR gate for illogically combining the inverting chip selection signal and the output signal of the first inverter. 3. The display device of claim 2, wherein each of the plurality of write drivers comprises: a second inverter for inverting the first control signal; A CMOS transfer gate for transmitting a data input signal to a data line of the pair of data lines in response to the first control signal at a low level; And a third inverter for inverting an output signal of the CMOS transfer gate and transferring the inverted data line of the pair of data lines. 4. The transistor of claim 3, wherein each of the plurality of sense amplifiers comprises: a second PMOS transistor having a source electrode to which a power supply voltage is applied; A third PMOS transistor having a source electrode to which a power supply voltage is applied and a drain electrode connected to the drain electrode of the second PMOS transistor; A fourth PMOS transistor having a source electrode to which a power supply voltage is applied, a gate electrode and a drain electrode connected to the gate electrode of the third PMOS transistor; A second NMOS transistor having a gate electrode connected to the data line and a drain electrode connected to the drain electrode of the third PMOS transistor; A third NMOS transistor having a drain electrode connected to the drain electrode of the fourth PMOS transistor, a source electrode connected to the source electrode of the second NMOS transistor, and a gate electrode connected to the inversion data line; A fourth NMOS transistor having a drain electrode connected to a source electrode of the third NMOS transistor and a source electrode connected to a ground voltage; And a fourth inverter having an input terminal connected to the drain electrode of the third PMOS transistor and an output terminal for outputting an output signal.