經濟部中央標準局員工消费合作社印製 317652 A7 B7_ 五、發明説明（1 ) 發明背景 1 .發明領域 本發明係關於半導體記憶裝置，尤指一種使用P型薄膜 電晶體（TFT)做爲負載元件的CMOS型態（互補式金氧半導 體）靜態隨機存取半導體記憶裝置》 2 .相關習知技術說明 靜態隨機存取半導體記憶裝置通常包括一連接至位址 線的正反器（flip-flop)陣列，並被歸類爲高阻抗負載型 NMOS(N通道金氧半導體）記憶體及反相型器態的CMOS 型態記憶體。N Μ 0 S記憶單元目前使用高阻抗複晶矽電晶 體做爲反相器負載元件來取代先前所使用的空乏型η通道電 晶體。C Μ 0 S記憶單元使用C Μ 0 S反相器，於記憶單元待 機時關閉η通道或ρ通道電晶體。於關閉η逋道或ρ通道電晶 體時，電源電流不傳輸至CMOS反相器。因此，靜態隨機 存取半導體記憶裝置的電流消耗可以降低》然而，CMOS 記憶單元的積體化程度比NMOS記憶體低。此外這種 CMOS型靜態隨機存取半導體記憶單元使用TFTs做爲負載 元件》TFT必需使用複晶矽層做爲TFT通道，並使用一薄 氧化層做爲閘極隔離層以改進on/off特性，以便維持單位 資料。然而，TFT通道是以複晶矽製成，具有與電壓源線 用的相同導電層。因此使TFT通道產生一些問題。 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 装· ,?τ 經濟部中央標準局貝工消費合作社印製 317652 A7 B7 五、發明説明（2 ) 以下將參照圖一特別描述CMOS靜態隨機存取半導體 記憶裝置的問題。美國第4，9 1 6,6 6 8號專利，名爲"Internal Synchronization Type MOS SRAM with Address Transition Detctine Circuit11，以及 1985年International Solid-State Circuit Conference Digest of Technical 第64頁一篇 名爲"4$A..LZfl§_M【C.M〇S· RAM with a Schmit Trigger Sense Amplifier"論文中 描述記憶單元包括做爲負載元件的p型TFTs 14, 16, n通 道型驅動MOS電晶體6,8，以及η通道型傳輸MO Sit晶體 5，7。T F T s 1 4 , 1 6的源極連接於電晶體6，8的汲極，電晶 體6 , 8的源極連接至接地電壓。Μ 0 S電晶體5的電流路徑連 接於位元線BL與點12之間，其閘極連接至字元線WL。電 晶體7的電流路徑連接於位元線/BL與點10之間，其閘極連 接於字元線W L點1 0及1 2具有互補的資料並以電晶體5，7的 導通而分別將該互補資料傳輸至位元線BL與/BL。這種記 憶單元也稱爲4電晶體型態靜態記憶單元。 圖二表示一種習知CMOS型態靜態隨機存取半導體記 憶裝置之平面圖，其中記憶單元陣列區域100與週邊電路 200 —起被表示出來。此外，圖三係沿圖二之線3-3'而得 到的截面圖以便表示習知記憶裝置之問題。電源線4從記憶 單元陣列區域100之p型薄膜電晶體之通道層延伸至週邊電 路200經由接觸洞18與金屬接觸用以提供電源電壓。電源 線4被第一與及第二隔離層2 2，2 0與基體1隔離，並與記憶 單元陣列100的ρ型TFT共用相同的複晶（polycrystalline)或非結 晶性複晶矽層。在此狀況中，接觸洞1 8與其它接觸洞，如 用以接觸金屬線與主動區域的接觸洞，同時形成，所以蝕 刻深度的不同導致薄電壓源線4被過度蝕刻，造成與金屬線 (請先閣讀背面之注意事項再填寫本頁) 裝- 訂 A7 _B7__ 五、發明説明（3 ) 2接觸的失效，如圖三所示。爲處理這種問題，二種方法被 提出，一種是形成用以分離地接觸電源線4與金屬線2與其 它接觸洞的的方法，以及其它用以增加接觸金屬線2上方之 區域內的電源線4的厚度。然而，當電源線4的厚度隨記憶 晶片之積體化而降低時這些方法太難以執行。 另一種習知解決這種問題的方法是在基體1之一井區內 形成電源線4與金屬線2之間的直流路徑（或稱爲第二導電型 態主動區域）2 4，如圖四 '五所示。此處，圖五係沿圖四之 線5-5’的截面圖。也就是說，製造與主動層接觸之分離接 觸洞18,18a。這可以防止電源線4的過度鈾刻，但在形成 接觸電源線4的蝕刻深度時應該以厚隔離層22爲基礎。同 時，如圖一所示，P型TFT經由點10或12與相對p型TFT之 閘極連接，其中比隔離層22薄的F疫显嗝離層被.過度蝕刻以 形成閘極及汲極的接觸洞，產生基體的損壞。 發明綜合說明 +發明之一目的在提供一種靜態隨機存取半導體記憶 裝置及其製造方法，可以確保性能及可靠度。 本發明之另一目的在提供一種靜態隨機存取半導體記 憶裝置中不具有不同蝕刻深度之連接電源線與金屬線的手 段。 本發明之又一目的在提供一種降低單元尺寸之靜態隨 機存取半導體記憶裝置。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 請 先 閱 讀 背 之 注 意 事 項 再 填 寫 本 頁 裝 訂 經濟部中央標準局員工消費合作社印製 317652 A7 B7 五、發明説明（4) 本發明之再一目的在提供一種改良ΟΝ/OFF電流特性 的靜態隨機存取半導體記憶裝置。 依據本發明較佳實施例，一種靜態隨機存取半導體記 憶裝置，包括一具有第一導電型態驅動元件及第二導電型 態薄膜電晶體（TFT)的負載單元並以栓鎖電路型式形成於 一半導體基體內的的陣列區域，一與該單元陣列區域相關 . 之週邊電路區域用以形成連接一電源電壓線與一金屬線的 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 電流路徑，以及一元件區域隔離層用以隔離該單元陣列區 域，其中該週邊電路區域更包括：一第二導電型態主動區 域，被該半導體基體內之該元件區域隔離層隔離；一第一 隔離層，沉積於該第二導電型態主動區域；一第一接觸 洞，穿透該第一隔離層至該主動區域之表面；一閘極隔離 層沉積於該第一隔離層之一表面；一第二接觸洞，穿透該 閘極隔離層至該第一接觸洞內之主動區域之表面，該第二 接觸洞比該第一接觸洞小，該電源線沉積於該閘極隔離層 之一部份並經由該第二接觸洞延伸至該主動區域之表面； 一第二隔離層，沉積於包括該電源線與該閘極隔離層之基 體之全部表面上；以及一第三接觸洞，穿透該第二隔離 層，閘極隔離層及第一隔離層以便接收該金屬線而接觸該 主動區域，藉此傳輸一輸入至該金屬線之外部電源至該電 源線。 依據本發明另一實施例，該週邊電路區域可包括：一 第二導電型態主動區域，被該半導體基體內之該元件區域 隔離層隔離；一第一隔離層，沉積於該第二導電型態主動 區域；一第一接觸洞，穿透該第一隔離層至該主動區域之 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消费合作社印裝 A7 B7 五、發明説明（5 ) 表面；一閘極隔離層沉積於該第一隔離層之一表面；一第 二接觸洞，穿透該閘極隔離層至該第一接觸洞內之主動區 域之表面，該第二接觸洞比該第一接觸洞小，該電源線沉 積於該閘極隔離層上並經由該第二接觸洞延伸至該主動區 域之表面；一第二隔離層，分佈於包括該電源線與該閘極 隔離層之基體之全部表面上；以及一第三接觸洞穿透該第 二隔離層及該第二接觸洞中之電源線以便接收該金屬線菽 觸該主動區域，該第三接觸洞比該第二接觸洞小，藉此傳 輸輸入該金屬線之一外部電壓至該電源線。 依據本發明另一形式，提供形成靜態隨機存取半導體 記憶裝置之週邊電路區域之方法，包括下列步驟：藉由植 入離子至該半導體基體內被該元件區域隔離層隔離的部份 形成一第二導電型態的主動區域；形成一第一隔離層至基 體之全部表面藉由過度蝕刻至該第二導電型態主動區域之 一部份以形成一第一接觸洞；於該第一隔離層之全部表面 上延伸該單元陣列之一閘極隔離層藉由蝕刻沉積於該第一 接觸洞內之該閘極隔離層之部份以形成小於該第一接觸洞 之一第二接觸洞；沉積該電源線至該第二接觸洞內以便使 該電源線接觸該第二型態主動區域；形成一第二隔離層於 該源電線及閘極層之上藉由依序鈾刻該第二隔離層，閘極 隔離層及第一隔離層以形成一第三接觸洞；以及沉積該金 屬線至該第三接觸洞內。該第三接觸洞可以藉由依序蝕刻 第二隔離層及電源線而形成於該第二接觸洞內。 以下參照所附圖式針對本發明做更詳盡的說明。 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 五、發明説明（6 圖式簡要說明 A7 B7 經濟部中央標準局員工消费合作社印裝 —係習知CMOS型態靜態隨機存取半導體記憶裝置 之結構。 二係習知CMOS型態靜態隨機存取半導體記憶裝置 之記憶單元陣列（100)及週邊電路區域（2〇〇)之平闻圖； vi三係沿圖二線3-3 1勺截面圖； 四係解決圖二裝置之問題的另一習知CMOS型態靜 態隨機存取半導體記憶裝置之記憶單元陣列（i 〇 0 )及週邊電 路區域（200)之平面圖； \/圖五係沿圖四線5-5_的截面圖； 六係本發明較佳實施例CMOS型態靜態隨機存取半 導體記憶裝置之記憶單元陣列（1 0 0 )及週邊電路區域（2 0 0 ) 之平面圖； 7 a - 7 d係沿圖六之線7 d - 7 (Γ之截面圖，用以表示本 發明一較佳實施例之半導體記憶裝置中連接電源線與金屬 線之流程； 4八係圖六記憶單元陣列區域（100)之截面圖；以及 ^九係本發明另一實施例之截面圖 較佳實施例詳細說明 參照圖6-7d，一半導體基體經過LOCOS(基體區域性 氧化的名稱）製程以形成元件隔離區域26來隔離主動區域° 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝- 317652 五、發明説明（7 ) 一單元陣列區域100具有第一導電型態驅動元件以及在基體 內以栓鎖形式設置的第二導電型態TFT負載元件。週邊電 路200與單元陣列區域100相關以形成連接一電源線4與一 金屬線2的電流路徑。週邊電路區域200藉元件區域隔離層 26而與單元陣列區域100隔離。週邊電路區域200更包括 一第二導電型態主動區域或層24藉由離子形成於一井 區內.。第一隔離層22形成於基體的整個表面，然後被蝕刻 以便於主動區域24上形成第一接觸洞28，如圖7a所示。 參照圖7 b - 8，單元陣列區域1 0 0的閘極隔離層3 0延伸 於週邊電路區域200的整個第一隔離層22的表面上，並進 III..I ................... ，_ 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 入第一接觸洞2 8。沉積第一接觸洞2 8之閘極隔離層3 0之該 部份被蝕刻以形成比第一接觸洞2 8小的第二接觸洞1 8。同 時形成的是用以接觸對應的MOS電晶體之閘極97與p型 TFT之汲極98之接觸洞99。電源線4沉積於閘極隔離層30 之上並延伸至第一接觸洞28的內角以便接觸第二接觸洞18 內之第二導電型態主動區域24，如圖7c所示。也就是說， 電源線4的導電型態與通道層34及於週邊電路區域200上延 伸並覆蓋主動區域24表面之較低閘極型態（閘極32)TFT的 汲極相同’如圖八所示》第二隔離層20沉積於電源線4及間 極隔離層30之上以藉由依序蝕刻第二隔離層20，閘極隔離 層30以及第一隔離層22而形成鄰近第一接觸洞28之第二捽 觼_涧1 8 a以便顯露出第二導電型態區域24，如圖7d所示。 金屬線2沉積於第三接觸洞以形成一電流路徑用以經由第二 導電型態主動區域24傳輸一外部電源至電源線24。 本紙張尺度適；u巾關家標準（CNs) (2iQx297公楚） A7 _ B7 五、發明説明（8 ) 參照圖八，表示沿圖六之線8-8’之包括如圖一所示之p 型TFT 14或16之記憶單元陣列區域200之截面圖。 .參照圖7cl及8描述第二接觸洞的形成，蝕刻深度是基於 閘極隔離層30的厚度，所以電源線4與p型主動區域24接觸 之區域的蝕刻深度與單元陣列區域之p型TFT電晶體之汲極 與相對應的P型TFT的閘極連接區域相同。因此，電源線有 效地與金屬線連接而不需要任何導致基體損害及降低可靠 度的蝕刻深度差。 依據本發明另一實施例第二隔離層20及電源線4依序被 鈾刻以便形成與第二接觸洞1 8小的一第三接觸洞1 8 a，如 圖九所示。當然，接觸電源線4與主動區域24的接觸洞的蝕 刻是以閘極隔離層30的厚度爲基礎，與前一實施例相同。 然後，金屬線被形成於第三接觸洞內以形成經由主動區域 2 4傳輸外部輸入之電源電壓至電源線4的電流路徑。 在以上說明中，本發明以特定實施例爲說明，但可輕 易了解的是，在不悖離本發明精神的情況下可有許多修 飾。當然，本發明可以應用於需要連接金屬線的T F T s。此 外，取代用以克服蝕刻深度差的閘極隔離層3 0可以增加沉 積於第一接觸洞2 8內的電源線4的厚度。 (請先閲讀背面之注意事項再填寫本頁) •裝_ 經濟部中央標準局貝工消費合作社印製 9 |_ 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐）Printed 317652 A7 B7_ by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) Background of the invention 1. Field of the invention The present invention relates to semiconductor memory devices, in particular to a P-type thin film transistor (TFT) as a load element CMOS type (complementary metal oxide semiconductor) static random access semiconductor memory device "2. Related conventional technical descriptions Static random access semiconductor memory devices usually include a flip-flop connected to the address line (flip-flop) Array, and is classified as high-impedance load type NMOS (N-channel metal oxide semiconductor) memory and inverter type CMOS type memory. N MOS memory cells currently use high-impedance polycrystalline silicon transistors as inverter load elements to replace the previously used depletion-type n-channel transistors. C Μ 0 S memory cells use C Μ 0 S inverters to turn off n-channel or p-channel transistors when the memory cell is in standby. When the η-channel or ρ-channel transistor is turned off, the power supply current is not transmitted to the CMOS inverter. Therefore, the current consumption of static random access semiconductor memory devices can be reduced. However, the degree of integration of CMOS memory cells is lower than that of NMOS memories. In addition, this CMOS type static random access semiconductor memory cell uses TFTs as load elements. TFTs must use a polycrystalline silicon layer as the TFT channel and a thin oxide layer as the gate isolation layer to improve on / off characteristics. In order to maintain unit information. However, the TFT channel is made of polycrystalline silicon and has the same conductive layer as the voltage source line. Therefore, the TFT channel has some problems. 2 The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210X297mm) (please read the precautions on the back and then fill out this page). Packed by? Τ Printed by Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 317652 A7 B7 5. Description of the Invention (2) The following will specifically describe the problems of the CMOS static random access semiconductor memory device with reference to FIG. U.S. Patent No. 4,9 1 6,6 6 8 entitled " Internal Synchronization Type MOS SRAM with Address Transition Detctine Circuit11, and 1985 International Solid-State Circuit Conference Digest of Technical page 64, entitled " 4 $ A..LZfl§_M [CM〇S · RAM with a Schmit Trigger Sense Amplifier " The paper describes that the memory unit includes p-type TFTs 14, 16, n-channel drive MOS transistors 6,8, And n channel type transmission MO Sit crystal 5,7. The sources of T F T s 1 4, 16 are connected to the drains of the transistors 6 and 8, and the sources of the transistors 6 and 8 are connected to the ground voltage. The current path of the MOS transistor 5 is connected between the bit line BL and the point 12, and its gate is connected to the word line WL. The current path of the transistor 7 is connected between the bit line / BL and the point 10, and its gate is connected to the word line WL points 10 and 12 which have complementary data and are connected by the conduction of the transistors 5, 7 respectively The complementary data is transferred to the bit lines BL and / BL. This type of memory cell is also called 4-transistor type static memory cell. FIG. 2 shows a plan view of a conventional CMOS type static random access semiconductor memory device, in which the memory cell array area 100 and the peripheral circuit 200 are shown together. In addition, Fig. 3 is a cross-sectional view taken along line 3-3 'of Fig. 2 to show the problem of the conventional memory device. The power line 4 extends from the channel layer of the p-type thin film transistor of the memory cell array area 100 to the peripheral circuit 200 and contacts the metal via the contact hole 18 to provide a power voltage. The power line 4 is isolated from the base 1 by the first and second isolation layers 22, 20, and shares the same polycrystalline or non-crystalline polycrystalline silicon layer with the p-type TFT of the memory cell array 100. In this situation, the contact hole 18 and other contact holes, such as contact holes for contacting the metal line and the active area, are formed at the same time, so the difference in etching depth causes the thin voltage source line 4 to be over-etched, causing Please read the precautions on the back first and then fill out this page) Binding-Order A7 _B7__ 5. Description of the invention (3) 2 Failure of contact, as shown in Figure 3. To deal with this problem, two methods have been proposed, one is to form a method for separately contacting the power line 4 and the metal line 2 and other contact holes, and other methods for increasing the power in the area above the contact metal line 2 The thickness of line 4. However, these methods are too difficult to perform when the thickness of the power supply line 4 decreases as the memory chip is integrated. Another conventional method to solve this problem is to form a DC path (or called the second conductive type active area) 2 4 between the power line 4 and the metal line 2 in a well area of the substrate 1, as shown in FIG. 4 'Five shown. Here, Fig. 5 is a cross-sectional view taken along line 5-5 'of Fig. 4. That is, separate contact holes 18, 18a are made in contact with the active layer. This prevents excessive uranium engraving of the power line 4, but the thick isolation layer 22 should be used as the basis for forming the etch depth that contacts the power line 4. At the same time, as shown in FIG. 1, the P-type TFT is connected to the gate of the opposite p-type TFT via the point 10 or 12, wherein the F-layer hiccup layer thinner than the isolation layer 22 is over-etched to form the gate and the drain The contact hole will cause damage to the substrate. Comprehensive Description of the Invention + An object of the invention is to provide a static random access semiconductor memory device and a method of manufacturing the same, which can ensure performance and reliability. Another object of the present invention is to provide a means for connecting a power line and a metal line without different etching depths in a static random access semiconductor memory device. Another object of the present invention is to provide a static random access semiconductor memory device with reduced cell size. This paper scale is applicable to China National Standard (CNS) A4 (210X297mm). Please read the precautions before filling in this page. 317652 A7 B7 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Another object of the invention is to provide a static random access semiconductor memory device with improved ON / OFF current characteristics. According to a preferred embodiment of the present invention, a static random access semiconductor memory device includes a load cell having a first conductivity type driving element and a second conductivity type thin film transistor (TFT) and formed in a latch circuit type in An array area within a semiconductor substrate, one related to the cell array area. The peripheral circuit area is used to form a connection between a power supply voltage line and a metal line printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the back (Notes need to fill out this page) The current path and a device area isolation layer are used to isolate the cell array area, wherein the peripheral circuit area further includes: a second conductivity type active area, which is covered by the device area in the semiconductor substrate Isolation layer isolation; a first isolation layer deposited in the active area of the second conductivity type; a first contact hole penetrating the first isolation layer to the surface of the active area; a gate isolation layer deposited in the first A surface of an isolation layer; a second contact hole penetrating the gate isolation layer to the surface of the active area in the first contact hole, the Two contact holes are smaller than the first contact hole, the power line is deposited on a part of the gate isolation layer and extends to the surface of the active area through the second contact hole; a second isolation layer is deposited on the On the entire surface of the base body of the power line and the gate isolation layer; and a third contact hole penetrating the second isolation layer, the gate isolation layer and the first isolation layer to receive the metal line and contact the active area, By this, an external power input to the metal wire is transmitted to the power wire. According to another embodiment of the present invention, the peripheral circuit region may include: a second conductivity type active region isolated by the device region isolation layer in the semiconductor substrate; and a first isolation layer deposited on the second conductivity type Active area; a first contact hole, penetrating the first isolation layer to the active area. The 5 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). A7 B7 5. Description of the invention (5) Surface; a gate isolation layer is deposited on a surface of the first isolation layer; a second contact hole penetrates the gate isolation layer to the active area in the first contact hole The surface, the second contact hole is smaller than the first contact hole, the power line is deposited on the gate isolation layer and extends to the surface of the active area through the second contact hole; a second isolation layer is distributed in The entire surface of the substrate including the power line and the gate isolation layer; and a third contact hole penetrating the power line in the second isolation layer and the second contact hole to receive the metal wire and contact the main body In the active area, the third contact hole is smaller than the second contact hole, thereby transmitting an external voltage input to the metal line to the power line. According to another form of the present invention, a method for forming a peripheral circuit area of a static random access semiconductor memory device is provided, which includes the following steps: forming a first portion by implanting ions into the semiconductor substrate and separated by the element region isolation layer An active region of two conductivity types; forming a first isolation layer to the entire surface of the substrate by over-etching to a part of the active region of the second conductivity type to form a first contact hole; at the first isolation layer A gate isolation layer extending on the entire surface of the cell array is deposited by etching a portion of the gate isolation layer in the first contact hole to form a second contact hole smaller than the first contact hole; The power line into the second contact hole so that the power line contacts the second type active area; forming a second isolation layer on the source wire and the gate layer by sequentially engraving the second isolation layer , A gate isolation layer and a first isolation layer to form a third contact hole; and depositing the metal line into the third contact hole. The third contact hole may be formed in the second contact hole by sequentially etching the second isolation layer and the power line. The present invention will be described in more detail below with reference to the accompanying drawings. 6 This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling in this page) Order V. Invention description (6 Brief description of the diagram A7 B7 Employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative-It is the structure of the conventional CMOS type static random access semiconductor memory device. The second is the memory cell array (100) and the peripheral circuit area (200) of the conventional CMOS type static random access semiconductor memory device. ) Of the plain view; vi three is a cross-sectional view along the line 3-3 of Figure 2; four is a memory cell array (i) of another conventional CMOS type static random access semiconductor memory device that solves the problem of the device of FIG. 2 (i 〇0) and a plan view of the peripheral circuit area (200); Figure 5 is a cross-sectional view taken along line 5-5_ of Figure 4; Six is the preferred embodiment of the present invention CMOS type static random access semiconductor memory device memory Plan view of the cell array (1 0 0) and the peripheral circuit area (2 0 0); 7 a-7 d is a cross-sectional view taken along the line 7 d-7 (Γ of FIG. 6 to represent a preferred embodiment of the present invention The power cord in the semiconductor memory device And the metal wire flow; 4-8 is a cross-sectional view of the memory cell array area (100) of FIG. 6; and ^ 9 is a cross-sectional view of another embodiment of the present invention. After the LOCOS (the name of the regional oxidation of the substrate) process to form the component isolation area 26 to isolate the active area ° This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the notes on the back before filling in Page) Installation-317652 5. Description of the invention (7) A cell array area 100 has a first conductivity type driving element and a second conductivity type TFT load element arranged in a latch form in the substrate. Peripheral circuit 200 and the cell array The area 100 is related to form a current path connecting a power line 4 and a metal line 2. The peripheral circuit area 200 is isolated from the cell array area 100 by the element area isolation layer 26. The peripheral circuit area 200 further includes a second conductivity type active The region or layer 24 is formed in a well region by ions .. The first isolation layer 22 is formed on the entire surface of the substrate, and then is etched to facilitate the active region 24 A first contact hole 28 is formed, as shown in FIG. 7a. Referring to FIGS. 7b-8, the gate isolation layer 30 of the cell array area 100 extends over the entire surface of the first isolation layer 22 of the peripheral circuit area 200, Go ahead III..I ..................., _ Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The first contact hole 28. The portion of the gate isolation layer 30 where the first contact hole 28 is deposited is etched to form a second contact hole 18 that is smaller than the first contact hole 28. At the same time, a contact hole 99 for contacting the gate electrode 97 of the corresponding MOS transistor and the drain electrode 98 of the p-type TFT is formed. The power line 4 is deposited on the gate isolation layer 30 and extends to the inner corner of the first contact hole 28 to contact the second conductive type active region 24 in the second contact hole 18, as shown in FIG. 7c. In other words, the conductivity type of the power line 4 is the same as the channel layer 34 and the lower gate type (gate 32) of the lower gate type (gate 32) extending over the peripheral circuit area 200 and covering the surface of the active area 24 'as shown in FIG. 8 As shown, the second isolation layer 20 is deposited on the power line 4 and the inter-electrode isolation layer 30 to form the adjacent first contact hole by sequentially etching the second isolation layer 20, the gate isolation layer 30, and the first isolation layer 22 28 of the second 槽 _ Jian 18 a so as to reveal the second conductivity type region 24, as shown in FIG. 7d. The metal line 2 is deposited in the third contact hole to form a current path for transmitting an external power source to the power line 24 through the second conductive type active region 24. The size of the paper is suitable; the standard of the national standard (CNs) (2iQx297 Gongchu) A7 _ B7 V. Description of the invention (8) Referring to FIG. 8, it indicates that the line 8-8 'along the line of FIG. 6 includes the A cross-sectional view of the memory cell array area 200 of the p-type TFT 14 or 16. 7cl and 8 describe the formation of the second contact hole, the etching depth is based on the thickness of the gate isolation layer 30, so the power line 4 and the p-type active region 24 in the area of the etching depth and the cell array region of the p-type TFT The drain of the transistor is the same as the gate connection area of the corresponding P-type TFT. Therefore, the power line is effectively connected to the metal line without any difference in etching depth that causes damage to the substrate and reduces reliability. According to another embodiment of the present invention, the second isolation layer 20 and the power line 4 are sequentially uranium-engraved to form a third contact hole 18 a smaller than the second contact hole 18, as shown in FIG. Of course, the etching of the contact hole contacting the power line 4 and the active area 24 is based on the thickness of the gate isolation layer 30, which is the same as the previous embodiment. Then, a metal line is formed in the third contact hole to form a current path for transmitting the externally input power voltage to the power line 4 through the active area 24. In the above description, the present invention has been described with specific embodiments, but it can be easily understood that many modifications can be made without departing from the spirit of the present invention. Of course, the present invention can be applied to T F T s that need to connect metal wires. In addition, the thickness of the power supply line 4 deposited in the first contact hole 28 can be increased by replacing the gate isolation layer 30 to overcome the difference in etching depth. (Please read the precautions on the back before filling in this page) • Installation _ Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs 9 | _ This paper scale is applicable to China National Standard (CNS) A4 specification (21〇 < 297 Mm)