JP2003149300A - Test method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test method that can test without high-functional tester by constituting a test circuit testing a memory either in a wafer level or in a chip level by using a memory other than the memory of an object to be tested. SOLUTION: In a system provided with a plurality of memory circuits (11) and a means (40) for variably connecting that enables free connection between these memory circuits, a plurality of the memory circuits are connected with the means 40 for variably connecting as needed and therewith the test circuit is constituted by storing truth value data for outputting data equivalent to a prescribed logical result into the memory circuits corresponding to a prescribed address input. Then other memory circuits are tested by using the test circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technique for testing a memory circuit formed on a semiconductor substrate, a logic circuit construction technique for realizing a desired logic function using the memory circuit, and a memory circuit for a desired logic circuit. The present invention relates to a method of storing data for configuring logic in a memory circuit.

[0002]

2. Description of the Related Art Conventionally, there are the following methods as a method for developing a logic integrated circuit. First, the functional design of the logic integrated circuit to be realized is performed, and the designed function is implemented in HDL.
(Hardware Description Language) and other languages. Then, the design data (H
DL description sentence) is stored as a data file in a storage device such as a hard disk.

Next, the design data described in HDL is verified by a verification program called a test vector for proper operation. If a defect is found by the verification, the HDL description sentence is corrected. Then HDL
The written design data is converted into logic gate level design data by a program called a logic synthesis tool. The generated logic gate level design data is verified again by the test vector. If any defect is found by the verification, the logic gate level design data is corrected.

Next, based on the logic gate level design data, element level layout data is generated by a program called an automatic layout tool. The generated layout data is subjected to an actual load simulation by a test vector in a form including a wiring delay and the like, and an inappropriate portion is corrected and optimized.

Then, mask pattern data is generated by artwork based on the generated layout data, and a mask is generated based on this data.
After that, a logic integrated circuit is formed on the semiconductor wafer in the previous step, the wafer is cut into each chip, sealed with a sealing material such as resin, and assembled into a package.

[0006]

However, in the above-mentioned development method, many design steps are required until the final logic integrated circuit device is completed, and in the process, many stages of design are performed. Since the data is created, the amount of data is increased. Also, in a system-on-chip where the entire system is configured on a single semiconductor chip, various functional circuit blocks are often used, which increases the number of design data verification and correction processes. , Becomes a big problem in design.

Further, in the conventional design method, the finer the element, the more complicated the manufacturing process for manufacturing one semiconductor integrated circuit, and the more the number of masks used at that time, In addition, since fine processing requires an expensive manufacturing apparatus, the design cost and manufacturing cost increase, and the yield decreases. Moreover, in the conventional design method, since a separate mask has to be manufactured for each product, it takes a long time to develop a new product.

The present inventors utilize a memory circuit having a structure similar to a general-purpose memory, and the relationship between the address input and the data output of such a memory circuit corresponds to the relationship between the desired input and output of the logic circuit. Therefore, a structure for supplying data to such a memory circuit has been proposed (International Publication WO00
/ 52753). The proposal also includes a configuration capable of coping with a defect in the memory circuit. That is, a comparison circuit for comparing the data written and supplied to the memory circuit with the data read from the memory circuit, and a variable circuit for converting the address signal supplied to the memory circuit based on the comparison result in the comparison circuit. When an address conversion circuit is set and a memory failure is detected by the comparison circuit (that is, by comparing the data written and supplied to the memory circuit by the comparison circuit with the data read from the memory circuit, When a mismatch between data is detected), the variable address conversion circuit is operated so as to avoid the memory address. According to this proposed configuration, a circuit having a desired function can be obtained by writing data in the memory circuit, so that the number of design steps and the development period can be greatly shortened.

The above-mentioned prior invention requires a data comparison circuit, a variable address conversion circuit, etc., and it must be taken into consideration that the chip size becomes large. Further, there may be room for studying a suitable configuration for writing the truth value data that realizes the logical function in the memory circuit.

Conventionally, general inspection of a semiconductor memory is performed by a tester which generates a test pattern according to a predetermined algorithm. The generation algorithm of the test pattern is different from that of the test pattern generated by the logic tester for testing the logic circuit. Therefore, the semiconductor memory is often measured by a tester dedicated to the memory. Therefore, when the variable logic LSI is configured using the memory circuit, the logic configured by the memory circuit can be verified by using the test vector, but in order to test the memory circuit which is the basic circuit. There is a problem that an expensive memory tester is required.

Further, in an LSI having a built-in memory, a BIST (Built in
It is possible to reduce the load on the tester by providing a self test) circuit. However, in that case, another problem such as an increase in chip size and a decrease in yield due to the BIST circuit must be taken into consideration.

An object of the present invention is to provide a semiconductor device capable of efficiently storing truth value data for realizing a desired logic function in a memory circuit in the memory circuit. Another object of the present invention is to provide a test circuit for testing either memory at a wafer level or a chip level by using a memory function capable of realizing an arbitrary logical function, and to test a memory other than the memory under test. It is to provide a test method that can be tested without using a highly functional tester by using the configuration.

Still another object of the present invention is to provide a semiconductor device which can use a DRAM as a memory circuit and can realize a desired logical function by a plurality of memory circuits. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, a plurality of memory circuits and variable connection means capable of arbitrarily connecting these memory circuits are provided,
A test circuit is configured by appropriately connecting the plurality of memory circuits by the variable connection means and storing truth value data for causing the memory circuits to output data corresponding to a desired logical output with respect to a predetermined address input. Then, another memory circuit is tested using the test circuit. According to the above-mentioned means, since the memory circuit can be tested using the memory circuit, a highly functional tester is not required, and the test cost can be significantly reduced.

As one of the preferable means for writing the truth value data for constructing the test circuit in the memory circuit, JT
A boundary scan circuit defined by AG (Joint Test Action Group) can be used. The boundary scan circuit defined by JTAG enables parallel transfer of data between two circuit blocks and also latches a signal supplied from one circuit block to the other circuit block to scan out by a shift operation. Therefore, it is possible to add the truth value data required to configure the test circuit by the memory circuit without adding a new circuit.
It can be efficiently stored by using the boundary scan circuit of JTAG. Moreover, by using this JTAG boundary scan circuit, an operation test of the memory circuit can be performed.

Further, since the boundary scan circuit of this JTAG has a flip-flop as a basic configuration, a counter can be constructed by using this flip-flop. By generating an address for the refresh operation required in the DRAM by the configured counter, the DRAM can be used as a memory circuit for configuring the logic, and a large logic is used in the system including the semiconductor integrated circuit. It is easy to scale up.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a variable logic cell enabling the test method according to the invention. The variable logic cell 10 of this embodiment is
A known SRAM (Static Random Access Memory) having a memory cell which can be regarded as substantially consisting of a flip-flop and a selection switch, or a known DRAM (Dynamic having a memory cell having a capacity for accumulating information charges and a selection switch). A readable / writable memory circuit 11 having a configuration similar to that of a random access memory) and a register capable of simultaneously fetching data read from the memory circuit 11 in a multi-bit configuration and outputting the data to the outside of the cell. 12
And peripheral logic composed of logic gates G1 to G4.

In this embodiment, the register 12 is used.
Although not shown in detail, it is configured to include a plurality of flip-flops so that a shift operation is possible. Further, the variable logic cell 10 directly separates the data input terminal DIN to the memory circuit 11 from the data output terminal DOUT_FF for outputting the data held in the register 12 and the read data from the memory circuit 11 without passing through the register 12. It has a terminal DOUT_TH for outputting to the outside of the cell.

Although not shown in detail, the memory circuit 11 has a plurality of memory cells arranged in a matrix, a plurality of word lines and a plurality of data lines arranged in a grid, and memory of the same row. The cells are connected to the corresponding word lines, and the memory cells in the same column are connected to the corresponding data lines, respectively, and a corresponding address signal in the memory array is decoded by decoding the supplied address signal. It is composed of an X address decoder that sets a word line to a selection level, a sense amplifier circuit that amplifies a potential read from a memory cell connected to the selected word line to a data line, and the like.

The register 12 is a JTAG (Joint Te
It is provided between the two circuit blocks proposed by the st Action Group) to enable the parallel transfer of data between the two circuit blocks and to latch the signal supplied from one circuit block to the other circuit block. Moreover, it is configured so that it can be used as a boundary scan circuit capable of being scanned out by the shift operation. The register 12 is also configured as bidirectional so that parallel data transfer from one of the two circuit blocks to the other and vice versa is possible. The detailed configuration of the circuit that operates in this way is not directly related to the present invention and may be easily configured by those skilled in the art, and thus detailed description thereof will be omitted.

The variable logic cell 10 has a control terminal for inputting control signals MUX_SEL, TMODE, CIN, RESET from the outside of the cell for controlling the bidirectional register 12, and the bidirectional register 12 A scan input terminal for serially inputting scan-in data SCAN_IN, an output terminal for serially outputting scan-out data SCAN_OUT from the register 12 to the outside of the cell, and a clock signal CLK for shifting the register 12 And a clock input terminal for operating.

The control signal MUX_SEL is registered in the register 1
2, a signal instructing whether scan-in data is to be captured or data from the memory circuit 11 is to be captured, T
MODE is a mode control signal indicating the test mode or the normal operation mode, CIN is a carry input signal from another cell, and RESET is a reset signal of the register 12. Table 1 shows the relationship between the control signal MUX_SEL and the mode control signal TMODE and the operation of the register 12.

[0023]

[Table 1]

As shown in Table 1, register 12
Indicates that the control signal MUX_SEL is "1" in the test mode in which the mode control signal TMODE is set to "1" level.
If it is set to, it operates as a shift register, and otherwise operates as an 8-bit data latch. Further, in the cell, a carry output signal COU generated by ANDing the carry input signal CIN and the most significant bit of the output of the memory circuit 11 in the AND gate G4.
A terminal for outputting T and a control terminal for inputting a write control signal WE indicating a write timing as a control signal to the memory circuit 11 are provided. Since a plurality of variable logic cells 10 of this embodiment are mounted on one chip and used in combination to form a desired logic, a chip enable provided in a general RAM is used. No signal or out enable signal is required.

The scan-out data output terminal (SCAN_OUT) of the register 12 is a scan-in data input terminal (SCAN_OUT) of the register 12 of another variable logic cell 10.
IN) can be connected. Thus, in the test mode, the data read from the memory circuit 11 can be taken into the register 12, shifted, and scanned out to facilitate detection of a defective bit in the memory circuit 11. If the test reveals a variable logic cell having a defective bit, the variable logic cell is removed from the list, the defective cell is bypassed, and normal variable logic cells are connected to achieve a desired logical function. A logic circuit having the same can be configured. As a result, the yield of the variable logic LSI including such variable logic cells can be improved.

Further, since the variable logic cell 10 of this embodiment is provided with the data terminal DOUT_TH for directly outputting the data read from the memory circuit 11 to the outside of the cell, it is configured to have a desired logic function. By using the data terminal DOUT_TH, the signal delay during normal operation can be reduced.

A block diagram of a second embodiment of the variable logic cell 10 is shown in FIG. The variable logic cell 10 of this embodiment has a memory circuit 11 and a shift-operable register 12 for holding data output from the memory circuit 11, and a first logic circuit for receiving and holding an address signal input from the outside. Second register 13 and third register 1 for receiving and holding write data input from the outside
4 is provided. Further, in order to control whether the second register 13 operates as a shift register or a normal register in the test mode, a logic gate G5 that receives the control signal AMS_SEL and the test mode signal TMODE is provided. There is. The third register 14 is controlled by a control signal common to the first register 12.

Further, the scan-out data output terminal of the second register 13 is connected to the scan-in data input terminal of the third register 14, and the scan-out data output terminal of the third register 14 is connected to the scan-out data output terminal of the first register 12. By connecting the scan-in data input terminals, the second, third, and first registers 13, 14, 12 are chain-connected, and a scan path can be configured. By having such a scan path, the memory circuit 1
It becomes easier to set the truth value data to 1 as compared with the variable logic cell 10 of the embodiment of FIG. Also, the cell test becomes easier than the variable logic cell 10 of the embodiment of FIG.

The variable logic cell 10 of this embodiment is not provided with the data terminal DOUT_TH for directly outputting the data read from the memory circuit 11 to the outside of the cell. The second and third registers 13 and 14 can have the same configuration as the first register 12. Other configurations are the same as those of the variable logic cell of the embodiment of FIG. The operation is also similar to that of the variable logic cell of the embodiment shown in FIG.

A block diagram of a third embodiment of the variable logic cell 10 is shown in FIG. The variable logic cell 10 of this embodiment includes a memory circuit 11, a shift-operable register 12 that holds data input to and output from the memory circuit 11, and peripheral logic composed of logic gates G1 to G4. It is configured. Since the register 12 holds the data input / output to / from the memory circuit 11,
A register capable of bidirectional input / output is used.

Further, a terminal to which a control signal DIRECTION for determining the input / output direction of data is input is provided. However, the variable logic cell of this embodiment is
A data terminal DO for directly outputting the data read from the data input terminal DIN and the memory circuit 11 to the outside of the cell
It does not have UT_TH, but has a data input / output terminal D_I / O for inputting / outputting data via the register 12.

A block diagram of a fourth embodiment of the variable logic cell 10 is shown in FIG. The variable logic cell 10 of this embodiment is the variable logic cell 10 of the second embodiment (FIG. 2).
Is provided with a spare memory column and a relief circuit 20 for replacing the defective memory column with the spare memory column when any one of the memory columns includes a defective memory cell.
4 includes a register for setting an address designating a defective memory column.

In this embodiment, by inputting the defective address to be set in the register 14 from the scan path connected in the chain, it is possible to set the defective address relatively easily. . Further, this embodiment is particularly effective when the memory capacity of the memory circuit 11 is large. If the storage capacity of the memory circuit 11 is small, the probability of defective memory cells occurring is low, and if there is a variable logic cell having a defective memory cell in the memory circuit 11, the logic is configured not to be used. That's because you can do it.

A block diagram of a fifth embodiment of the variable logic cell 10 is shown in FIG. The variable logic cell 10 of this embodiment is the variable logic cell 10 of the second embodiment (FIG. 2).
In the above, an address scramble circuit 30 is provided between the register 13 for holding the address and the memory circuit 11 to switch the address so as to skip the defective memory row when any of the memory rows includes the defective memory cell. A part of 13 includes a register for holding information for switching the address. In this embodiment, the address switching information to be set in the register 13 is input from the scan path connected in the chain, which has the advantage that the address switching can be set relatively easily.

Next, an example of a configuration in which a plurality of variable logic cells of the above embodiment are arranged to form a variable logic LSI is shown in FIG.
Will be explained. In FIG. 6, 10 is a variable logic cell having the configuration as shown in FIG. 1, 40 is each variable logic cell 10
It is a variable connection circuit that allows arbitrary connection between the two. A bus 50 is arranged on one side (upper side in the drawing) of the variable logic cell 10 along the cell arranging direction, and a signal line forming the bus 50 is connected to the data input terminal DIN (FIG. 1) in each cell.
Connected).

Further, on the left and right of each variable logic cell 10, there are provided wiring regions VLA11, VLA12; VLA in the vertical direction.
21, VLA22 ... VLAn1, VLAn2, and vertical wiring areas VLA13, VLA1 on the lower side of the cell.
4; VLA23, VLA24 ... VLAn3, VLAn
4 and the wiring areas in the horizontal direction HLA1, HLA2 ... HLAm
And the wiring area VLA1 in the vertical direction.
1, VLA12; VLA21, VLA22 ... VLAn
1, VLAn2 and wiring areas HLA1 and HLA2 in the horizontal direction
...... Switch matrixes SMX11 to SMX1n capable of connecting signal lines in each area at the intersection with HLAm.
SMXm1 to SMXmn are provided.

The horizontal wiring area HLA0 arranged so as to cross each variable logic cell 10 is for transmitting signals supplied to peripheral logics (logic gates G1 to G4, etc.) in the cell. This is an area where signal lines used are provided. The wiring in the vertical wiring region and the wiring in the horizontal wiring region are formed by conductive layers of different layers.

Furthermore, the vertical wiring areas VLA11, V
LA21 ... At the end (lower end in the figure) of VLAn1, the memory circuit 11 in the variable logic cell 10 is provided via the wiring region.
Shiftable registers REG1, REG2 ... REGn and switch matrices SMX11 to SMX1n ... SMXm1 to SM for setting addresses to be supplied to
Registers REG11, REG12 capable of shift operation for setting ON / OFF information of switches composing Xmn ...
REG1n is provided. And the register REG
1, REG2 ... REGn is one scan path SP1
Data can be transferred serially with the register REG
11, REG12 ... REG1n are also configured to be able to serially transfer data by one scan path SP2. Therefore, the registers REG1 to REGn and the registers REG11 to REG1n function as a serial-parallel conversion circuit. In FIG. 6, the register REG1
1, REG12 ... Reg1n to switch matrix SMX11 to SMX1n ... SMXm1 to SMXmn
The signal line for supplying the ON / OFF control signal to the is not shown.

In this embodiment, each variable logic cell 1
The truth value data to be stored in the memory circuit 11 in 0 is given via the bus 50, and the address to store the data is variable in the scan path SP1 via the registers REG1, REG2 ... REGn. By supplying the logic cell 10 with the logic cell 10, it is possible to store the truth value data that realizes a desired logic function. Although not shown, for example, wiring for supplying a clock for shifting the registers REG1, REG2, ... REGn in parallel with the scan path is provided.

A pad is provided at one end of the scan path SP1 and a probe is brought into contact with the pad to provide data. The truth value data to be stored in the memory circuit 11 can also be configured to be given to the variable logic cell via a scan path similar to the scan path SP1 and a shift register. However, the method of storing the truth value data via the bus 50 can store the truth value data in the memory circuit more efficiently and in a shorter time than the scan path method.

In the case where an address register for latching an address signal is provided, a truth value can be obtained by using a shiftable one as the address register and connecting them in series to form a scan path. Registers REG1 and REG2 of the embodiment for supplying an address indicating a data storage position to a memory circuit
... It can be made available as REGn.

Further, in this embodiment, the scan path S connecting the registers 12 in each variable logic cell 10 is connected.
P3 is also provided, and by scanning out the data of the register 12 through the scan path SP3, it is possible to easily test whether the memory circuit 11 includes a defective bit.

In the above embodiment, the truth value data to be stored in the memory circuit 11 is described as being given via the bus 50, but bidirectional data transmission is possible as a variable logic cell which constitutes a variable logic LSI. A register 12 is used to input / output data at a common terminal.
If a cell having the configuration shown in is used, the scan path S
Truth value data can be stored in the memory circuit 11 using P3 and the register 12 in the cell. Further, in this case, in the case where a circuit corresponding to the data input / output latch circuit in the normal memory is provided, the shift operation is used as this data input / output latch circuit and the truth is obtained by connecting with the scan path. It can also be used as a register for supplying value data to the memory circuit.

The truth value data stored in the memory circuit is equivalent verification (formal
It can be easily generated by using a technique called verification. By utilizing the equivalence verification technique, the data for configuring the desired logic can be generated from the HDL description, and the present invention can be applied without changing the current EDA technique.

In the equivalence verification technique, in order to overcome the enormous adverse effects of the logic verification in the conventional function verification, mathematical truth value data is generated for each logic circuit block unit and the operation of the logically configured circuit is verified. The verification TAT (turn around time) can be shortened by making the logic circuit block into glue logic. This truth value data is used as SRAM or DRA as a memory circuit.
If used for the M truth value data, an LSI having a desired logical function can be constructed in a short period of time.

FIGS. 7A and 7B show the switch matrices SMX11 to SMX1n ... SMXm1 to SMX.
A specific circuit configuration example of MXmn is shown. Of these, Figure 7
(A) is a switch element S11, such as a MOSFET, capable of electrically connecting / disconnecting signal lines intersecting each other,
A switch matrix composed of S12, S21, S22 ..., FIG. 7B shows a switch MOS for electrically connecting / disconnecting each signal line in the horizontal direction or the vertical direction on the way.
A switch matrix composed of FETs S51 to S54, S61 to S64. A signal output from a variable logic cell connected between arbitrary signal lines intersecting with each other by the switch matrix of FIG. 7A can be input to an address of another variable logic cell.

In order to transmit a signal between different cells by cutting each signal line in the horizontal direction or the vertical direction at an appropriate place by the switch matrix of FIG. 7B. Can be used for That is, without the switch matrix of FIG. 7B, a signal line of a certain channel cannot be used for signal transmission in other parts when it is used for signal transmission somewhere, which is extremely inefficient. However, the use of the switch matrix shown in FIG. 7B improves the utilization efficiency of the signal line. The ON / OFF control signals of the switches forming each switch matrix are given from the registers REG11, REG12 ... REG1n shown in FIG. Note that, in FIG. 6, what is indicated by a chain line A is a switch matrix as shown in FIG.
A switch matrix as shown in FIG. 7B is shown by.

Next, in the variable logic LSI having the configuration as shown in FIG. 6, a specific example of configuring a desired logical function by using the arbitrary variable logic cell 10 and the switch matrix 50 will be described. First, FIG. 8 shows an example in which a binary counter is configured by using two variable logic cells 10A and 10B. In FIG. 8, each variable logic cell 10
As A and 10B, circuits having 8-bit addresses and capable of inputting / outputting 8-bit data in parallel are used. Therefore, the counter configured by this is a 14-bit binary counter. In FIG. 8, the terminal DOUT_TH for directly outputting the data read from the memory circuit 11 to the outside of the cell is omitted.

In this embodiment, the switch matrix is connected so that the lower 7 bits of the 8-bit data signal read from the memory circuit 11 and output through the register 12 are fed back to its own address input terminal. Is done. The most significant bit of the address input terminal of each variable logic cell is fixed to either "0" or "1".

The variable logic cell 1 on the left side in FIG.
0A is output from the AND gate G4 to which the carry input signal CIN is fixed at "1" and the most significant bit of the carry input signal CIN and the 8-bit data signal output from the memory circuit 11 is input. The carry output signal COUT is supplied to the right variable logic cell 10B as the carry input signal CIN. Although not shown, the variable logic cells at the subsequent stage (right side in the figure) of the right variable logic cell 10B have the same configuration, and the carry output signal COUT of the left variable logic cell is supplied one after another as the carry input signal CIN. It is also possible to form a binary counter with an integral multiple of 7 bits such as 21 bits or 28 bits by connecting to. Table 2 shows the data to be stored in the memory circuit 11 of each of the variable logic cells 10A and 10B in the case of configuring the binary counter in relation to the address.

[0051]

[Table 2]

As is clear from Table 2, the data stored at each address is a binary code obtained by adding "1" to the address code. Therefore, when the data shown in Table 2 is stored in the memory circuit and the connection is made so that the data read from the memory circuit 11 is fed back to its own address input terminal as described above,
Every time the output of the memory circuit 11 is taken into the register 12 by the clock signal CLK, only one address is updated and a value larger by 1 than the previous output value is output, that is, the variable logic cell operates as a counter. I know what to do.

The most significant bit of the 8-bit code in the "Data" column of Table 2 is the carry output signal COUT, and the most significant bit of the lowest code is "1" as shown in this table. Since it is set to "", when the lower 7 bits change from "1111111" to "0000000", "1" is output as the carry output signal COUT. Therefore, this signal causes A of the variable logic cell of the next stage.
It can be seen that since the ND gate G1 permits the supply of the clock CLK to the register 12, the variable logic cell in the next stage starts the counting operation. Although FIG. 8 shows an example in which the counter is configured using the variable theory cell shown in FIG. 1, similarly, the counter is configured using the variable theory cell having the configurations shown in FIGS. 2 to 5. It is also possible to do so. The same applies to the following examples.

FIG. 9 shows an example in which the arithmetic unit ALU and the accumulator ACC are configured by using one variable logic cell 10. In FIG. 9, as the variable logic cell 10, a circuit having an address of 12 bits and capable of inputting / outputting 8-bit data in parallel is used. Therefore, the arithmetic unit configured by this is a 4-bit arithmetic unit. By arranging two variable logic cells connected in this way,
It is also possible to configure a bit arithmetic unit.

In the embodiment of FIG. 9, the switch matrix is arranged so that the lower 4 bits of the 8-bit data signal read from the memory circuit 11 and output through the register 12 are fed back to its own address input terminal. Connection is made. The remaining 8 bits of the 12-bit address are 4-bit operand data DATA, 3-bit operation code, and 1-bit carry. Also in FIG. 9, the terminal DOUT_TH for directly outputting the data read from the memory circuit 11 to the outside of the cell is not shown.

FIG. 10 shows an equivalent circuit of the circuit of FIG.
As can be seen by comparing FIGS. 9 and 10, the memory circuit 1
1 corresponds to the arithmetic unit ALU, and the register 12 corresponds to the accumulator ACC. Table 3 shows the data to be stored in the memory circuit 11 of the variable logic cell 10 in the case of configuring the arithmetic unit in relation to the address.

[0057]

[Table 3]

In Table 3, the first 3 bits of the 12 bits in the address column are the operation code, and Table 4 shows the mnemonic symbol of the operation corresponding to this 3-bit code and the function and code of the operation. In Table 4, the operation “CLR” indicated by the code “000” is the process of resetting the output, that is, all “0”, and the operation “ADD” indicated by the code “001” is the input data which is the data of the accumulator ACC. The addition process and the operation "SUB" whose code is "000" indicate the process of subtracting the input data from the data of the accumulator ACC. It is also possible to define operations not shown in Table 4.

[0059]

[Table 4]

FIG. 11 shows eight variable logic cells 10A-.
An example in which a test circuit is configured using 10H will be shown. MUT
The cells indicated by are the cells to be tested. Note that FIG.
1 exemplifies, as each of the variable logic cells 10A to 10H, a circuit having an address of 8 bits and capable of inputting / outputting 8-bit data in parallel. Although not shown, the clock CLK is commonly supplied to all cells, and each cell operates in synchronization with the clock.

Each of these eight variable logic cells 10A-10
Of H, 10A and 10B are configured as 14-bit binary counters COUNT0 and COUNT1 as a whole according to the same configuration as described in FIG. Of the 7-bit outputs of the counters COUNT0 and COUNT1, the upper 4 bits of COUNT0 (D3 to D
6) and the lower 4 bits (D0 to D3) of COUNT1,
Used as an address to access the tested cell MUT.

Further, each counter COUNT0, COUNT
Of the 7-bit output of T1, the lower 3 bits of COUNT0 (D0 to D2) and the upper 3 bits of COUNT1 (D4 to
D6) is used as an operation control signal of the variable logic cell 10C as the controller CONT. The variable logic cells 10D and 10E supply the addresses generated by the variable logic cells 10A and 10B to the cell MUT as they are or invert them to supply the lower 4 bits (D0 to D3) of the address by +1. It is configured as circuits NOT0 and NOT1 which operate as an up counter for updating and a down counter for updating an address by -1.

The variable logic cell 10F is configured as a circuit that generates write data to be input to the cell MUT to be tested. The write data output from the variable logic cell 10F is input to the data input terminal DIN of the cell MUT to be tested. In addition, the variable logic cells 10G and 1
0H is the 8-bit data output from the tested cell MUT and the expected value EX generated by the variable logic cell 10C.
It is configured as comparators CMP0 and CMP1 for comparing with D. The data output from the cell MUT to be tested is divided into lower 4 bits and upper 4 bits and input to the address input terminals A0 to A3 of the variable logic cells 10G and 10H functioning as comparators CMP0 and CMP1.

Further, the variable logic cell 10C has control signals WE and CIN to be inputted to the cell MUT to be tested.
And a controller CONT that generates an expected value EXD and a comparison enable signal CEN for the variable logic cells 10F to 10H. The expected value EXD and the comparison enable signal CEN generated in the variable logic cell 10C as the controller CONT are the comparator CMP.
0, variable logic cells 10G and 10 functioning as CMP1
It is input to the H address input terminals A4 and A5. The expected value EXD is a 1-bit value indicating all “1” or all “0”.

The variable logic cells 10G and 10H receive the data output from the tested cell MUT from the controller C.
If it matches the expected value generated by the variable logic cell 10C as the ONT, the output data Dout0 is, for example, "0".
Is output and the output data is Dou if it does not match the expected value.
"1" is output as t0. Each output Dout0 is fed back to its own address input terminal A6, and once "1" is output as the output data Dout0, the output data Dou is continuously output.
It is configured to output "1" as t0. The output Dout0 of the variable logic cell 10H functioning as the comparator CMP1 is also input to the address input terminal A7 of the variable logic cell 10G functioning as the comparator CMP0, and the output data Dou is temporarily output from the variable logic cell 10H.
When "1" is output as t0, then the variable logic cell 1
Output data Dout0 "1" (ERRO
R) is output.

The data stored in advance in the memory circuits of the variable logic cells (NOT) 10D and 10E for generating the address to be given to the cell under test MUT outputs the address which changes in the descending order when the input address changes in the ascending order. It is such data. Since such data can be created relatively easily, illustration is omitted. The data stored in advance in the memory circuit of the variable logic cell (DATA) 10F that generates write data is all "1" or all "0" data. Since such data can be created relatively easily, illustration is omitted.

The data stored in advance in the memory circuits of the variable logic cells 10G and 10H functioning as the comparators CMP0 and CMP1 is either A0 to A3 when the address A6 input as the expected value EXD is "0". When it is "1" or when any of A0 to A3 is "0" when the address A6 is "1", "1" indicating a defect is output, and when the address A6 is "0". A0
~ All of A3 are "0" and address A6
When A0 is "1", if A0 to A3 are all "1", the data is output as "0". Since such data can be created relatively easily, illustration is omitted.

Table 5 shows the data output terminals D6 and D of the variable logic cell 10B functioning as the counter COUNT1.
5, signals SLout6, SLout5, SL output from D4
The relationship between out4 and the sequence of tests controlled by it and the functions of the variable logic cells (NOT) 10D and 10E at that time is shown. "Buffer" in the "Function" column of Table 5 means that the same data as the input data is output, and "Inverter" means that the input data is inverted. There is.

[0069]

[Table 5]

FIG. 12 shows the data output terminals D2 and D of the variable logic cell 10A which functions as the counter COUNT0.
Signals SLout2 and SLout output from the terminals 1 and D0 and input to the variable logic cell 10C as the controller CONT.
1, signals WE (Write Enable) and CIN (Carry Inpu) output from the variable logic cell 10C by SLout0
t), CEN (Comparator Enable) and address AD input to the cell under test MUT by these control signals
RESS, write data DATA_IN, read data DATA_OUT
The timing of is shown. That is, the signal of such timing is used as the variable logic cell 10 as the controller CONT.
The data stored in the memory circuit in the variable logic cell 10C is created so that C outputs. Since such data can be created relatively easily, illustration is omitted.

13 and 14 show some simulation results of the test circuit shown in FIG. This timing chart shows the test sequence “write 0 inc.” And “read 0
andwrite 1 inc. ”, that is, SL_ {OUT} (6), S in Table 9
The values of L_ {OUT} (5) and SL_ {OUT} (4) are (000) and (00
The operation timing of each signal in the test circuit when in the state 1) is shown. CLK represents a clock signal input from the outside, WE, CIN, Addres
s is the input signal of the cell under test MUT, Dout is the output signal of the cell under test MUT, CEN is the comparator C
The comparison enable signal to MP0 and CMP1, ERROR represents the comparison result output of the comparator CMP0. Here, the values of Address and Dout are in hexadecimal notation.

From the timing chart of FIG. 13, it can be confirmed that the address changes to FD, FE, FF, 00, 01, 02. This indicates that the binary counter is working properly. Dout changes from "00" to "F" due to the transition of WE at the timing Ta.
It can be confirmed that the data has changed to F ”. This indicates that new data FF has been written to the address“ 00 ”where the data“ 00 ”was stored. Also, when the marching test ends The ERROR output is low level, which means that the cell under test MUT has passed the marching test normally.

FIG. 14 shows a timing chart when an error occurs in the same test sequence as that in FIG. When the address 00 is designated at the timing Tb, the cell under test MUT is expected to output the data “00”. However, if the cell under test MUT outputs data “10” due to a failure, the comparator COMP is generated at the clock next to the transition of the signal CEN.
The ERROR output of 0 changes from high level to low level. As a result, it can be confirmed that an error has occurred.
As a result of simulating the test circuit of the embodiment under the above conditions, the ERROR signal of the comparator COMP0 remains at the high level at the time when the marching test is completed, the comparator COMP0 can detect the error normally, and the detection result is kept until the end of the test. I found that I could hold it.

As described above, by constructing the test circuit as shown in FIG. 11 on the chip, one of the variable logic cells can be tested by using another variable logic cell. When the test of the variable logic cell is completed, the cell to be tested can be exchanged, and the test circuit can be rebuilt by using other variable logic cells in the periphery to perform the test. In this case, the test circuit can be constructed by writing the truth value data to the memory circuit of each cell using the scan path in the chip using a personal computer or a workstation, so an expensive tester is used. You can run the test without it.

In the above embodiment, the case where a plurality of variable logic cells are formed on one chip has been described. However, from the above description, for example, the wiring area and the switch matrix are provided in the scribe area of the wafer. Therefore, it is understood that the test circuit is not limited to one chip, and a test circuit can be formed over a plurality of chips to test a variable logic cell on any chip. Furthermore, although the embodiment has been described with respect to a variable logic LSI having a plurality of variable logic cells as shown in FIGS. 1 to 5, particularly when attention is paid to the variable logic cell of FIG. Since the structure is almost the same, the wiring region and the switch matrix are provided in the scribe region in the wafer in which a plurality of memories are formed.
It can be seen that one memory chip can be tested with the other memory chip.

Further, as is apparent from the embodiments shown in FIGS. 8 and 11, the counter circuit can be constructed with only one variable logic cell, and the number of bits can be further increased by using a plurality of cells. Since a large counter circuit can be constructed, it can be used as an address counter. Therefore, even if a DRAM is used as the memory circuit 11 forming the variable logic cell instead of the SRAM, the variable connection circuit formed on the chip or on the wafer constitutes the address counter made of the DRAM. DR that constitutes 11
It can be seen that the DRAM can be used as the memory circuit 11 because the AM can be refreshed.
The chip size can be significantly reduced by using DRAM instead of SRAM.

When the arithmetic circuit of FIG. 9 and the test circuit of FIG. 11 are configured by using the variable logic cells having the DRAM as the memory circuit 11, when the refresh operation is required in the DRAM configuring these circuits. , It is necessary to interrupt the original logic operation, but at this time, if the output data of the DRAM to be refreshed is held in the register 12 during the refresh operation, the logic operation after the refresh is completed is the state before the refresh is started. Can be restarted from.

Further, in recent years, a multi-chip memory having a structure in which a flash memory chip and an SRAM chip are laminated is provided. In such a multi-chip memory, the SRAM chip is tested by the above method or a normal tester, The selected non-defective SRAM chip may be mounted on the back of the flash memory chip, and the SRAMs on the back may be coupled to each other on the test board to form the test circuit to test the flash memory. The flash memory has a long write time, which causes a long test time, which increases the test cost. However, according to the method of configuring the test circuit with the SRAM described above and performing the test, the flash memory chip is tested. Since it is not necessary to use an expensive tester, the test cost can be significantly reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the case where the test circuit is configured at the wafer level or the chip level has been described.
A grid-like wiring group is provided on a test board or an aging board to which C can be mounted, and a variable switch circuit (IC) including a switch capable of connecting and disconnecting arbitrary wirings is provided at the intersection of the wiring groups. It can also be used when a tester is configured with the memory IC attached to the other to test other memory chips.

[0080]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, since the memory circuit can be used to test the memory circuit, a high-performance tester is not required, the test cost can be significantly reduced, and the JTAG boundary scan circuit can be used. The truth value data necessary to configure the test circuit by the circuit without adding a new circuit,
It can be efficiently stored in the memory circuit. Further, since a DRAM can be used as a memory circuit for configuring logic, it becomes easy to increase the scale of logic in a system including a semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a variable logic cell enabling a test method according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of a variable logic cell enabling the test method according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of a variable logic cell enabling the test method according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of a variable logic cell enabling a test method according to the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of a variable logic cell enabling a test method according to the present invention.

FIG. 6 is a circuit configuration diagram showing a configuration example of a main part when a plurality of variable logic cells of the embodiment are arranged to form a variable logic LSI.

FIG. 7 is a circuit diagram showing a configuration example of a variable switch circuit which constitutes the variable logic LSI of FIG.

8 is a circuit configuration diagram showing a connection example when a counter circuit is configured by using two variable logic cells of the embodiment of FIG.

FIG. 9 is a circuit configuration diagram showing a connection example when an arithmetic circuit is configured using the variable logic cell of the embodiment of FIG.

10 is a functional block diagram functionally showing the arithmetic circuit of FIG.

FIG. 11 is a circuit configuration diagram showing a connection example when a test circuit of a memory is configured using eight variable logic cells of the embodiment.

12 is a diagram illustrating a control signal output from a controller cell CONT and an address input to a cell under test MUT in one address period in the test circuit of FIG. 11;
It is a timing chart which shows the example of a timing of data and output data.

13] In the test circuit of FIG. 11, "0" is written to the cell under test MUT while sequentially updating the address, and then data "0" is read and data "1" is written while sequentially updating the address. 6 is a timing chart showing an example of signal timings when an error does not occur in the marching test.

14] In the test circuit of FIG. 11, "0" is written to the cell under test MUT while sequentially updating the address, and then data "0" is read and data "1" is written while sequentially updating the address. 6 is a timing chart showing an example of signal timings when an error occurs in the marching test.

[Explanation of symbols]

10 variable logic cells 11 Memory circuit 12 to 14 registers 20 Relief circuit 30 address scramble circuit 40 variable connection circuit 50 bus SP1-SP3 scan campus

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Rikidai Yamada             293-17 Kamizuruma, Sagamihara City, Kanagawa Prefecture (72) Inventor Kenichi Ichino             5-8-24 Kamima, Setagaya-ku, Tokyo (72) Inventor Takeshi Asakawa             327-19 Gorita, Aso-ku, Kawasaki-shi, Kanagawa (72) Inventor Satoshi Fukumoto             5-10-25-102 Suga, Tama-ku, Kawasaki City, Kanagawa Prefecture (72) Inventor Kazuhiko Iwasaki             Kanagawa Prefecture Yokohama City Kohoku Ward Kishine Town 409-6-504 F term (reference) 2G132 AA08 AB01 AC14 AK07 AK14                       AL00                 5F038 DT03 DT06 DT15 EZ20                 5L106 AA01 AA02 DD08 DD22 DD23                       EE02 GG01

Claims (10)

[Claims] 1. A method of testing a system including a plurality of memory circuits, wherein variable connection means capable of connecting between the plurality of memory circuits is set, and a desired memory circuit among the plurality of memory circuits is set. , Storing data for outputting data corresponding to a desired logical value to the address input through the variable connection means, thereby forming the desired memory circuit as a test circuit, and using the test circuit. A test method for testing a memory circuit to be tested among the plurality of memory circuits. 2. The plurality of memory circuits are circuits formed on one semiconductor chip, and the variable connection means are formed on the same semiconductor chip as the plurality of memory circuits. The test method according to claim 1. 3. The memory circuit according to claim 1, wherein the plurality of memory circuits are circuits formed on one semiconductor wafer, and the variable connection means is formed in a divided region of the semiconductor wafer. Test method. 4. A first register connected to an address input terminal of a corresponding memory circuit and capable of a shift operation is provided for each of the plurality of memory circuits, and the test circuit of the plurality of memory circuits is configured. Address data for instructing an address for storing truth value data for outputting data corresponding to a desired logical output with respect to a predetermined address input to the first register corresponding to the memory circuit to be serially supplied. The truth value data is serially supplied to the second register corresponding to the memory circuit which should form the test circuit, and the data is stored in the memory circuit by the data of the first and second registers to execute the test circuit. The test method according to claim 1, wherein the test method is configured. 5. A shiftable second register connected to a data input / output terminal of a corresponding memory circuit is provided for each of the plurality of memory circuits, and a predetermined address is input to the memory circuit. The truth value data for outputting the data corresponding to the logical output of
5. The test circuit is constructed by serially supplying the register and storing the truth value data held in the second register at a desired address of the memory circuit. The test method described in Crab. 6. A scan path in which the first register and the second register are connected in series is configured to output data corresponding to a predetermined logic output to the memory circuit for a predetermined address input. Of the truth value data and address data designating an address for storing the truth value data are supplied to the first register and the second register through the scan path and held in the first register. 6. The test circuit according to claim 5, wherein the memory circuit is operated by the address data and the truth value data held in the second register is stored in the selected address to form a test circuit. Test method. 7. A plurality of variable logic circuits each having a memory circuit and capable of forming an arbitrary logic by storing predetermined truth value data in the memory circuit, and a first direction along the plurality of variable logic circuits. And a second wiring group arranged in the second direction, and a plurality of wirings provided at an intersection of the first wiring group and the second wiring group and capable of connecting and disconnecting arbitrary wirings. Variable switch circuit, each of the plurality of variable logic circuits comprises a shiftable register connected to a data input terminal of the memory circuit, and the registers of the plurality of variable logic circuits are connected in series. A semiconductor device having a scan path connected to the. 8. The memory circuit has a data input terminal and a data output terminal in common, and the register connected to the common terminal is composed of a register capable of bidirectionally parallel input / output of data. 7. The method according to claim 7, wherein
The semiconductor device according to. 9. A plurality of variable logic circuits, each of which has a memory circuit and can form an arbitrary logic by storing predetermined truth value data in the memory circuit, and a first direction along the plurality of variable logic circuits. And a second wiring group arranged in the second direction, and a plurality of wirings provided at an intersection of the first wiring group and the second wiring group and capable of connecting and disconnecting arbitrary wirings. And a variable switch circuit according to claim 1, wherein the memory circuit is formed of a dynamic memory circuit having a memory cell including a capacitance for accumulating information charges and a selection switch. 10. A scan path in which the plurality of variable logic circuits each include a shiftable register connected to a data input terminal of the memory circuit, and the registers of the plurality of variable logic circuits are connected in series. The semiconductor device according to claim 9, wherein the semiconductor device is provided.