JPH0799000A - Method and circuit for testing ram block - Google Patents

Abstract

PURPOSE:To reduce external terminals for testing parallel separation of plural RAM blocks. CONSTITUTION:In an address/data generation circuit 30, when a RAM block test state is specified by a test mode specifying line 6, a counter is reset by a signal from a reset input terminal 36, and an address, the data and a control signal for test are generated by a clock from a clock input terminal 35 to be outputted to a RAM block 2a, etc., through an ink put selector 20a, etc. By a comparator 31, the read data received through an output selector 21a, etc., is compared with the expected value data received from the address/data generation circuit 30 by the line 33, and where they disagree, an error signal is outputted to a test result output terminal 37.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a plurality of RAM blocks, and more particularly to a RAM block test circuit.

[0002]

2. Description of the Related Art In the field of semiconductor integrated circuits, ASICs for realizing individual requirements of users are developed by easily combining functional macros and random logic circuits as represented by gate arrays and cell-based ICs. It is said that the demand will continue to increase in the future because it can be designed.

Now, the gate array and the cell-based IC A
The memory represented by the RAM block in the SIC is
When a user designs a circuit, in addition to the primitive block that is a logic circuit cell, it is the most basic and indispensable function macro. The ASIC vendor prepares libraries and test patterns in advance, I try not to burden myself. In particular, in an ASIC such as a cell-based IC that can mount a large number of functional hard macros other than RAM blocks, individual tests of the hard macros mounted on the same mounted chip are performed so as not to burden the user. The RAM block is tested by using (such as CB-C7 manufactured by NEC).

However, recently, because of the above advantages, RAMs having different numbers of bits and words in the same chip
In many cases, a block or several large-capacity RAM blocks are mounted, which causes problems such as an increase in test time and the number of test patterns.

A conventional test circuit in which three RAM blocks are mounted on the same chip will be described below.

FIG. 2 is a block diagram of a conventional example of a RAM block test circuit when three RAM blocks are mounted. The RAM block test circuit shown in FIG. 2 includes RAM blocks 2a, 2b and 2c of the main body and RAM blocks 2a and 2
It is composed of input selectors 20a, 20b and 20c for selecting a test signal input to and output from b and 2c and a normal signal, and output selectors 21a, 21b and 21c.

When the normal operation state is designated by the test mode designation line 6, the input selectors 20a, 20b, 2
0c selects the internal address lines 7a, 7b, 7c, the internal write data lines 8a, 8b, 8c and the internal control signal lines 9a, 9b, 9c, respectively, and the address input lines 3a, 3
RAM blocks 2a, 2 via write data lines 4a, 4b, 4c and control signal lines 5a, 5b, 5c.
Address signals, write data, and control signals such as a chip select signal, a write signal, and a read signal are supplied to b and 2c. And output selectors 21a, 21b, 2
Reference numeral 1c denotes the read data 13a, 13b, 13c from the RAM blocks 2a, 2b, 2c and the internal read data line 14
a, 14b, 14c. That is, in the normal operation state, the RAM blocks 2a, 2b, 2c interface with the internal circuits of the semiconductor integrated circuit 51.

Next, the RAM is set by the test mode designation line 6.
When the block test state is designated, the input selectors 20a, 20b, 20c respectively detect the test address line 1
0a, 10b, 10c, test write data line 11a,
11b and 11c and test control signal lines 12a and 12
b, 12c to select the address input lines 3a, 3b, 3
c, write data lines 4a, 4b, 4c and control signal lines 5a, 5b, 5c, RAM blocks 2a, 2b,
An address signal, write data, and control signals such as a chip select signal, a write signal, and a read signal are supplied to 2c. And output resists 21a, 21b, 21c
Reads the read data 13a, 13b, 13c from the RAM blocks 2a, 2b, 2c on the test read data line 15
a, 15b, 15c. As a result, the RAM blocks 2a, 2b, 2c can be directly accessed from the outside by through, and the test patterns prepared in advance can be applied regardless of the internal circuit configuration.

In the case of FIG. 2, all the terminals of the three RAM blocks are directly exposed to the outside at the same time, so that the three RAM blocks can be tested at the same time. However, for example, 51
If there are three 2 word × 8 bit RAM blocks, 9 × 3 = 27 for address input, 8 × 3 = 24 for data input, 8 × 3 = 24 for data output.
Book, control signal (read, write, chip select signal)
For this purpose, a total of 84 external terminals, 3 x 3 = 9, are required for testing at the same time.

[0010]

The conventional RAM described above.
In the block test circuit, when the test mode of the RAM block is designated, all terminals of the RAM block are external terminal throughs of the semiconductor integrated circuit, and a direct external test is possible regardless of the internal circuit of the semiconductor integrated circuit. However, when testing a plurality of RAM blocks in parallel at the same time, a large number of test pins are required for the test, and it is impossible to use the test method in an ASIC having a small number of pins. there were. Then, a method of testing the RAM blocks one by one in order to solve the above-mentioned drawbacks can be considered, but in this case, there is a trade-off problem that the test time is conversely long.

An object of the present invention is to provide a semiconductor integrated circuit with a RAM which does not require a large number of external terminals for testing in order to simultaneously test a plurality of RAM blocks in parallel.
It is to provide a block test circuit.

[0012]

SUMMARY OF THE INVENTION A RAM block test circuit according to the present invention externally supplies an address for writing a RAM block, write data, expected value data, and a control signal for controlling a read / write operation of the RAM block. An address / data generation circuit generated by a clock is compared with read data from a plurality of RAM blocks and the expected value data, and an error signal is output when the read data does not match the expected value data. And a comparator.

[0013]

Since one address / data generation circuit generates an address and data for a test and a RAM block separation test is performed by comparison with one comparator,
Even if the number of RAM blocks is large, the number of external terminals for testing is small, the configuration of the semiconductor integrated circuit is easy, and the test time and the number of test patterns do not increase.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a RAM block test circuit of the present invention.

The semiconductor integrated circuit 1 includes a RAM block 2a,
2b and 2c and input selectors 20a, 20b and 20c,
It is composed of output selectors 21a, 21b, 21c, an address / data generation circuit 30 for a test circuit, and a comparator 31 for the test circuit. RAM blocks 2a, 2b, 2c and input selectors 20a, 20b, 2
0c, the output selectors 21a, 21b and 21c function in the same manner as in the conventional example shown in FIG. However, input selector 2
Address / data generation circuit 3 is the input destination of the address, write data, and control signal at the time of testing 0a, 20b, 20c.
The read data output destination when the output selectors 21a, 21b, and 21c are tested is the comparator 31.

Therefore, when the normal operation state is designated by the test mode designation line 6, the input selector 20
a, 20b and 20c are internal address lines 7a and 7a, respectively.
b, 7c, internal write data lines 8a, 8b, 8c and internal control signal lines 9a, 9b, 9c are selected, and address input lines 3a, 3b, 3c, write data lines 4a, 4b,
4c and control signal lines 5a, 5b, 5c, RAM
An address signal, write data, and control signals such as a chip select signal, a write signal, and a read signal are supplied to the blocks 2a, 2b, 2c. And output selector 2
1a, 21b and 21c are RAM blocks 2a, 2b and 2
The read data 13a, 13b, 13c from c is sent to the internal lead wires 14a, 14b, 14c. That is, in the normal operation state, the RAM blocks 2a, 2b, 2c interface with the internal circuits of the semiconductor integrated circuit 1.

The address / data generation circuit 30 has a built-in counter (not shown). When the RAM block test state is designated by the test mode designation line 6, the address / data generation circuit 30 enters the operating state and is reset by the reset signal from the reset input terminal 36. The internal counter is reset, and the clock signal from the clock input terminal 35 sequentially increments the counter to increase the RA of a predetermined address, write data, chip select signal, and write enable signal.
A control signal for writing to the M blocks 2a, 2b, 2c is output. At this time, the input selectors 20a, 2
0b and 20c are RAMs by the test mode designation signal line 6
Since the block test mode is specified, each signal generated by the address / data generation circuit 30 is received via the test address line 40, the test write data line 41, and the test control signal line 42, and the address input line 3
a, 3b, 3c, write data 4a, 4b, 4c and control signal lines 5a, 5b, 5c to write data to the RAM blocks 2a, 2b, 2c. address/
When the internal counter overflows, the data generation circuit 30 sequentially performs a predetermined address, expected value data, chip select signal, and read enable in order to perform a data read operation from the RAM blocks 2a, 2b, 2c, similarly to the write operation. Output a signal. At this time, the expected value data is the same as the write data and is directly output to the comparator 31 through the expected value data line 33 without going through a selector or the like. Output selectors 21a, 21
b and 21c receive the read data from the RAM blocks 2a, 2b and 2c via the read data lines 13a, 13b and 13c and send them to the test read data lines 15a, 15b and 15c when the RAM block is tested.

The comparator 31 uses the test mode designation line 6
Thus, when the RAM block test mode is specified, the three read data from the RAM blocks 2a, 2b, 2c read by the data read operation of the RAM block are output selectors 21a, 21.
test read data lines 15a, 15 from b, 21c
It is received via b and 15c and collated and compared with the expected value data 33 from the address / data generation circuit 30 for each address. If there is a mismatch, an error signal is output to the test result output terminal 37.

Next, the address / data generation circuit 30
When the internal counter overflows, the address / data generation circuit 30 sends write data different from the first time with the address, and from the next overflow, a read operation is performed and the comparator 31 performs the same comparison as described above. Let

The above processing is repeated with write data having different values required for the test, and the RAM block is tested.

In this RAM block test circuit, one address / data generation circuit supplies a common address / data to all the RAM blocks to the three RAM blocks in the semiconductor integrated circuit 1, and the comparator uses the comparator. The three RAM blocks have a structure in which read data is collectively compared and an error signal is output to the outside when they do not match.

Therefore, in the conventional isolation test of a plurality of RAM blocks, for example, in the case of three 512 word × 8 bit RAM blocks in FIG. 2, 84 test external terminals are required. In this case, since only three external terminals are required, the amount of test patterns can be small and a plurality of RAM blocks can be tested in parallel even when the number of external terminals is small, so that the test time can be shortened.

RAMs having different numbers of bits and words
Regarding the case where multiple blocks are built in,
When the number of bits is different, the write data is directly input to the input of the comparator 31 for the portion having the insufficient number of bits, and when the number of words is further different, when the non-target address is input to the RAM block. The write data is directly read data lines 13a, 13b, 13
The RAM block may be configured to output from c. This method is not particularly limited without departing from the scope of this embodiment.

Furthermore, a BIST (Built) similar to that of this embodiment is used.
Although there is also a t-In Self Test circuit, in the present application, the comparison with the read data from a plurality of RAM blocks by the comparator 31 is different from the comparator of the conventional BIST circuit.

[0026]

As described above, according to the present invention, a common address / data is provided to a plurality of RAM blocks of a semiconductor integrated circuit by one address / data generation circuit for all addresses of the plurality of RAM blocks. Supply in parallel,
A single comparator compares read data from multiple RAM blocks at once, and outputs an error signal to the outside if they do not match, regardless of the number and capacity of built-in RAM blocks. Since the number of terminals can be reduced to only three, the RAM block can be tested in parallel even if the number of external terminals of the semiconductor integrated circuit is small, and the test time can be shortened.

Further, in the present invention, even if the number of built-in RAM blocks is any, it can be constituted by one address / data generation circuit and the comparator, so that the conventional BIS can be used in advance.
Compared to the case where a RAM block having a built-in T circuit is combined, the test circuit can be configured with a smaller amount of hardware and a smaller number of test terminals, the semiconductor integrated circuit can be easily configured, and only the test time is required. Not
This has the effect of avoiding an increase in test patterns.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a RAM block test circuit of the present invention.

FIG. 2 is a block diagram of a conventional example of a RAM block test circuit.

[Explanation of symbols]

 1 semiconductor integrated circuit 2a, 2b, 2c RAM block 3a, 3b, 3c address input line 4a, 4b, 4c write data line 5a, 5b, 5c control signal line 6 test mode designation line 7a, 7b, 7c internal address line 8a, 8b, 8c internal write data line 9a, 9b, 9c internal control signal line 10a, 10b, 10c test address line 11a, 11b, 11c test write data line 12a, 12b, 12c test control signal line 13a, 13b, 13c read data line 14a, 14b, 14c Internal read data line 15a, 15b, 15c Test read data line 20a, 20b, 20c Input selector 21a, 21b, 21c Output selector 30 Address / data generation circuit 31 Comparator 33 Expected value data line 35 Clock input terminal 36 Re Set input terminal 37 Test result output terminal 40 Test address line 41 Test write data line 42 Test control signal line

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[Procedure amendment]

[Submission date] March 14, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Patent application title: RAM block test method and circuit

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit containing a plurality of RAM blocks, and more particularly to a RAM block test method and circuit.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010]

The conventional RAM described above.
In the block test method , when the test mode of the RAM block is designated, all terminals of the RAM block are external terminal throughs of the semiconductor integrated circuit, and a direct external test is possible regardless of the internal circuit of the semiconductor integrated circuit. However, when testing a plurality of RAM blocks in parallel at the same time, a large number of test pins are required for the test, and it is impossible to use the test method in an ASIC having a small number of pins. there were. And Is al in a method is also conceivable to perform the test of the RAM blocks one by one in order to solve the above drawbacks, in this case the test time reversed had problems antinomy is called long.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

An object of the present invention is to provide a semiconductor integrated circuit with a RAM which does not require a large number of external terminals for testing in order to simultaneously test a plurality of RAM blocks in parallel.
A block test method and circuit are provided.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

RAM block of the present invention
The test method is an address for testing the RAM block.
Memory, write data, expected value data and RAM block
External control signals for controlling read / write operations
Of the RAM blocks,
Compare the read data from the lock with the expected value data
However, the read data does not match the expected value data.
If there is, an error signal is output. The RAM block test circuit of the present invention is an address / data generation circuit that generates an address for writing a RAM block, write data, expected value data, and a control signal for controlling the read / write operation of the RAM block from an external clock. And a comparator that compares read data from a plurality of RAM blocks with the expected value data and outputs an error signal when the read data does not match the expected value data.

Claims (1)

[Claims] 1. A semiconductor integrated circuit including a plurality of RAM blocks, comprising: a RAM block test circuit for performing a separation test of the RAM blocks; an address, a write data, an expected value data and a test data for the RAM block; An address / data generation circuit that generates a control signal for controlling the read / write operation of the RAM block by an external clock is compared with the read data from the plurality of RAM blocks and the expected value data. A RAM block test circuit, comprising: a comparator that outputs an error signal when the expected value data does not match.