JPS63148498A - Memory device with self-disagnosing function - Google Patents

Abstract

PURPOSE:To execute self-diagnosis in a short time even if the capacity of a memory device in large by executing reading and writing action at high speed through the use of a data reproducing function which is added to the memory device, logically comparing data read out by means of the reading action with an expected value, and executing self-diagnosis. CONSTITUTION:With using high speed write function, data for self diagnosis is written in an address area to be diagnosed. In such a case, data inverters 80A and 80B write data in respective address with the value inverted to '1' or '1' in respective address. If writing terminates, a read/write controller 50 is set in a data reproducing mode, and it executes the action of reproducing written data other address area. A logical comparator 100 compares having read data with the expected value and decides quality. If non-coincidence is detected, a failure generation address is transmitted to a test processor so as to display that the address is a failure. Thus, a diagnosing speed can considerably be increased, and the self-diagnosis can be terminated in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a memory device used in, for example, semiconductor testing equipment.

BACKGROUND OF THE INVENTION A semiconductor testing device that tests IC memories and the like is equipped with a large-capacity storage device that stores pattern signals used in testing. This memory device uses semiconductor memory elements to enable high-speed reading and writing. When a semiconductor memory device is used as a storage device, if even one memory cell in the device is faulty, a defect will occur in the turn signal used for testing, making the test results unreliable.

For this reason, semiconductor test equipment has traditionally been equipped with a function to self-diagnose whether or not the storage device that stores pattern signals etc. is normal at the beginning of use, and if the storage device is normal as a result of the self-diagnosis, the test is started. ing.

"Prior Art" FIG. 3 shows a conventional storage device for an IC testing device equipped with a self-diagnosis function. In the figure, 1 is a storage device to be diagnosed, 2 is a test processor, and 3 is an external storage device.

The IC test operation is performed as follows.

First, a test pattern signal is transferred from the external storage device 3 to the storage device 1 under the control of the test processor 2 and written at high speed by the high-speed writing means. The test pattern signal is read out and tested externally.) The z4 turn signal is sent and applied to the IC under test (not particularly shown).

Here, the following functions are added to read the test turn signal.

■ A function to read out and send out test pattern signals stored from a specified address to a specified address in the storage device 1 at high speed, and ■ test pattern signals stored from a specified address to a specified address in the storage device 1)
Z? This function is to transfer the turn signal to another storage area in the storage device 1 at high speed.

In order to execute these two functions, there is a start address pointer 10 that sets the start address of the address area to be read and written, a destination address pointer 20 that specifies the start address of the destination address area to be rewritten, and a destination address pointer 20 that specifies the start address of the address area to be rewritten. A word counter 30 for specifying the address area to perform the reading, a zero detector 4o for detecting completion of reading and writing of the specified address area, a read/write controller 50, and a clock generator 60. It is provided.

Start address pointer 10 and destination address pointer 2
For 0, a presettable up/down counter is used, and by switching the address multiplexer 4, a start address and a destination address are given from the test processor 2, and the start address and destination address are preset.

Start address pointer 10 and destination address pointer 2
The starting address and the destination address that have been reset to 0 are selected by the multiplexer 5 and provided to the storage device 1.

When reading and writing, start address pointer 1
Every time the start address that has been reset to 0 is given to the storage device 1 and read or written, the start address pointer 10 counts by +1 or -1 according to the set mode, and the address of the storage device 1 is increased by +1. Or increment by -1.

When transferring data, start address pointer 1
0 and the Grisenode value of the destination address pointer 20 are alternately applied to the storage device 1.

That is, with the precent value of the head Azores pointer 10 being given to the storage device 1, the read/write controller 50 reads the data stored at that address from the storage device 1 and stores it in the register 6. Next, multiplexer 5
selects the destination address pointer 20, gives its reset value to the storage device 1, and accesses the destination address of the data. When this access is completed, the read/write controller 50 applies the read data from the data reno star 6 to the storage device 1 through the multiplexer 7, and writes the data to the destination address.

When reading and writing are completed, the start address pointer 10
The destination address pointer 20 counts by +1 or -1 according to the designated mode, and increments the read address of the storage device 1 and the destination address by +1 or -1.

On the other hand, the word counter 30 is constituted by a presettable down counter, for example, and is given the number of words from the test processor 2 to determine the area to be read or written, and is preset with the number of words.

The word counter 30 performs a subtraction operation by -1 every time the storage device 1 advances by one address, and when the number of advances reaches the precented value, the zero detector 110 detects the state and performs read/write control. A detection signal is sent to the device 50 to stop its operation.

In this way, the operation of writing a test pattern signal at a high speed into a desired address area of the storage device 1, and the operation of reading out the TEST)/F turn signal written in the address area at a high speed and sending it to others, Furthermore, the structure is such that an operation is performed to transfer the written test signal to another storage area.

By the way, in order to diagnose whether each memory cell of the memory device 1 is normal or not, conventionally, data for self-diagnosis is written to each address of the memory device 1 by a command from the test processor 20, and the data is read and sent to the test processor 2. , the test processor 2 compares it with the expected value to determine pass/fail.

"Problems to be Solved by the Invention" Conventionally, self-diagnosis has been carried out by the test processor 2. Therefore, the speed of diagnosis is Test Zorocessor 2.
This method has the disadvantage that the execution speed is 100%, and the diagnosis time is long. In particular, since the storage device 1 provided in the IC tester has a large storage capacity of, for example, 16 Mbytes, a relatively long time is required for self-diagnosis.

Incidentally, in the case of 16MB, the time will be about the same as that of the second common law.

An object of the present invention is to provide a storage device equipped with a self-diagnosis function that can significantly shorten the time required for self-diagnosis.

"Means for Solving Problems" In this invention, in addition to the conventionally provided head address pointer, destination address pointer, word counter, zero detector, read/write controller, clock generator, etc. A diagnostic data register that holds diagnostic data; a data inverter that inverts the data value to "1" and "0" for each address when writing self-diagnostic data;
A word register that holds the number of words that determines the area to perform self-diagnosis, a multiplexer that reloads the word counter by giving the number of words held in this word register to the word counter every time the value of the word counter reaches zero, and a diagnostic area. The structure includes a logical comparator that compares data read from each address with an expected value.

"Operation" According to the configuration of the present invention, self-diagnosis data is written into the address area to be diagnosed using a conventional high-speed write function. In this case, the data value is inverted to "1" and "0" for each address by a data inverter and then written to the hook address.

When writing is completed, the read/write controller is set to a data transfer mode and executes an operation to transfer the written data to another address area.

In this case, by setting the destination address to be the same as the read address, the read data is rewritten to the same address again.

The read data is compared with an expected value by a logical comparator to determine whether it is good or bad. If a mismatch is detected, the address where the defect occurred is sent to the test processor, and it is displayed that the address is defective.

As described above, according to the present invention, the conventional high-speed writing function and data transfer function are used to write and read data for self-diagnosis, and the logic comparator is used to determine pass/fail. Diagnosis speed can be significantly increased compared to when a processor is used to determine pass/fail. Therefore, self-diagnosis can be completed in a short time.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals.

The parts added by this invention are a self-diagnosis data renostaph 0 that holds self-diagnosis data during self-diagnosis, and data held in this self-diagnosis data register 70 that is set to "1" and "1" for each address. A data inverter 80A that inverts the data "O" and supplies it to the storage device 1, and a word register 90 provided to reload the set value W to the word counter 30 each time the count value of the word counter 30 becomes zero.
, a data inverter 80B that generates an expected value, a logic comparison that provides an inversion command signal to the data inverters soA and soB as necessary, and a logical comparison that compares the data read from the storage device 1 with the expected value. 100.

The self-diagnosis data register 70 includes a test processor 2.
Self-diagnosis data is sent from the test processor 2 at an early stage of execution of the self-diagnosis program and is stored. The self-diagnosis data stored in the self-diagnosis data register 70 is supplied to the storage device 1 through the data inverter 80A.

The data inverter 80A is supplied with a signal that alternately repeats "1" and "0" for each address through the data GA, and this inverted signal causes the data stored in the self-diagnosis data register 70 to be changed to "1" and "0" for each address. '' is inverted to "0" and supplied to the storage device 1, which is stored in the designated address area.

This write operation is performed in cooperation with the word counter 30 and the start address pointer 10 that defines the start address for writing, as described above.

In other words, the address from the first address written in the starting address pointer 10 to the address corresponding to the number of words written in the word counter 30 is specified, and the self-diagnosis in which "1" and "0" are inverted for each address in the address area is specified. Write data for This write operation is performed in section A shown in FIG.

Here, by setting the starting address AA as the starting address of the storage device 1 and setting the number of words W to the total number of addresses in the storage device 1, the entire address area from the starting address AA to the final address AZ of the storage device 1 can be specified. I can do it. Further, it is also possible to specify a part of the address area of the storage device 1 as necessary.

When the self-diagnosis data is written to the specified address, the zero detector 40 detects that the count value of the word counter 30 has become zero, and reads out the detection signal from the write controller 5.
0 to switch the operation mode to data transfer mode.

In the data transfer mode, data is read from the address specified by the start address pointer 10, and the logical comparator 100 compares the data with an expected value, and at the same time, the data is written to the address set in the destination address register 20. During self-diagnosis, the address set in the head address pointer 10 and the destination address are set to the same address, so data is rewritten to the read address.

Here, the start address pointer 10 and the destination address pointer 20 are switched to the down count mode when the data transfer mode)'[is switched, and the data transfer operation advances from the final address AZ to the first address. It is done while

Furthermore, when the final address AZ is reached and the data transfer mode is switched, the number of words set in the word register 90 is transferred to the word counter 3 through the multi-blephr 8.
0 and reload. Therefore, the data transfer operation is executed until the value of word counter 30 becomes zero.

This state is shown in section B of FIG.

When the data transfer operation is performed up to the start address AA, the zero detector 40 detects that the count value of the word counter 30 has become zero, gives the detection signal to the read/write controller 50, and sends the data to the start address AA. Pointer 10 and destination ato V7.1! '(7fi20 is switched to up-count mode and the number of words held in the word register 90 is reloaded into the word counter 30 through the multi-blephr 81!.

With this switching, the data transfer operation is performed in section C in Figure 2.
As shown in FIG. 3, the execution is performed while the start address AA is also incrementing toward the end address AZ.

All data read from each address during a data transfer operation is compared with an expected value in logic comparator 100. The expected value is obtained by taking out the self-diagnosis data held in the data register 70 through the data inverter 80B, and combining the expected value data with "1" and "0" inverted for each address and the data read from the storage device 1. The comparison is made to determine whether there is a match or a mismatch, and when a mismatch occurs, a signal indicating the occurrence of a defect is sent from the logic comparator 100 to the test processor 2, and a defective address is sent from the address register 110 to the test processor 2. The presence of a defect and its address are displayed on the display attached to the device.

"Effects of the Invention" As explained above, according to this invention, the data transfer function added to the storage device L is used to perform read/write operations at high speed, and the read/write operations are performed at high speed. Since the system is configured to perform self-diagnosis by logically comparing the obtained data with expected values, self-diagnosis can be performed at high speed. Therefore, even if the storage device 1 has a large capacity, self-diagnosis can be performed in a short time.

Incidentally, the time for self-diagnosing the 16 Mbyte storage device 1, which was conventionally 120 seconds, has been reduced to about 2 seconds.

Furthermore, since the present invention effectively uses the conventional functions, the increase in cost is small, but the advantage is that the self-diagnosis time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining one embodiment of the present invention, FIG. 2 is a graph for explaining the invention in detail,
FIG. 3 is a block diagram for explaining a conventional storage device with a self-diagnosis function. 1...Storage device, 2...Test processor, 3...
・External memory, 4, 5, 7.8... multiplexer,
10...Start address pointer, 20...Destination address pointer, 30...Word counter, 40...
・Zero detector, 50...Read/write controller, 60...
Clock generator, 110...Address reno star.

Claims (1)

[Claims] (1) A. A high-speed transfer means that reads the written data at high speed and transfers the data to another device; B. Reads the written data and rewrites the data to another address. C. An address pointer that provides the address at which the high-speed transfer means and rewriting means start their operations; D. Executing the high-speed transfer operation and rewriting operation from the address set by this address pointer. A word counter that stores the number of words; E, a detector that detects when the contents of the word counter reach a predetermined value; and F, a logical comparator that compares the read data with an expected value. A storage device equipped with self-diagnosis functions.