JPH08184645A - Semiconductor integrated circuit and test method therefor - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit comprising a plurality of ROM blocks in which the number of external terminals required for the parallel test of the ROM block is decreased and the test time is shortened drastically. CONSTITUTION: Data read out from a plurality of ROM blocks 2a, 2b, 2c, corresponding to the address data inputted from an address input terminal 4, are added or subtracted. The results are delivered through a buffer 5 to a read data output terminal 3. The terminal is monitored externally and a test is carried out through collation with an expected value data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and its testing method, and more particularly to a plurality of ROMs (read only
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a circuit for testing a memory block and a method for testing the same.

[0002]

2. Description of the Related Art In the field of semiconductor integrated circuits, AS (Applicati) for realizing individual requirements of users.
It is said that the demand for on-specific (IC) ICs will continue to increase, as it can be developed and designed by easily combining functional macros and random logic circuits as represented by gate arrays and cell-based ICs. There is.

Now, the gate array and the cell-based IC A
In SIC, the memory is the most basic and indispensable function macro in addition to the primitive block which is a logic circuit cell in designing a user circuit.
The IC vendor prepares libraries, test patterns, and the like in advance so as to avoid burdening the designing user.
Among various memories, a programmable memory typified by a ROM can store user-specific data, parameter information, and the like in a small occupied area in the chip, so that its mounting requirement is strong. In recent years, in response to the diversification and complexity of mounting devices, a plurality of ROM blocks having different numbers of bits and words have been mounted in the same chip. Below are multiple ROMs in the same chip.
The conventional test circuit when the block is mounted and its operation will be described.

FIG. 3 is a block diagram of a conventional example of a ROM block test circuit when three ROM blocks are mounted. A semiconductor integrated circuit 1 having the ROM block test circuit shown in FIG. 3 has ROM blocks 2a, 2b and 2c each having a data width of 8 bits and the ROM blocks 2a and 2c.
Buffers 5a, 5b and 5c for storing read data of b and 2c are built-in. Other test mode designating circuits, ROM read signals, etc. are omitted in the drawing. Further, a control circuit and the like for performing a predetermined normal read operation are built in, but not shown.

In this block diagram, when the semiconductor integrated circuit 1 is designated as the ROM test mode, that is, the ROM code sweep mode, each of the ROM blocks 2a, 2b, 2 is supplied from a predetermined number of address input terminals 4.
Common address data is input to c, and the buffers 5a and 5a are driven by an internal read signal and a predetermined latch signal.
The read data of each ROM block is stored in b and 5c. Then, the stored data is directly output from the read data output terminals 3a, 3b, 3c and collated with the expected value data externally. In the case of this conventional example, since three ROM blocks having an 8-bit data width are built in, if three blocks are tested in parallel at the same time, in addition to the number of address input terminals, 24 test output terminals 3 are provided.
a, 3b, 3c are required.

However, in the case of a semiconductor integrated circuit in which the number of external terminals that can be used for the test is small, the test cannot be performed at the same time. Therefore, the buffers 5a, 5b,
The data stored in 5c are stored in the buffer 5 in order.
a, 5b, 5c in this order, for example, the read data output terminal 3
Some of them are provided with a switching means so as to output only from a, but such a read configuration has a drawback that a test cannot be efficiently performed because a read time of three times is required.

On the other hand, referring to FIG. 4 showing a ROM4 read test circuit described in Japanese Patent Laid-Open No. 63-288500, this test circuit is provided for each of the ROMs 50 and 51 and reset when a ROM test signal is input. ROM address generation circuits 52 and 53 for outputting address signals incremented from the address at the same predetermined timing to the ROMs 50 and 51, respectively, and the ROM 5
RO which is provided for each 0, 51, temporarily stores the data detected from the ROM 50, 51, and outputs it to the data bus.
The ROM test read signal 60 for reading the data of the ROMs of the same address held in the M data read buffers 55, 56 and the ROM data read buffers 55, 56 is supplied to the ROM data read buffers 55, 5 respectively.
ROM test read signal generation circuit 57 for outputting to 6
And a ROM test address generation circuit 58 for outputting a selection control signal for selecting the ROM data read buffers 55 and 56 to the respective ROM data read buffers 55 and 56, and a ROM test signal during the ROM read test to the external circuit and the ROM. Address generation circuit 53, ROM
The data is output to the data read buffers 55 and 56, the ROM test read signal generation circuit 57, and the ROM test address generation circuit 58 to prohibit access to the ROM by an external circuit, and the ROM data read buffers 55 and 5 are output.
6. ROM test read signal generation circuit 57 and RO
RO for enabling the M test address generation circuit 58
And an M test signal generation circuit 54.

Alternatively, the ROM test read signal 60
The same publication also discloses a configuration in which a ROM data switching circuit that inputs data as a selection signal, selects the data read in parallel from each ROM, and outputs the data for each ROM.

Here, in the former ROM read test circuit, the plurality of ROM address generation circuits 52 and 53 are simultaneously operated to simultaneously read data from each of the plurality of ROMs 50 and 51 to read the respective ROM data read buffers 55 and 56. After that, the ROM data read buffers 55 and 56 are sequentially selected to output the data onto the internal data bus 59. The latter ROM read test circuit operates the ROM address generation circuit,
Data read simultaneously from each of the plurality of ROMs forming the composite ROM is selected by the ROM data switching circuit, and the data is output to the internal data bus via the ROM data read buffer.

It is described that the read test time of the ROM can be further shortened by reading the plurality of ROMs simultaneously.

[0011]

The above-mentioned ROM of FIG.
In the block test circuit, read data from a plurality of ROMs are monitored in parallel bit by bit at the external terminals 3a, 3b, 3c, respectively. Therefore, in such a parallel test, a large number of test terminals are required. Becomes Therefore, in a semiconductor integrated circuit having a small number of external terminals, there is a drawback that parallel testing is impossible. Furthermore, when this test method is used, the read data test pattern requires a pattern capacity of 8 bits × the total number of words of all ROMs, which occupies most of the pattern memory of the LSI tester, and other additional purposes. It also had the drawback of running out of memory.

Further, according to the conventional technique shown in FIG. 4, data is read in parallel from a plurality of ROMs 50 and 51, and the respective data read in parallel are selected and output to the internal data bus 59. As a result, a large number of RO
Although there is an effect that the read test time of M50 and M51 can be relatively shortened, there is no dedicated data bus and the internal data bus used in the normal mode is used. Therefore, this internal data bus is also used in the test mode. However, there is a problem that more test information cannot be obtained, and it is necessary to read all the memory data in the ROM and temporarily store it, which not only increases the memory capacity of the tester, but also increases the memory capacity. , It was not possible to dramatically reduce the read time.

In view of the above problems of the prior art, the present invention has the following problems. (1) Dramatically shorten the data read time during the test. (2) Reduce the amount of read data. (3) The number of test patterns on the tester side, that is, the storage capacity is small. (4) The I / O bus used in the normal mode is free even while the semiconductor integrated circuit is operating in the test mode, and data can be output from this I / O bus as necessary. .
(5) Minimize the increase in the number of external test terminals.
(6) The test time can be shortened even with ROM blocks having different numbers of bits and words.

[0014]

According to the structure of the present invention, in a semiconductor integrated circuit having a plurality of ROM blocks built in on a semiconductor substrate, the storage data of a common address in the plurality of ROM blocks is united by a predetermined number of bits. It is characterized in that a calculation means for adding or subtracting each other and an output means for outputting the data calculated by the calculation means to the outside are provided on the substrate.

In particular, the output means has a function of outputting by adding 2 bits for carry in addition to the predetermined number of bit units, and in particular the output means has the plurality of ROM blocks. It is also characterized in that it has a switching means for selectively outputting the calculated value data obtained by calculating only the corresponding storage data in two of the ROM blocks, and more particularly, the calculating means is a ROM having no common address among the plurality of ROM blocks. When there is a block, it has a part without the common address.

The test method of the present invention is characterized in that the pass / fail judgment is performed by comparing the calculated value data from the calculating means with the expected value data prepared in the tester.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the block diagram of FIG. 1 showing a semiconductor integrated circuit according to a first embodiment of the present invention, this semiconductor integrated circuit 7 stores data stored in three ROM blocks 2a, 2b, 2c to each other. It is provided with an adder circuit 6 for adding, a 10-bit storage buffer 5 for temporarily storing the added value of the adder circuit 6, and ten read data output terminals 3 for deriving the output of the buffer 5 to the outside. Other than that,
Since it is common to the conventional FIG. 3, the common parts will not be described in detail. In FIG. 1, a predetermined read control circuit for testing, a control circuit used during normal operation, an I / O bus, etc. are omitted.

In this embodiment, the address data is inputted from the input terminal 4 and the 8-bit wide ROM block 2a,
The common address in 2b and 2c is selected, the storage data of the selected address is output every 8 bits, and is temporarily stored in the output buffer in some cases and then input to the adder circuit 6. The adder circuit 6 is a circuit for adding three types of 8-bit data to each other, and outputs the addition result in 10 bits including the carry 2 bits. For this reason,
The amount of data output to the output terminal 3 is about one-third of that in the conventional case shown in FIG. On the tester side, by comparing this added value with the expected value, the ROM blocks 2a, 2
b / 2c is judged as good or bad, but the amount of data is about 1/3
It's done.

The buffer 5 sets the addition result of the addition circuit 6 to 1
A buffer that latches in units of 0 bits,
Output to the read data output terminal 3 bit by bit. In this embodiment, the output data of each ROM block 2a, 2b, 2c is not output to the outside as it is, but is subjected to addition processing and output to the outside. Therefore, the parallel test of the ROM blocks 2a, 2b, and 2c can be performed with the number of terminals of 10 which is smaller than the conventional one. Moreover, since the input / output data transfer means such as the I / O buffer used in the normal mode is not used, it is possible to simultaneously test whether such a data transfer means is good or bad by using a normal terminal. is there.

As described above, in the present embodiment, since 8-bit data are added to each other, for example, a cell at a certain address in the ROM block 2a is erroneously stored as logic 1 when it should be logic 0, and the ROM block 2b is erroneously stored. When the cell of the common address is erroneously stored as logic 0 when it should be logic 1, it is considered that the addition result is judged to be good. However, the frequency of occurrence of such an accident is extremely low, and even if the mounting board itself is discarded as a defect in the comprehensive test after such a semiconductor integrated circuit is incorporated into the mounting board, the actual loss is slight as a whole. Is.
Also, the expected value data to be prepared is only one-third of the conventional one,
The comparative test takes only one-third the time, and the load on the tester side is light, which is extremely practical.

Referring to the block diagram of FIG. 2 showing the semiconductor integrated circuit of the second embodiment of the present invention, the semiconductor integrated circuit 8 includes first to third ROM blocks 24, 25 and 2.
6, a test address generation circuit 22 for generating an address signal for sequentially selecting a common address in the ROM blocks 24, 25, 26, and a memory cell selected and output in the ROM blocks 24, 25, 26. First to third buffers 27, 28, 29 for temporarily storing data for each 8 bits, and a second adder circuit 31 for adding 8-bit data of the first buffer 27 and the second buffer 28 to each other. And a fifth buffer 33 for temporarily storing the 10-bit addition value data of the addition circuit 31,
The ten output terminals 36 for outputting to the external tester as they are via the 10-bit data selector 34 of the buffer 33, the instruction control circuit 23 for generating a series of control signals at the time of testing, and the test address generation circuit 22. And a test mode generation circuit 21 which issues a series of test mode commands to the instruction control circuit 23, and at least one control terminal 35 for applying a test signal having a logical value 0 or 1 to the circuit 21 from the outside. Equipped with.

If only the data in the fourth buffer 32 is to be output to the outside, the selector 34 is selected. The selection signal is applied from the instruction control circuit 23.

Further, the instruction control circuit 23 stores the buffers 27, 28 and 29 corresponding to a common address in any of the first to third ROM blocks 24, 25 and 26 when there is no common address. It has a function of issuing a signal for resetting the element to a logic 0 level in 8-bit units or word units. Therefore, the ROM block 24,
25 and 26 can be added even if the storage capacities are different.

The operation of this embodiment will be described. First, the test mode is set from the control terminal 35, and the test address generation circuit 22 and the instruction control circuit 23 are respectively set to [+1].
It outputs the incremented address and outputs a series of read control signals. Storage data of every 8 bits is read from the first and second ROM blocks 24 and 25,
It is stored in the first and second buffers 27 and 28, respectively. These 8-bit data are added together in the first adder circuit 30, and the added value data is temporarily stored in the fourth buffer 32.
Is stored. Next, the storage data of the common address read from the third ROM block 26 is added to the data of the fourth buffer 32 by the second addition circuit 31 via the third buffer 29, and its 10-bit data is added. The added value data is output from each of the ten output terminals 36 through the selector 34. The output additional value data is compared with the expected value data prepared in the tester. If they match, the result is good, and if they do not match, the semiconductor integrated circuit 8 is discarded. However, when it is desired to specify the defective ROM block, the selector 34 is switched to output the data in the fourth buffer 32 to the outside and compare it with the expected value data in the tester. If the compared results match, it can be determined that only the third ROM block 8 is defective.

If the comparison results do not match, the stored data in the first ROM block 24 or the second ROM block 25 is output. In this case, the first adder circuit 3
The memory element in the buffer is reset to logic 0 by the instruction control circuit 23 so that only one data is input to 0 and the other data becomes logic 0. Next, the third ROM
Only block 26 is output and compared to the expected value. At this time, the fourth buffer 32 is reset to logic 0. The defective ROM block can be identified as described above.

For the above series of controls, the control terminal 35
It is preferable to prepare a plurality of, but when applying a series of control signals from an external tester, only one is required.

In this embodiment, the defective ROM block can be specified even if it is determined to be a defective product by the first determination, and even if it is determined to be a non-defective product, there is a possibility of the defect described in the first embodiment. In such a case, an advantage such as being able to individually test the ROM blocks is added.

Here, the test address is generated internally, but may be input from an external tester. For example, if the addition is performed in a state where the buffers 27, 28, 29 are all reset to logic 0, the adder circuits 30, 31, the buffers 32, 33, and the selector 34 can be the test targets. Further, if all the second and third buffers 28 and 29 are reset to logic 0 and added, only the storage data of the first ROM block 24 can be output to the outside. That is, there is also an advantage that a defective ROM block can be specified. Further, in addition to the adding circuits 30 and 31, it can be realized as a subtracting circuit. Also in this case, the other circuit blocks are configured in common, and the same effect as in the case of addition can be obtained.

In the first and second embodiments described above, RO
Although the case where the number of M blocks is 3 has been described, the case where the number of such ROM blocks is 2 or more than 4 is configured by constructing the addition (subtraction) circuit, that is, the calculation means, as described above, (Number of patterns x
The number of terminals is reduced, and the test can be performed very efficiently.

[0030]

As described above, according to the present invention, the ROM block test is realized by adding the read data of each ROM and externally monitoring the output, so that the number of terminals is smaller than the conventional one. Allows a parallel test of a plurality of ROM blocks to be performed, and also enables the test on a semiconductor integrated circuit having a small number of external terminals. Further, even in the case of a semiconductor integrated circuit having a sufficient number of external terminals for the parallel test of ROM blocks, Since the number of terminals occupied for the ROM test is small, there is an effect that the test of other functional blocks other than the ROM can be performed at the same time, and only the expected value data of the addition result of a plurality of ROM blocks can be prepared as a test pattern. This makes it possible to test other blocks at the same time, reducing the test pattern capacity, etc. Ri, each issue of the above-described (1) to (2) is entirely achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional ROM block test circuit.

FIG. 4 is a block diagram showing another example of a conventional ROM block test circuit.

[Explanation of symbols]

1,7,8 semiconductor integrated circuits 2a, 2b, 2c, 24, 25, 26 ROM blocks 3a, 3b, 3b, 36 read data output terminals 4 address input terminals 5a, 5b, 5c, 5, 27, 28, 29, 32, 33
Buffers 6, 30, 31 Adder circuit 21 Test mode generation circuit 22 Test address generation circuit 23 Instruction control circuit 35 Control terminal 50, 51 ROM 52, 53 ROM address generation circuit 54 ROM test signal generation circuit 55, 56 ROM data read buffer 57 ROM test read signal generation circuit 58 ROM test address generation circuit 59 Internal data bus

Claims (5)

[Claims] 1. In a semiconductor integrated circuit having a plurality of ROM blocks built in on a semiconductor substrate, calculation means for adding or subtracting stored data at a common address in the plurality of ROM blocks to or from each other by a predetermined number of bits. A semiconductor integrated circuit comprising: output means for outputting data calculated by the calculation means to the outside on the substrate. 2. The semiconductor integrated circuit according to claim 1, wherein said output means has a function of adding and outputting 2 bits for carry in addition to said predetermined number of bit units. 3. The semiconductor integrated circuit according to claim 1, wherein said output means has a switching means for selectively outputting calculated value data obtained by calculating only corresponding storage data in two ROM blocks of said plurality of ROM blocks. 4. When the calculating means has a ROM block having no common address among the plurality of ROM blocks, the data of a portion having no common address is logically 0.
2. The semiconductor integrated circuit according to claim 1, which has a function of performing calculation after setting to. 5. The test method for a semiconductor integrated circuit according to claim 1, wherein the pass / fail judgment is performed by comparing the calculated value data from the calculating means with the expected value data prepared in the tester. .