CN103678747A - United simulation tool suitable for multi-type CPU - Google Patents
United simulation tool suitable for multi-type CPU Download PDFInfo
- Publication number
- CN103678747A CN103678747A CN201210352252.1A CN201210352252A CN103678747A CN 103678747 A CN103678747 A CN 103678747A CN 201210352252 A CN201210352252 A CN 201210352252A CN 103678747 A CN103678747 A CN 103678747A
- Authority
- CN
- China
- Prior art keywords
- digital signal
- waveform
- file
- assembly instruction
- multichannel digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a united simulation tool suitable for a multi-type CPU. The united simulation tool comprises a ELF file interpreter for extracting debugging information and data areas in ELF files, an instruction set disassemble for converting the debugging information and instructions in the inside into kernel assembly instruction codes of corresponding kernel instruction sets, a waveform file interpreter for reading and analyzing VCD files, interpreting multi-channel digital signal waveform information in the VCD files to generate waveform output modes and loading the waveform output modes into an internal memory, a waveform oscilloscope for processing interpreted multi-channel digital signal waveform information stored in the internal memory, a debugger user interface for displaying the kernel assembly instruction codes and multi-channel digital signal waveforms through respective windows and achieving automatic mutual correspondence between the multi-channel digital signal waveforms and the kernel assembly instruction codes. The united simulation tool can effectively improve the verification work efficiency.
Description
Technical field
The present invention relates to a kind of polymorphic type CPU(central processing unit that is applicable to) associative simulation instrument.
Background technology
Along with the development of integrated circuit technology and deepening continuously of integrated circuit (IC) application, complexity and the performance complexity of IC design have had essential lifting than before, and the proof scheme of Zhe Dui chip design company and chip application manufacturer is had higher requirement.
For the design of the circuit with kernel, classic method is on large server or workstation, to carry out the emulation of hardware identification code, and simulation result is reflected on graphical interfaces with wave form.In this process, software or Hardware Engineer offer software code checking slip-stick artist as the input file of simulation hardware after compiling.This verification mode is located hiding defect (hereinafter to be referred as " BUG ") by manual observation waveform.But the level that BUG may occur is more, may be due to hardware circuit, also may be due to the reason of upper layer software (applications).Therefore after checking slip-stick artist pinpoints the problems, can combine software engineer and investigate together.Checking slip-stick artist points out the position that on waveform, abnormal conditions occur, conventionally by the signal of data and address bus one class, carries out the location of software instruction.Software engineer may occur that to software code wrong place carries out BUG location by the information that provides of checking slip-stick artist, confirms and revises, and gives checking slip-stick artist afterwards by result feedback.Conventionally for a BUG, will repeatedly repeat said process, and the work that corresponds to assembly code by waveform in said process is all by completing by hand, this increases a lot of unnecessary workloads to engineers.Due to the work in the mutual aspect of software and hardware, contain the knowledge of software and hardware two aspects, this has brought very large burden to the slip-stick artist who comes from different background simultaneously, has virtually improved the complexity of work.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of associative simulation instrument that is applicable to polymorphic type CPU, can effectively improve the work efficiency of checking.
For solving the problems of the technologies described above, the associative simulation instrument that is applicable to polymorphic type CPU of the present invention, comprising:
One ELF(can carry out link form, Executable and Linkable Format) file interpreter, for extracting ELF file debug file data, the Debugging message that this debug file data comprises and data field;
One instruction set disassembler, for loading debug file data, and is converted into the Debugging message of debugging file inside and instruction the kernel assembly instruction code of corresponding core instructions collection;
One wave file interpreter, load the file layout of VCD(based on ASCII character, Value ChangeDump) wave file, by reading and resolve VCD wave file, the multichannel digital signal shape information that emulation in VCD wave file is obtained makes an explanation, generate the form of output waveform, and load in internal memory;
One waveform oscilloscope, the multichannel digital signal shape information that the emulation being explained of storing in internal memory is obtained is processed;
One debugger user interface, is positioned on described waveform oscilloscope, is responsible for calling all background programs, loads and shows input file and dynamic debugging routine; The multichannel digital signal waveform that described kernel assembly instruction code and emulation are obtained shows in window separately, and realizes the mutually automatically corresponding of multichannel digital signal waveform that emulation obtains and kernel assembly instruction code.
In order to improve the work efficiency of whole proof procedure, can transfer to computing machine to process unnecessary manual operation.It is associated that the multichannel digital signal waveform that adopts the present invention kernel assembly instruction code can be obtained with simulation hardware carries out robotization, simplify software engineer and verify that slip-stick artist processes the work in software and hardware reciprocal process, make them more energy can be placed on to the field of being good at separately; And then the effective work efficiency that improves checking team.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Accompanying drawing is associative simulation tool operation schematic flow sheet.
Embodiment
By reference to the accompanying drawings, described in be applicable to polymorphic type CPU associative simulation instrument comprise: an ELF file interpreter, an instruction set disassembler, a wave file interpreter, a waveform oscilloscope, a debugger user interface.This associative simulation instrument has graphical interfaces (being debugger user interface) Presentation Function, waveform Presentation Function, and the waveform function associated with kernel assembly instruction code two-way automatic.Described associative simulation instrument is supported polytype CPU core, as C51, and ARM; Can select CPU core type by debugger user interface.Described associative simulation instrument, in many document views, is supported floating and embedding of each subwindow.
Software test code is the software code for circuit is done further to debug of being write by software test personnel.This software test code generates ELF file and the desired BIN(scale-of-two of emulation by the compiler compiling based on different kernels) file (being firmware testing file).
Digital circuit net table is the digital circuit net table with kernel circuitry, is the hardware identification code process compiling of being write by hardware description language by Digital Design personnel and the gate level netlist comprehensively obtaining.
At Linux server end, use emulator to load digital circuit net table and BIN file, digital circuit is carried out to simulation hardware, generation is with the wave file of VCD formatted output, it is VCD wave file, this VCD wave file is a kind of file layout based on ASCII character, for record by EDA(electric design automation) signal message that produces of emulation tool.The form of this wave file has * .vcd and two kinds of forms of * .fsdb, and wherein * .fsdb form can be converted into * .vcd form.
ELF file is written in described associative simulation instrument as the input file of software emulation, by described ELF file interpreter, the Debugging message in ELF file and data field (instruction area) is extracted.This Debugging message and data field are the debug file data shown in accompanying drawing.
Described instruction set disassembler loads debug file data, and the Debugging message of debugging file inside and instruction is converted into the kernel assembly instruction code of corresponding core instructions collection.
The wave file interpreter of described associative simulation instrument loads VCD wave file, by reading and resolve VCD wave file, the multichannel digital signal shape information that emulation in VCD wave file is obtained makes an explanation, and generates the form of output waveform, and loads in internal memory.
Described waveform oscilloscope, the multichannel digital signal shape information that the emulation being explained of storing in internal memory is obtained is processed, and shows by debugger user interface the multichannel digital signal waveform that emulation obtains.Described waveform oscilloscope can be user PC(PC).
Described debugger user interface, is responsible for calling all background programs (as instruction set disassembler), loads and shows input file and dynamic debugging routine; Make described kernel assembly instruction code, the multichannel digital signal waveform that emulation obtains is presented on user PC by window separately, and realizes multichannel digital signal waveform that emulation obtains and the mutual correspondence of kernel assembly instruction code.
Described debugger user interface transverse and longitudinal axle is respectively sampling time point and each digital signal channel that is recording waveform.This debugger user interface can realize and comprises the amplification of waveform and dwindle, and scale is searched upper and lower edge, the functions such as program trace.Described debugger user interface is supported increase and the minimizing of multichannel digital signal waveform signal quantity, and the change of signal colour, manually changes signal and put order, and a plurality of signals are summed up as bus, and bus is untied becomes a plurality of signals, the time between show rulers.
The multichannel digital signal waveform that described emulation obtains is associated with the two-way automatic of kernel assembly instruction code, can correspond to the multichannel digital signal waveform that emulation obtains from kernel assembly instruction code, the multichannel digital signal waveform that also can obtain from emulation corresponds to corresponding kernel assembly instruction code.Associated direction can be selected by user oneself.
It is associated (as adopted R15 register in ARM CPU that the multichannel digital signal waveform that emulation obtains and kernel assembly instruction code adopt the feature register that represents address information in CPU to carry out two-way automatic, following R15 represents this address information register), mean by a Position Scale on multichannel digital signal waveform and corresponding instruction on multichannel digital signal waveform can be navigated on the kernel assembly instruction code corresponding with it, simultaneously also can be by selecting kernel assembly instruction code, locate the position that this kernel assembly instruction code occurs on multichannel digital signal waveform.
If selected, from kernel assembly instruction code, correspond to multichannel digital signal waveform, can be by setting search in the edit box in program main frame interval and input need the R15 value of search, realize the corresponding of kernel assembly instruction code and multichannel digital signal waveform.Concrete mode is, in kernel assembly instruction CodeWindow, by selecting corresponding kernel assembly instruction code, to obtain its corresponding R15 value.The frontier point A and the B that set the time zone of searching on multichannel digital signal waveform search in time point B at time point A simultaneously.After clicking search, program is searched for this R15 value automatically on multichannel digital signal waveform, if searched for successfully, program will mark the waveform of all couplings in this multichannel digital signal wave regions, and window view is positioned to first Search Results place, at shape information window, demonstrate Search Results simultaneously, be the time point of region of search and each coupling waveform, by clicking Search Results, can directly window view be jumped to coupling waveform.If searched for unsuccessfully, in shape information window, demonstrate Search Results, i.e. region of search and do not find coupling waveform.
If select to correspond to kernel assembly instruction code from multichannel digital signal waveform, can be in waveform window by locking R15 signalling channel with Position Scale position is set, realize the corresponding of multichannel digital signal waveform and corresponding kernel assembly instruction code.Concrete mode is, first R15 signalling channel is locked, by a Position Scale in slip waveform window, the waveform on this passage is selected afterwards, software can be according to the value of the selected waveform of scale at kernel assembly instruction CodeWindow by corresponding kernel assembly instruction marking code out.
By embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. an associative simulation instrument that is applicable to polymorphic type CPU, is characterized in that, comprising:
One can carry out link form ELF file interpreter, and for extracting the debug file data that can carry out link form ELF file, this debug file data comprises Debugging message and data field;
One instruction set disassembler, for loading debug file data, and is converted into the Debugging message of debugging file inside and instruction the kernel assembly instruction code of corresponding core instructions collection;
One wave file interpreter, the file layout VCD wave file of loading based on ASCII character, by reading and resolve the file layout VCD wave file based on ASCII character, the multichannel digital signal shape information that emulation in file layout VCD wave file based on ASCII character is obtained makes an explanation, generate the form of output waveform, and load in internal memory;
One waveform oscilloscope, the multichannel digital signal shape information that the emulation being explained of storing in internal memory is obtained is processed;
One debugger user interface, is positioned on described waveform oscilloscope, is responsible for calling all background programs, loads and shows input file and dynamic debugging routine; The multichannel digital signal waveform that emulation by described kernel assembly instruction code and after processing obtains shows in window separately, and realizes the mutually automatically corresponding of multichannel digital signal waveform that emulation obtains and kernel assembly instruction code.
2. associative simulation instrument as claimed in claim 1, is characterized in that: support polytype CPU core, and select CPU core type by described debugger user interface.
3. associative simulation instrument as claimed in claim 1, is characterized in that: described debugger user interface transverse and longitudinal axle is respectively sampling time point and each digital signal channel that is recording waveform; This debugger user interface can realize the amplification of waveform and dwindle, and scale is searched upper and lower edge, program trace; Described debugger user interface is supported increase and the minimizing of multichannel digital signal waveform signal quantity, and the change of signal colour, manually changes signal and put order, and a plurality of signals are summed up as bus, and bus is untied becomes a plurality of signals, the time between show rulers.
4. associative simulation instrument as claimed in claim 1, is characterized in that: in many document views, support floating and embedding of each subwindow.
5. associative simulation instrument as claimed in claim 1, is characterized in that: described waveform oscilloscope is client personal computer PC.
6. associative simulation instrument as claimed in claim 1, is characterized in that: it is associated that the multichannel digital signal waveform that described emulation obtains and kernel assembly instruction code adopt the feature register that represents address information in CPU to carry out two-way automatic.
7. as the associative simulation instrument as described in arbitrary in claim 1 to 6, it is characterized in that: the multichannel digital signal waveform that described emulation obtains and associated the referring to of kernel assembly instruction code two-way automatic, by a Position Scale on multichannel digital signal waveform, corresponding instruction on multichannel digital signal waveform can be navigated on the kernel assembly instruction code corresponding with it, also can, by selecting kernel assembly instruction code, locate the position that this kernel assembly instruction code occurs on multichannel digital signal waveform simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210352252.1A CN103678747B (en) | 2012-09-19 | 2012-09-19 | Suitable for polymorphic type CPU associative simulation instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210352252.1A CN103678747B (en) | 2012-09-19 | 2012-09-19 | Suitable for polymorphic type CPU associative simulation instrument |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103678747A true CN103678747A (en) | 2014-03-26 |
| CN103678747B CN103678747B (en) | 2017-10-31 |
Family
ID=50316290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210352252.1A Active CN103678747B (en) | 2012-09-19 | 2012-09-19 | Suitable for polymorphic type CPU associative simulation instrument |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103678747B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104035360A (en) * | 2014-05-07 | 2014-09-10 | 株洲易力达机电有限公司 | Parameter adjusting method for EPS controller and device |
| CN105446859A (en) * | 2014-09-01 | 2016-03-30 | 上海华虹集成电路有限责任公司 | Automatic generation method of software condition monitoring and wave file for power consumption analysis |
| CN111627489A (en) * | 2020-04-20 | 2020-09-04 | 珠海妙存科技有限公司 | Flash memory characteristic analysis method and system |
| CN112257359A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN112257360A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN113868189A (en) * | 2021-12-02 | 2021-12-31 | 成都奥卡思微电科技有限公司 | Waveform file processing method, storage medium and device |
| CN114138346A (en) * | 2021-11-02 | 2022-03-04 | 北京安天网络安全技术有限公司 | Terminal evidence obtaining method and device, electronic equipment and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622312A (en) * | 2003-11-27 | 2005-06-01 | 北京北阳电子技术有限公司 | Method for verifying consistency of chip hardware behavior and software simulation behavior |
-
2012
- 2012-09-19 CN CN201210352252.1A patent/CN103678747B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622312A (en) * | 2003-11-27 | 2005-06-01 | 北京北阳电子技术有限公司 | Method for verifying consistency of chip hardware behavior and software simulation behavior |
Non-Patent Citations (2)
| Title |
|---|
| ANDREAS HOFFMANN ET AL.: "A Framework for Fast Hardware-Software Co-simulation", 《DESIGN,AUTOMATION AND TEST IN EUROPE》 * |
| 王江等: "基于MIPS内核的SoC软硬件协同仿真", 《计算机工程》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104035360A (en) * | 2014-05-07 | 2014-09-10 | 株洲易力达机电有限公司 | Parameter adjusting method for EPS controller and device |
| CN104035360B (en) * | 2014-05-07 | 2018-03-13 | 株洲易力达机电有限公司 | A kind of parameter adjustment method and device of EPS controllers |
| CN105446859A (en) * | 2014-09-01 | 2016-03-30 | 上海华虹集成电路有限责任公司 | Automatic generation method of software condition monitoring and wave file for power consumption analysis |
| CN105446859B (en) * | 2014-09-01 | 2018-06-19 | 上海华虹集成电路有限责任公司 | The software condition monitoring of power consumption analysis and wave file automatic generation method |
| CN111627489A (en) * | 2020-04-20 | 2020-09-04 | 珠海妙存科技有限公司 | Flash memory characteristic analysis method and system |
| CN111627489B (en) * | 2020-04-20 | 2023-09-29 | 珠海妙存科技有限公司 | Flash memory characteristic analysis method and system |
| CN112257360A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN112257359A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN112257360B (en) * | 2020-10-21 | 2024-04-16 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN112257359B (en) * | 2020-10-21 | 2024-04-16 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN114138346A (en) * | 2021-11-02 | 2022-03-04 | 北京安天网络安全技术有限公司 | Terminal evidence obtaining method and device, electronic equipment and storage medium |
| CN113868189A (en) * | 2021-12-02 | 2021-12-31 | 成都奥卡思微电科技有限公司 | Waveform file processing method, storage medium and device |
| CN113868189B (en) * | 2021-12-02 | 2022-02-11 | 成都奥卡思微电科技有限公司 | Waveform file processing method, storage medium and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103678747B (en) | 2017-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103678747A (en) | United simulation tool suitable for multi-type CPU | |
| CN109739766B (en) | System and method for rapidly building FPGA digital simulation model | |
| US9064068B1 (en) | Debuggable opaque IP | |
| JP2002530659A (en) | IC test software system for mapping logic functional test data of a logic integrated circuit to a physical representation | |
| CN107665168A (en) | A kind of embedded software GUI automated test devices | |
| US10255400B1 (en) | Debugging system and method | |
| US10997332B1 (en) | System and method for computing electrical over-stress of devices associated with an electronic design | |
| CN106354630A (en) | Software defect detecting method based on dynamic symbolic execution | |
| US8732632B1 (en) | Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test | |
| CN103425584A (en) | Large-scale application regression testing information processing method based on Java bytecode | |
| US8132161B2 (en) | Semiconductor test program debug device | |
| CN1987820A (en) | Method and system for tracing program execution in field programmable gate arrays | |
| CN104268310A (en) | Method for calling UVM verification environment through special graphical interface | |
| US8230382B2 (en) | Model based simulation of electronic discharge and optimization methodology for design checking | |
| US20200074040A1 (en) | Hierarchical expression coverage clustering for design verification | |
| US8214701B1 (en) | Hardware and software debugging | |
| CN116126700A (en) | Chip verification method and system based on SystemC | |
| CN104850692B (en) | A kind of intelligent wiring design method for chip design | |
| US6842883B2 (en) | Application of co-verification tools to the testing of IC designs | |
| CN112346918A (en) | Method and application for assisting waveform debug in chip verification | |
| CN104536880A (en) | GUI program testing case augmentation method based on symbolic execution | |
| US11354477B1 (en) | System and method for performance estimation for electronic designs using subcircuit matching and data-reuse | |
| JP4183182B2 (en) | Design support apparatus and design support method | |
| US7065724B2 (en) | Method and apparatus for generating and verifying libraries for ATPG tool | |
| US6760904B1 (en) | Apparatus and methods for translating test vectors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |