CN101055523A - Method for exchanging software program code to hardware described language program code - Google Patents
Method for exchanging software program code to hardware described language program code Download PDFInfo
- Publication number
- CN101055523A CN101055523A CNA2007101010439A CN200710101043A CN101055523A CN 101055523 A CN101055523 A CN 101055523A CN A2007101010439 A CNA2007101010439 A CN A2007101010439A CN 200710101043 A CN200710101043 A CN 200710101043A CN 101055523 A CN101055523 A CN 101055523A
- Authority
- CN
- China
- Prior art keywords
- hardware
- source file
- program
- software
- software program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Stored Programmes (AREA)
Abstract
Systems and methods are disclosed for transferring assertions in a software programming language source file to an HDL source file. In one such method, a first source file contains source code in a software programming language and a second source file contains HDL source code translated from the source code in the first source file. The second source file excludes assertions translated from the source code in the first source file. This method comprises the steps of: reading a software assertion from the first source file; locating a second block within the second source file, where the second block corresponds to a first block that contains the software assertion; mapping the software assertion to a hardware assertion expressed in the HDL; determining a location within the second block for insertion of the hardware assertion; and inserting the hardware assertion at the determined location within the second source file.
Description
Technical field
The present invention is used for designing digitizing integrated circuit (integrated circuits relevant for a kind of, IC) Software tool, particularly (hardware description language HDL) asserts the instrument of (assertion) relevant for a kind of use hardware description language.
Background technology
Integrated circuit (IC) design comprises several stages traditionally, each stage all needs to use different instruments or set of tools, general integrated circuit (IC) design person can use one of several program languages to write program code, when writing the program code flow process, can simulate, the deviser can carry out simulation tool loading routine coding with the Test Design result, when simulation process goes wrong, the tester also simulates with the reparation problem once again to the program code editor, the deviser can use compositor program coding to be translated to the logical expressions of integrated circuit after simulation, then use other integrated circuit instruments that logical expressions are changed into the entity integrated circuit, become programmable gate array (Field Programmalbe Gate Array, FPGA), special IC (Application-Specific Integrated Circuit, ASIC), or other customized silicon integrated circuits.
Integrated circuit (IC) design person can use the program language of several classifications to design; wherein there is a kind of language set to be called as hardware description language (Hardware Description languages; HDL); also be called as register transfer language (Register Transfer Languages; RTL); register transfer language known to general comprises Verilog and VHDL; register transfer language is considered to the low order program language; because its description is special hardware feature such as the sequential or the depth of parallelism; other can comprise C for the program language that integrated circuit (IC) design is used; C++; or other similar language; this speech like sound relatively is commonly used to develop software but not hardware traditionally; these software languages can allow the deviser write program code with the notion of higher-order, therefore can increase deviser's work efficiency usually.
General C/C++ and hardware description language program code all comprise asserts, can accurately carry out the design of expection in order to confirm program coding, one section is asserted as and is used for representing the declaration how a specific design feature should or should not turn round, for instance, the program code of a particular block may suppose that it is effective once having only a collection of in two batches of outputs, again for instance, a block may suppose that the value of each batch input can be greater than a specific maximal value, and these hypothesis can be expressed as by the deviser and assert and realize.
Because most simulation and synthetics all use hardware description language input, rather than C/C++, the deviser who uses C/C++ to write program code will translate to hardware description language with program code, the process of translating may be manually to translate, translate automatically or the combination of dual mode, yet, be not that all instruments of translating can both be asserted C++ that translating to suitable hardware description language asserts, therefore, need badly and propose a kind ofly to translate the instrument that software program code is a hardware description language, to overcome the shortcoming of conventional art.
Summary of the invention
Because many shortcomings of above-mentioned conventional art, the objective of the invention is to propose a kind of System and method for that is asserted as hardware description language that can translate software program code, in a method of the present invention, one first source file comprises the source program code of being write as with the software program language, can be translated to the second source file that comprises the hardware description language source program code.The second source file can be carried out by what the first source file routine code was translated and assert that this method comprises: come source file reading software program code to assert by first; One second block in the second source file of location, wherein second block corresponds to first first block that software program code is asserted that has that comes in the source file; Translating software program code is asserted as the hardware program of representing with hardware description language and asserts; Determine a position in second block to assert to insert hardware program; And hardware program asserted insert the position that is determined in the second source file.
For those of ordinary skills, other system, method, feature or benefits that are not included in following disclosed content of the present invention and the accompanying drawing are conspicuous, therefore all other do not break away from the equivalence of being finished under the spirit that invention discloses and change or revise, and all should be included in the described claim scope.
Description of drawings
Fig. 1 shows the overall data stream block synoptic diagram that uses method switching software program code of the present invention to be asserted as the hardware description language program code.
Fig. 2 A software for display program code and hardware program code hierarchical structure and the block level synoptic diagram of corresponding relation between the two.
Fig. 2 B software for display program code and hardware program code file be the synoptic diagram of the hierarchical structure among the presentation graphs 2A how.
The synoptic diagram of another kind of hierarchical structure in Fig. 3 software for display program code and the hardware program code.
Fig. 4 shows a software program code function and corresponding hardware code modules synoptic diagram.
Fig. 5 shows the synoptic diagram that uses the hardware program code module of asserting in the method disclosed in the present conversion software program code function as shown in Figure 4.
Fig. 6 shows how asserting in the synoptic diagram of hardware description language form of corresponding C/C++ form of the method disclosed in the present.
Fig. 7 shows that convertible software program in one embodiment of the invention is asserted as the block synoptic diagram of the system of hardware description language program code.
Fig. 8 shows that convertible software program in one embodiment of the invention is asserted as the process flow diagram of hardware description language program code means.
Fig. 9 shows the hardware block synoptic diagram in order to the multi-purpose computer that to implement switching software program assertion of the present invention be the hardware description language program code means.
The main element symbol description
110 software program codes
120 translate instrument
130 hardware program codes
140 assert crossover tool
150 comprise the hardware program code that hardware is asserted
160 hardware description language simulators
210S function m ain
210H module top
220S classification S_MUX
220H module H_MUX
230S classification S_CTR
230H module H_CTR
240S classification S_ENC
240H module H_ENC
310 function blocks
320 module blocks
330 sequence blocks
340 flow process blocks
350S software control block
350H hardware controls block
The 410S software function
The 410H hardware module
The 420S first control block
The 420H first control block
The 430S second control block
The 430H second control block
440 flow process blocks
450 assert
510 hardware are asserted
610 C/C++ (software) assert
620 Boolean algebras
630 output word strings
640 orders of severity
650 Verilog language (hardware) are asserted
660 attribute definitions
670 ASSERT declaration
680 Boolean algebras
690 $FATAL (order of severity) declaration
695 output word strings
710 read logic
720 first location logics
725 software indication codes
727 software blocks
730 second location logics
735 hardware indication codes
737 hardware blocks
740 translation logic
750 the 3rd location logics
760 insert logic
800 convertible softwares are asserted as the hardware description language program code means
810 come to read the source file to comprise function or the classification that software is asserted from software
820 decision softwares are asserted and the relative position of forming the various blocks of function or classification
830 read the hardware module with respect to function or classification
840 switching softwares assert that hardware asserts
850 judge that hardware assert insertion position in the hardware program code file
860 insert hardware in the insertion position asserts
900 computer systems
910 processors
920 network interfaces
930 storeies
940 Nonvolatile memory devices
950 buses
Embodiment
Some embodiments of the present invention can be described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment, and scope of the present invention do not limited, and it is as the criterion with the claim scope that is proposed.Moreover in this manual, the different piece of each element is not drawn according to size.Some yardstick is compared with other scale dependents and is exaggerated, so that clearer description and understanding of the present invention to be provided.
The present invention discloses a kind of software program code is asserted and comprises the method that is converted to the hardware description language program code: the hardware description language program code that software program code comes with translating via software program code is inspected; Translating software program code in the software program code of being inspected is asserted as the hardware description language program code and asserts; And the hardware description language program code asserted insert in the hardware program code.
Fig. 1 shows the overall data stream block synoptic diagram that uses method switching software program code of the present invention to be asserted as the hardware description language program code, method of the present invention is used two groups of input files, two groups of input files are configured in the different sub-directories usually, wherein one group of input file comprises software program code 110, the program code of software program code 110 for using software program language such as C or C++ to be write as, these input files also comprise with asserting that the same software program language is write as, software program code 110 can be transfused to the instrument of translating 120 software program code is translated to hardware description language such as VHDL or Verilog, translate instrument 120 thus and translate generation hardware program code 130, hardware program code 130 is another group input file, is used for input assertion crossover tool 140.
In above-mentioned importantly, do not comprised by the software program language by the hardware program code 130 of being translated and to be translated into asserting of hardware description language, yet it still comprises corresponding other asserts, these assert by the instrument of translating 120 produce or after the process of translating by artificial adding.
Two groups of input files all can be handled by input assertion crossover tool 140, wherein can carry out method of the present invention and be asserted as the hardware description language program code with the switching software program code by computer program, assert thus crossover tool 140 produce comprise original hardware description language program code with translate to by the software program language hardware program code assert contain the hardware program code 150 that hardware is asserted, software program language in the method reading software program code 110 of the present invention is asserted, and it is translated to hardware description language assert, at last hardware description language is asserted the appropriate location of putting into the hardware program code 130 of being translated, contain the hardware program code 150 that hardware is asserted so produce, to contain hardware program code 150 that hardware asserts afterwards and can be transfused to hardware description language simulator 160 and carry out simplation verification.
Can understand as the those of ordinary skill of field of software development, of the present inventionly assert that crossover tool 140 can be encoded and be compiled by multiple program language and carry out to realize, therefore the present invention does not limit its employed program language, spendable program language comprises perl, awk, shell script, VBscript or other program languages during coding, compiles spendable program language and comprises C, C++, C#, JAVA, Visual Basic or other program languages.
Though software program code 110 is comprised in a plurality of files, yet its integral body can be considered the hierarchical structure that forms single software entity, identical hardware program code 130 also is comprised in a plurality of files, but equally can be considered as the hierarchical structure of single hardware entities, these entities are called as module (module) in the Verilog language, then being called function (function) in the C language, then is to be called as classification (class) in C Plus Plus, and wherein classification comprises function again.
Fig. 2 A and Fig. 2 B show two kinds of hierarchical structures and its corresponding relation, the synoptic diagram that plots with different viewpoints, Fig. 2 A is the block level synoptic diagram of hierarchical structure, in hierarchical structure topmost is single top entity 210, entity 210S in top is the function that is called as main in the hierarchical structure of C/C++ language, top entity 210H in Verilog language hierarchical structure is the module that is called as top, so hardware program code 130 has the hardware program language top entity 210H corresponding to the top entity 210S of software program language hierarchical structure.
Can set up or propose to be positioned at the entity of other lower-order layers at an entity of a specific stratum, example shown in Fig. 2 A, classification 220S " S_MUX " and 230S " S_CTR " are the middle-class software entity, proposed by top entity 210S " main ", same module 220H " H_MUX " and 230H " H_CTR " be the middle-class hardware entities, proposed by top entity 210H " top ", more the bottom software entity class 240S " S_ENC " of lower floor is the same is proposed by middle-class entity class 220S " S_MUX ", and bottom hardware entity module 240H " H_ENC " is then proposed by middle-class entity module 220H " H_MUX ".
The title of hardware program module 220H importantly in above-mentioned " H_MUX " can derive from the title of software classification 220S " S_MUX ", owing to C/C++ software program code 110 is translated to the flow process of translating of Verilog hardware program code 130, no matter all can follow the naming method that pre-defines for translating or manually translate automatically, when software program being asserted when translating to the hardware description language program code, the method disclosed in the present can be inspected the input file of formation software program code 110 to find out software program code hierarchical structure wherein, and inspect constitute hardware program code 130 input file to find out hardware program code hierarchical structure, use the naming method that pre-defines to help to allow method of the present invention find between the two corresponding relation.
Fig. 2 B software for display program code 110 and hardware program code 130 files are the synoptic diagram of the hierarchical structure among the presentation graphs 2A how, function 210S " main " proposes classification 220S " S_MUX ", and classification 220S " S_MUX " proposes classification 240S " S_ENC ", in the corresponding hardware hierarchical structure, module 210H " top " proposes module 220H " H_MUX ", and module 220H " H_MUX " proposes module 240H " H_ENC ".
In the embodiment shown in Fig. 2 B, each classification and independent function (as " main ") all be arranged in the file that separates, each same module is also all in the file that separates, therefore the file name of particular module can be by the file name of derivation from corresponding classification or function, derive from h_mux.cpp as h_mux.v, if therefore a specific file with specific software classification is arranged, software program code is asserted that the method that is translated into the hardware description language program code can find easily to hardware program module and hardware file that should the specific software classification, in another embodiment of the present invention, a file can comprise a plurality of classifications or module, in this case, software program code is asserted that the method that is translated into the hardware description language program code can derive hardware program module title from the software item name, search again and comprise the source file that comes that has hardware program module title in the file of hardware program code 130.
The synoptic diagram of another kind of hierarchical structure in Fig. 3 software for display program code 110 and the hardware program code 130: wherein software entity and hardware entities all are made up of block, wherein software entity and hardware entities all comprise a single top layer block in the place of top layer, and each function in the software classification all comprises a single top layer function block 310, in each same hardware program module a top-level module block 320 is arranged all.
Each function block 310 all comprises 330, one hardware program modules of one or more sequence blocks with module block 320 and also can comprise flow process block 340, and flow process block 340 is different from other blocks and does not have similar software classification.
Declaration in the sequence block 330 is carried out in regular turn, 350 of blocks of control are used to control sequence, though the syntax of distinct program language are different, but most of softwares or hardware program language all comprise condition control block (judging as IF) and repeat control block (as FOR, WHILE statement), in Fig. 3, block 350S is a C/C++ software program language condition block (IF), and corresponding block 350H is a Verilog hardware program language condition block (IF-THEN-ELSE).
As mentioned above, software program code is asserted that the method that is translated into the hardware description language program code can be translated asserts and puts into the suitable position of hardware program code 130, this method can use the block in the annexation of Fig. 3 to judge to insert insertion position suitable in appropriate location, especially the hardware program code 130 that hardware description language asserts by specific for meet with software program code 110 in the relevant rule of block.
For instance, if have a software program code to assert to be picked out between the block X and block Y in software program code 110, then hardware description language is asserted between may be in the hardware program code 130 corresponding block X ' and block Y ' in position, translate the those of ordinary skill of hardware description language technical field and should be able to find out to translate the hardware description language program code meeting that obtains and translated that very big-difference is arranged in the software program code, therefore in this example, the appropriate location that hardware description language is asserted also might be at block X ' and block Y ' afterwards, or among block X ' and block Y ', insert the appropriate location of asserting and decide on the software program code 110 and the structure of hardware program code 130.
Fig. 4 shows the software program function 410S in the example software program code 110, and the synoptic diagram of the hardware program module 410H in the corresponding hardware program code 130.Software program function 410S comprise two control blocks " IF read " 420S and " IF write " 430S, and in corresponding hardware program module 410H, comprise corresponding control block 420H and 430H, these two control blocks are arranged in flow process block 440, and this flow process block 440 does not have corresponding part at software program function 410S.
Software program function 410S comprise assert 450 " ASSERT (! (read ﹠amp; M_empty)) ", assert that 450 are positioned at before the first control block 420S, as shown in Figure 4, hardware program code 130 does not comprise by software program asserts that 450 translate the hardware program code that forms and assert.
Fig. 5 shows that having among as shown in Figure 4 the hardware program code module 410H assert that 450 translate and the hardware program that comes is asserted 510 synoptic diagram among the software program function 410S, translation method asserts that with hardware program 510 are inserted among the module 410H before the first control block 420H, assert that with corresponding software program 450 are arranged in before the function 410S first control block 420S, as described above, hardware program asserts that 510 may be inserted among the control block 420H in other cases, or after control block 420H, decide on the software program code 110 and the structure of hardware program code 130 its appropriate location.
Example shown in Figure 5 is comparatively simple, wherein have only two sequence blocks, and assert and be arranged in the first sequence block, more complicated example can comprise the sequence and control block in conjunction with multilayer, yet as previously mentioned, Software tool can correspond to the software program code block hardware description language block, and the those of ordinary skill of therefore translating software program code and be the hardware description language field should be able to be known the appropriate location that insertion hardware program how to judge in the hardware description language program code is asserted.
Fig. 5 shows when software program being asserted when translating to hardware description language, hardware program is asserted and is placed on position in the hardware program module, Fig. 6 shows how corresponding C/C++ asserts that form arrives the hardware description language form to the method disclosed in the present, explain as described above, assert for one and be used for representing an effective situation of expection meeting, a typical software program asserts that 610 can carry out in the mode of the huge collection instruction of the pretreater that three parameters are arranged, three parameters are: expection keeps the Boolean algebra 620 of true value, output word string 630, when the non-true value of Boolean algebra, then show output word string 630, and the order of severity 640, judge whether to interrupt the executive routine code by the order of severity during the non-true value of if symbol.
In the example of Fig. 6, software program asserts that 610 expection first in first out reading variable and empty flag parameter can all not be true value, if two parameters all are true value, then Boolean algebra 620 can not be calculated as true value when carrying out, at this moment word string 630 is described " S_FIFO::Access underflow " will show, because the order of severity 640 is CRITICAL, so program code can be ended to carry out, termination may be decided on the content of the huge collection instruction of ASSERT for entering debug mode or leaving program.
The translation method of asserting disclosed in this invention can be asserted software program that 610 translate to the Verilog language and assert 650, the Verilog language version that uses in the example of Fig. 6 is System Verilog withAssertions (SVA), SVA comprises the language conception of asserting, wherein a kind of attribute (property) that is contemplated that, software program code and hardware program code have a bit, and very important difference can be timed for the hardware program code, software can simple test variable value decide whether Boolean algebra is true value when carrying out, but the parameter at hardware is a signal, need be with reference to clock pulse during test.
Therefore, translation method disclosed in this invention is asserted Verilog and partly realized with two: attribute definition 660 makes that assert can be with reference to clock pulse; And ASSERT declaration 670.Attribute definition 660 has defined the attribute of Verilog language name, and attribute has generic name in this example " fifol ", attribute definition 660 comprises an ALWAYS block, and this block comprises device when certain, and in the block Boolean algebra 680 is contemplated to true value.
The use of $FATAL declaration can be considered as the CRITICAL that corresponding software program is asserted the order of severity in 610, order of severity NORMAL during software program is asserted then can correspond to Verilog or the declaration that hardware program is asserted, these declarations equally can show the output word string but can break simulation.
The software program of another kind of form asserts and then uses SWITCH or CASE control declaration and do not comprise Boolean algebra, get and generation to assert that the position in the control declaration uses as Boolean algebra, classify the program code example that this software program is asserted down as:
switch(access_type)
case?Read：
；more?code
case?Write：
；more?code
default：
ASSERT(0，“invalid?value?for?access_type”，NORMAL)；
In this section program code, only asserting after default can and be not equal to Read or just carry out during Write at access_type, therefore just equals the Boolean condition formula:
((access_type！＝Read)&&access_type！＝Write))
Because the Boolean condition formula is implied in the position of asserting in SWITCH/CASE control block, so do not need to comprise Boolean algebra with parameter as the huge collection instruction of ASSERT, the software program of this particular form asserts that can effectively correspond to the declaration of SystemVerilog attribute supports De $INSET operator, below asserts for the SystemVerilog of corresponding above-listed program code:
property?invalid_access_type；
@(posedge?clk)not($inset(access_type，`Read，`Write))
endproperty
assert?property(invalid_access_type)
else?$error(″H_FIFO：invalid?access?type！”)
Fig. 7 shows the block synoptic diagram of the system that is the hardware description language program code as the described switching software program assertion of Fig. 1 to Fig. 6 in one embodiment of the invention, read logic 710 and come source file 110 reading software program assertions 450 from software, judge that simultaneously software program asserts 450 are arranged in which software module 410S that software comes source file 110, the first location logic 720 can judge that software programs assert that 450 control the position of block with related one or more, control block 420S and 430S as Fig. 4, in one embodiment of this invention, position at the software block is obtained by the viewpoint of the first location logic 720 with block internal program code, because program code has been pointed out the position of software block, therefore the block of visual this position comprise a software indication code 725, the first location logics 720 can keep or set comprise software program assert 450 with the software block 727 of software indication code 725.
The second location logic 730 is searched hardware and is come source file 150 to find out the hardware block 420H corresponding to software block 420S, in one embodiment of this invention, the position of hardware block is for to find out with the viewpoint of the hardware program code in this block, just comprise hardware indication code 735, therefore the hardware block 737 that comprises hardware indication code 735 can be kept or be set to hardware indication code 735 corresponding to software indication code 725, the second location logics 730.
Fig. 8 shows in one embodiment of the invention that the conversion software program is asserted as the process flow diagram of hardware description language program code means 800, wherein step 810 is for to read the source file to comprise function or the classification that software program is asserted from software, next step 820, the decision software program is asserted and the relative position of forming the various blocks of function or classification, step 830 is for reading the hardware program module with respect to function or classification, step 840 switching software program assertion asserts that to hardware program step 850 and 860 is for judging the insertion position that hardware program is asserted and inserting hardware program in this position and assert afterwards.
Hardware program asserts that the insertion position may be in the hardware program module or module-external, wherein inside modules asserts to be called in the row and asserts (inline assertions), in this case, the position of inserting can be relevant with the block in the module, and assert that based on software program the position in software module or function judges, yet since software program functional form and hardware program modular form can be when conversion generation difference, program is translated the field those of ordinary skill and should be able to be understood method of the present invention and can allow this situation and find out the insertion position.
Block in above-mentioned in any process step or the process flow diagram will be understood that and is module, paragraph or sub-program coded representation to comprise one or more executable instructions, use logical function or the step carried out in the flow process, should be able to understand as the field of software development those of ordinary skill, the implementation that in scope disclosed in this invention, can have other to substitute, in these implementations, function may not be to carry out by above-mentioned disclosed order, and it may be looked function performance and adopt synchronous execution or reverse order to carry out.
Fig. 9 shows the hardware block synoptic diagram in order to the multi-purpose computer 900 of the method 700 that to implement switching software program assertion of the present invention be the hardware description language program code, computer system 900 comprises many elements that are widely known by the people, as processor 910, network interface 920, storer 930, and Nonvolatile memory devices 940, wherein Nonvolatile memory devices 940 can be a hard disk, quickflashing random access memory (flashRAM), flash ROM (flash ROM), the erase memory storage of formula ROM (read-only memory) (EEPROM) or other similar functions of electronics, these elements couple together by bus 950, in storer 930, comprise instruction set, the method that instruction set is performed by processor 910 and to implement switching software program assertion of the present invention be the hardware description language program code, omitted many traditional factors in Fig. 9, these factors are therefore not need known to the those of ordinary skill to explain too many to the operation of computer system 900.
The method and system that switching software program assertion of the present invention is the hardware description language program code can be implemented with software mode, hardware mode, or both combinations, in part embodiment of the present invention, system or method are implemented by the software that leaves in the storer, this software is performed by the microprocessor in the calculation element that is fit to, yet, method and system of the present invention also can implant any use for instruction execution system or device or with the computer fetch medium that is connected, such instruction execution system comprises any calculation element, the system that comprises processor, but or the system of the instruction set of other accesses or execution command executive system, in above-mentioned disclosed content, computer fetch medium can be any containing, deposit, communication, propagate or conveying program for the execution command executive system used or with the device that is connected, for instance, computer fetch medium can be based on electronics, magnetic, optics, electromagnetism, infrared ray, or the system of semiconductor technology or communications media, and be not limited thereto.
Use the computer fetch medium of electronic technology to comprise: to have one or the electrical connection of many circuits or electronic installation, random-access memory (ram), ROM (read-only memory) (ROM), the formula of erasing programmable read only memory (EPROM or flash memory), use the computer fetch medium of magnetic technique to comprise portable computing machine magnetic sheet, use the computer fetch medium of optical technology to comprise: optical fiber or portable optical disc (CD of CD-ROM or extended formatting), the above usedly the invention is not restricted to this for demonstrating.Computer fetch medium even may comprise paper or other can print off the medium of computer program, when using this medium, program can be used the processing mode that electronic technology obtains, understands, compiles or other are suitable on medium, as optical scanning, be to deposit in the computer memory afterwards with one-tenth, in the scope of the embodiment of the invention, the present invention also comprises logic element or software set medium in the function implantation hardware of embodiment in addition.
In sum, though the present invention with preferred embodiment openly as above, so it is not in order to limit the present invention.Those of ordinary skill under any in the technical field under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification.Therefore, protection scope of the present invention is as the criterion with the scope of the claim that proposed.
Claims (17)
1. conversion one a software program language comes the hardware description language of asserting in the source file to come the conversion method in the source file, comprises:
Read a software program and assert from the one first software program language program code that comes in the source file, wherein this software program is asserted and is arranged in one first block;
Locate the position of one second block, wherein this second block is to should first block, and be positioned at one and comprise the second source file that hardware description language comes source program code, program code in this second source file first comes source file for translating this, wherein do not comprise by this software program assert translate and a hardware program assert;
Changing this software program is asserted as a hardware program of being write as with hardware description language and asserts;
Judge that the insertion position in this second block asserts to insert this hardware program; And
Inserting this hardware program in this insertion position asserts.
2. conversion method as claimed in claim 1, the first wherein above-mentioned source file comprises a minimum top software entity, and this second source file comprises a minimum top hardware entities, and wherein each entity comprises a minimum block, and this conversion method also comprises:
Which this top software entity judges that this software program is asserted is arranged in;
Judge that this software program asserts and a relative position that comprises other blocks in this top software entity that this software program asserts;
Judge which this top hardware entities is corresponding to comprising this top software entity that this software program is asserted; And
Judge in this top hardware entities of correspondence in order to insert this insertion position that this hardware program is asserted based on this relative position.
3. conversion method as claimed in claim 1 also comprises:
Locate the position that this software program in this first block is asserted, this first block is arranged in this first this top software entity that comes source file; And
Judge the file name comprise this second source file of this top hardware entities that should the top software entity.
4. conversion method as claimed in claim 3, wherein this top software entity is a software program language function, this top hardware entities is a hardware description language module.
5. conversion method as claimed in claim 4, wherein this function and this module all comprise a minimum block, and this conversion method also comprises:
Judge that this software program is asserted and assert the position with respect to a software program of other blocks in same function;
Judge a plurality of blocks position of a plurality of blocks in this top hardware entities;
Judge an insertion position, the relative position relation of this insertion position and these a plurality of blocks in same module is asserted the position corresponding to this software program; And
Inserting this hardware program asserts in this insertion position.
6. conversion method as claimed in claim 1 also comprises:
Read one first group and come source file, this first group source file comprises and a plurality ofly come source file with what the software program language write as, wherein also comprises this and first comes source file;
Set up one first hierarchical structure in order to represent that this first group is come the program's code file hierarchical structure in the source file; And
Judge that one second group is come this second source file in the source file, this second group is come source file to come source file to translate by this first group, and wherein this second source file first comes the position of source file in this first hierarchical structure this second group hierarchical structure position of coming source file corresponding to this.
7. conversion method as claimed in claim 1, wherein above-mentioned software program are asserted and are comprised a Boolean algebra and an output word string, and above-mentioned hardware program is asserted and comprised an attribute definition.
8. a conversion one first comes minimum one in the source file to assert converting system in the second source file, wherein this first source file comprises with what the software program language was write as and comes source code, this second source file comprises hardware description language and comes source code, and this converting system comprises:
One reads logic, in order to this first comes source file to read a software program to assert certainly;
One first location logic, set one first block, this first block comprises this and first comes this software program in the source file to assert and a minimum software position indication code, this first location logic relative position in order to judge that this software program is asserted, this relative position are in this first block and relevant with this software position indication code;
One second location logic, set one second block, this second block is positioned at this second source file and corresponding to this first block, this second location logic is searched the minimum hardware location indication code in this second source file, and this hardware location indication code is corresponding to this software position indication code;
One translation logic is asserted as a hardware program and asserts in order to translate this software program;
One the 3rd location logic, in order to judging the insertion position in this second source file, interior this minimum hardware location indication code of this insertion position and this second block is relevant; And
One inserts logic is asserted to this insertion position in order to insert this hardware program.
9. converting system as claimed in claim 8, the first wherein above-mentioned source file comprises a minimum top software entity, and this second source file comprises a minimum top hardware entities, and wherein each entity comprises a minimum block, and this converting system also comprises:
Which this top software entity one logic element is arranged in order to judge that this software program is asserted;
One logic element is asserted and a relative position that comprises other blocks in this top software entity that this software program asserts in order to judge this software program;
One logic element is in order to judge which this top hardware entities is corresponding to comprising this top software entity that this software program is asserted; And
One logic element is judged in this top hardware entities of correspondence in order to insert this insertion position that this hardware program is asserted based on this relative position.
10. converting system as claimed in claim 8 also comprises:
The position that one logic element is asserted in order to this software program of locating in this first block, this first block are arranged in this first this top software entity that comes source file; And
One logic element comprises file name to this second source file of this top hardware entities that should the top software entity in order to judgement.
11. converting system as claimed in claim 10, wherein this top software entity is a software program language function, and this top hardware entities is a hardware description language module.
12. converting system as claimed in claim 11, wherein this top software entity and this top hardware entities comprise a minimum block, and this converting system also comprises:
One logic element is asserted the position in order to judge that this software program is asserted with respect to a software program of other blocks in same function;
One logic element is in order to judge a plurality of blocks position of a plurality of blocks in this top hardware entities;
One logic element is in order to judging an insertion position, and the relative position relation of this insertion position and these a plurality of blocks in same module is asserted the position corresponding to this software program; And
One logic element is asserted in this insertion position in order to insert this hardware program.
13. converting system as claimed in claim 8 also comprises:
One logic element comes source file in order to read one first group, and this first group source file comprises and a plurality ofly come source file with what the software program language write as, wherein also comprises this and first comes source file;
One logic element is in order to set up one first hierarchical structure in order to represent that this first group is come the program's code file hierarchical structure in the source file; And
One logic element is in order to judge that one second group is come this second source file in the source file, this second group is come source file to come source file to translate by this first group, and wherein this second source file first comes the position of source file in this first hierarchical structure this second group hierarchical structure position of coming source file corresponding to this.
Comprise a Boolean algebra and an output word string 14. converting system as claimed in claim 8, wherein above-mentioned software program are asserted, and above-mentioned hardware program is asserted and is comprised an attribute definition.
15. conversion one a software program language comes the hardware description language of asserting in the source file to come the method in the source file, comprises:
Reading a software program from the one first software program language program code that comes in the source file asserts;
Locate the position that this software program is asserted in the software program function;
Read a hardware program module from a second source file, this hardware program module is to should the software program function, this second source file comprises by this and first comes source file coming source program code to translate and the hardware description language that comes comes source program code, and wherein this second source file does not comprise by this and first comes source file to translate and the hardware program that comes is asserted;
Changing this software program is asserted as a hardware program of being write as with hardware description language and asserts;
, assert in an insertion position of this hardware program module based on the position judgment of this software program function in order to insert this hardware program; And
Inserting this hardware program in this insertion position asserts.
16. conversion method as claimed in claim 15, wherein above-mentioned this software program function and this hardware program module all comprise a minimum block, and this conversion method also comprises:
Judge that this software program is asserted and assert the position with respect to a software program of other blocks in this software program function;
Judge a plurality of blocks position of a plurality of blocks in this hardware program module;
Judge that corresponding to this software program among this a plurality of blocks position asserts a corresponding block position of position; And
Inserting this hardware program asserts in this correspondence block position.
Comprise a Boolean algebra and an output word string 17. conversion method as claimed in claim 15, wherein above-mentioned software program are asserted, and above-mentioned hardware program is asserted and is comprised an attribute definition.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/445,013 | 2006-06-01 | ||
| US11/445,013 US20070294647A1 (en) | 2006-06-01 | 2006-06-01 | Transferring software assertions to hardware design language code |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101055523A true CN101055523A (en) | 2007-10-17 |
Family
ID=38795377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101010439A Pending CN101055523A (en) | 2006-06-01 | 2007-04-23 | Method for exchanging software program code to hardware described language program code |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20070294647A1 (en) |
| CN (1) | CN101055523A (en) |
| TW (1) | TWI329821B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104199652A (en) * | 2014-08-26 | 2014-12-10 | 邱涌 | C TO HDL synchronous mapping method based on data flow |
| CN111192503A (en) * | 2018-11-15 | 2020-05-22 | 株式会社麦卢思 | Block type wireless coding command input device and method |
| CN111615688A (en) * | 2019-05-28 | 2020-09-01 | 深圳市大疆创新科技有限公司 | Assertion verification code binding method and device |
| CN112364580A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN112364581A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN112560401A (en) * | 2020-12-22 | 2021-03-26 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
| CN113496105A (en) * | 2020-03-20 | 2021-10-12 | 洛极豪斯私人有限公司 | Method for synthesizing RTL description of HDL for digital circuit design |
| CN114547085A (en) * | 2022-03-22 | 2022-05-27 | 中国铁塔股份有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN116661794A (en) * | 2023-04-21 | 2023-08-29 | 合芯科技有限公司 | Hardware description language semantic conversion method and device |
| CN116663463A (en) * | 2023-07-27 | 2023-08-29 | 北京开源芯片研究院 | Circuit verification method and device, electronic equipment and readable storage medium |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7934183B2 (en) * | 2008-04-25 | 2011-04-26 | Synopsys, Inc. | Method and apparatus for simulating behavioral constructs using indeterminate values |
| TWI407370B (en) * | 2010-04-30 | 2013-09-01 | Univ Nat Taiwan | A circuit system and common method of regular expression |
| JP6352607B2 (en) * | 2012-09-07 | 2018-07-04 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Assertion generation apparatus and method, and processor verification apparatus and method |
| US20140282390A1 (en) * | 2013-03-15 | 2014-09-18 | Nvidia Corporation | System, method, and computer program product for creating a compute construct |
| US9015643B2 (en) | 2013-03-15 | 2015-04-21 | Nvidia Corporation | System, method, and computer program product for applying a callback function to data values |
| US9323502B2 (en) | 2013-03-15 | 2016-04-26 | Nvidia Corporation | System, method, and computer program product for altering a line of code |
| US9021408B2 (en) | 2013-04-10 | 2015-04-28 | Nvidia Corporation | System, method, and computer program product for translating a source database into a common hardware database |
| US9015646B2 (en) | 2013-04-10 | 2015-04-21 | Nvidia Corporation | System, method, and computer program product for translating a hardware language into a source database |
| US9171115B2 (en) | 2013-04-10 | 2015-10-27 | Nvidia Corporation | System, method, and computer program product for translating a common hardware database into a logic code model |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2173812C (en) * | 1995-04-11 | 2000-02-08 | Shinichi Kikuchi | Recording medium, recording apparatus and recording method for recording data into recording medium, and reproducing apparatus and reproduction method for reproducing data from recording medium |
| US6226776B1 (en) * | 1997-09-16 | 2001-05-01 | Synetry Corporation | System for converting hardware designs in high-level programming language to hardware implementations |
| US6625797B1 (en) * | 2000-02-10 | 2003-09-23 | Xilinx, Inc. | Means and method for compiling high level software languages into algorithmically equivalent hardware representations |
| US7346881B2 (en) * | 2002-05-13 | 2008-03-18 | Tensilica, Inc. | Method and apparatus for adding advanced instructions in an extensible processor architecture |
| US20040163072A1 (en) * | 2003-02-19 | 2004-08-19 | Royal Design Ltd. | Electronic design automation with automatic generation of hardware description language (HDL) code |
| US7769794B2 (en) * | 2003-03-24 | 2010-08-03 | Microsoft Corporation | User interface for a file system shell |
-
2006
- 2006-06-01 US US11/445,013 patent/US20070294647A1/en not_active Abandoned
-
2007
- 2007-02-09 TW TW096104799A patent/TWI329821B/en active
- 2007-04-23 CN CNA2007101010439A patent/CN101055523A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104199652A (en) * | 2014-08-26 | 2014-12-10 | 邱涌 | C TO HDL synchronous mapping method based on data flow |
| CN111192503A (en) * | 2018-11-15 | 2020-05-22 | 株式会社麦卢思 | Block type wireless coding command input device and method |
| CN111615688A (en) * | 2019-05-28 | 2020-09-01 | 深圳市大疆创新科技有限公司 | Assertion verification code binding method and device |
| CN113496105A (en) * | 2020-03-20 | 2021-10-12 | 洛极豪斯私人有限公司 | Method for synthesizing RTL description of HDL for digital circuit design |
| CN112364580A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN112364581A (en) * | 2020-11-13 | 2021-02-12 | 上海兆芯集成电路有限公司 | Method and device for automatically inserting specific code into register transmission level design file |
| CN112560401A (en) * | 2020-12-22 | 2021-03-26 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
| CN112560401B (en) * | 2020-12-22 | 2024-04-09 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
| CN114547085A (en) * | 2022-03-22 | 2022-05-27 | 中国铁塔股份有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN116661794A (en) * | 2023-04-21 | 2023-08-29 | 合芯科技有限公司 | Hardware description language semantic conversion method and device |
| CN116661794B (en) * | 2023-04-21 | 2024-04-05 | 合芯科技有限公司 | Hardware description language semantic conversion method and device |
| CN116663463A (en) * | 2023-07-27 | 2023-08-29 | 北京开源芯片研究院 | Circuit verification method and device, electronic equipment and readable storage medium |
| CN116663463B (en) * | 2023-07-27 | 2023-11-10 | 北京开源芯片研究院 | Circuit verification method and device, electronic equipment and readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070294647A1 (en) | 2007-12-20 |
| TW200805102A (en) | 2008-01-16 |
| TWI329821B (en) | 2010-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101055523A (en) | Method for exchanging software program code to hardware described language program code | |
| CN1906619A (en) | Assertion generating system, program thereof, circuit verifying system, and assertion generating method | |
| CN1368693A (en) | Method and equipment for global software | |
| CN1828618A (en) | Semiconductor designing apparatus | |
| CN100342381C (en) | Integrated circuit design conforming method and component element, transaction method and product applied thereby | |
| CN1419211A (en) | File conversion system and method, readable medium for storing file conversion program | |
| CN1503161A (en) | Statistical method and apparatus for learning translation relationship among phrases | |
| CN1834955A (en) | Multilingual translation memory, translation method, and translation program | |
| CN101065746A (en) | System and method for automatic enrichment of documents | |
| CN1490744A (en) | Method and system for searching confirmatory sentence | |
| CN1530863A (en) | Design detecting system, design method and design detecting program | |
| CN1801155A (en) | Method for combination of original files of hardware design language and checking data files | |
| CN101051332A (en) | Verifying system and method for SOC chip system grade | |
| CN1934565A (en) | Machine translation system, machine translation method, and program | |
| CN100337231C (en) | Structured document processor , method and programme | |
| CN1734458A (en) | Methods and systems for electronic device modelling | |
| CN1667622A (en) | Design verification using formal techniques | |
| CN1702650A (en) | Apparatus and method for translating Japanese into Chinese and computer program product | |
| CN1523660A (en) | Bidirectional technique system of integrated circuit design | |
| CN1539113A (en) | Representing design of sub-module in hierarchical integrated circuit design and analysis system | |
| CN1744092A (en) | Method and system for automatic schedule logic simulation and code coverage rate analysis | |
| CN1261898C (en) | Crosstalk detecting method | |
| CN1525323A (en) | Processor and compiler for creating program for the processor | |
| CN1910574A (en) | The auto translator and the method thereof and the recording medium to program it | |
| CN1169210C (en) | Design for testability method selectively employing two methods for forming scan paths in circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |