CN1539113A - Representing design of sub-module in hierarchical integrated circuit design and analysis system - Google Patents
Representing design of sub-module in hierarchical integrated circuit design and analysis system Download PDFInfo
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Abstract
A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.
Description
Technical field
The present invention relates to the electronic circuit manufacturing.More specifically, the present invention relates to be used for designing and check the content of integrated circuit and the system of layout.
Background technology
In robot calculator Aided Design (ECAD) software systems, must and realize data as one group of data-base recording storage integrated circuit (IC) design standard, and have certain limited maximum length owing to move these records of virtual memory capacity of the computing machine of this software thereon.In addition, the execution time of ECAD software increases with the scale of design usually.The data of a very large integrated circuit (IC) design of expression may be too greatly can not adaptometer be calculated the storer of machine, and perhaps, the execution time that the whole designing institute of design or emulation needs may be long.The quantity of the element in integrated circuit (i.e. door) and follow be connected to several ten million, several hundred million or more for a long time especially like this.
Hiberarchy Decomposition or " division " are a kind of technology that can be used to reduce the complicacy of big integrated circuit (IC) design standard, thereby the storer of finishing design and/or execution time are kept is manageable.Need not single panel data storehouse represent design, but design is divided into be commonly referred to " piece " but independent design and the fragment of check.Utilize given individual layer level, design specifications is made up of the interconnection of the top layer between a chunk and these pieces.Adopt the level of multilayer, piece itself is made up of the littler sub-piece and the interconnection of sub-piece.
Design group can also serve as the method for dividing design item between the numerical digit designer to Hiberarchy Decomposition simply as organization tool.But, the logical level that design group sets up in design planning needn't with for the physical level realizing dividing in the design and adopted identical.Usually logical layer less important firmly get than physical level many.Can utilize the piece formation process that logical level is transformed into physical level.
Conventional hierarchical Design plan is undertaken by two key steps usually: top-down slip gauge is drawn step and is followed bottom-up checking procedure.If block itself is realizing during the top-down stage that (promptly realizing each piece before its children) this flow process is called top-down flow process.On the contrary, if realizing during the bottom-up stage that this flow process of piece (promptly realizing this piece after all children of each piece finish) is called bottom-up flow process.Top-down flow process and bottom-up flow process respectively have merits and demerits.Under the situation of being without loss of generality, in the remainder of this paper top-down flow process as an example.Can utilize the bottom-up flow process of constructed realization.
Fig. 1 illustrates typical top-down slip gauge and draws and realization flow.It is from dividing design netlist, with logical level conversion (mapping) one-tenth physical level, thereby defines top layer piece and the one group of sub-piece (step 110) that will realize.Then to the layout (step 115) in each sub-piece distribution width and height value and the plane figure.To the pin assignment position on each sub-piece, they represent net and the crossing position (step 120) of this sub-block boundary then.Be the time budget step then, this step is to each sub-piece pin assignment signal arrival/required time restriction, the timing path that intersects with sub-block boundary distributed which part (step 135) of clock period with indication.
In top-down flow process this moment, after having planned the top layer piece, this process prepares to realize this piece.All leaf unit (standard block and macroelement) that this piece is had distribute layout, and all nets (step 140) of having of this piece that connects up.(so-called " feedthrough net ") shifted these leads downwards onto in the sub-piece of their overlap joints if any net connects up on sub-piece, and forms new pin (step 145) at these leads and sub-block boundary intersection on sub-piece.Then, recursively realize each sub-piece (step 150) according to identical process.This relates to and each sub-piece is treated as the top layer piece recursively carries out step 110 to 170.
In order successfully to finish top process, shape, Pin locations and timing budget that each piece is distributed must embody attainable restriction.Otherwise this system may not finish the realization of these pieces according to the standard of some piece.Before reaching correct realization, may need to revise standard and may need to repeat this top-down process in this case.This iterative modifications is consuming time, thereby should avoid.Therefore, it is extremely important to be used for reaching the method for high quality results in these steps.
When the top-down planning of finishing this recurrence and performing step, can begin bottom-up checkout procedure.From bottom piece to top layer, with regard to logical correctness, timing and electrical property analyze independently each piece and and its standard according to (step 155).After checking all sub-pieces of a piece independently, can analyze this piece itself (step 170) at all sub-pieces of supposition correctly down.
Summary of the invention
In various embodiments, the present invention includes and set up and use is called the simplified model of piece " abstract ", it is the structure of capture block and behavior at length enough, thereby can correctly analyze with its father's piece and with the interface of mass.This abstract target is to reduce memory space from the required use of this piece to the elder generation of piece in level that express, and reduces at his father's piece and the needed execution time amount of each example piece of analysis in the mass environment.
Description of drawings
By reading following detailed description and will be better appreciated by these and other purpose of the present invention, feature and advantage being inconjunction with under each accompanying drawing situation, in the accompanying drawing:
Fig. 1 illustrates typical top-down planning and realization flow;
Fig. 2 illustrates the hierarchical Design process according to the one or more embodiment of the present invention;
Fig. 3 illustrates at least the abstract processing according to one embodiment of the invention;
Fig. 4 illustrates at least and handles according to the logical shell mark of one embodiment of the invention;
Fig. 5 illustrates one and goes through the piece that this mark is handled;
The deal with data input step of Fig. 6 overview diagram 4;
Forward shown in Fig. 7 overview diagram 6 is handled the pin step;
The processing output step of Fig. 8 overview diagram 4;
Reverse process pin step shown in Fig. 9 overview diagram 8;
The processing clock input step of Figure 10 overview diagram 4;
Figure 11 summarizes the processing clock of forward shown in Figure 10 pin step;
Shell model when Figure 12 illustrates physical set in one embodiment of the invention; And
Figure 13 illustrates a kind of example computer system that can realize and use one or more embodiment of the present invention.
Embodiment
A kind of mode that realizes top-down hierarchical Design process is shown in Fig. 2 and the hierarchical Design flow process of describing.Design cycle shown in Fig. 2 is the improvement to the top-down flow process shown in Fig. 1 that has three additional steps 230,260 and 265.This improvement relate to during a kind of top-down budget process, piece performing step and the bottom-up checking procedure at his father's piece and under with mass environment (Context) to the method for a sub-piece modeling.These steps are represented the position on the clear level of overslaugh border in the flow process and the position that need analyze transboundary.If that does not manage that this effective technology of analyzing can lose the hierarchical Design process transboundary can reduce to design required storer of large-scale integrated circuit and the major advantage of working time.
During top-down budget process, a purpose is to analyze combinational logic path (logic gate between latch and/or the trigger) of crossing one or more levels border and the clock period share of determining each section in path is answered budget.
During top-down performing step, a piece was set before realizing its each sub-piece also determines its wiring.This layout and wiring are chosen in good decoupling on the level border in most applications, but, many modern manufacture process requirement wiring leads are observed one group of rule that is called " antenna rule ", the detailed grasp of the wiring lead that these rules need occur on the level boundaries on either side.
During bottom-up checkout procedure, also need to analyze the combinational logic path of crossing over the level border.When analysis contains the piece of sub-piece, should wish the fact of utilizing each sub-piece to check in advance, thereby avoid when analyzing their father and mother, analyzing once more each sub-piece.
In order to solve this three kinds of situations, the present invention openly uses a kind of simplified model that is called piece " abstract " in various embodiments, and it is the structure of capture block and behavior at length enough, thereby can correctly analyze with its father's piece and with the interface of mass.This abstract target is to reduce amount of memory from the required use of this piece to the elder generation of piece in level that express, and reduces at his father's piece and the needed execution time amount of each example piece of analysis in the mass environment.
As previously described, in this respect, replenish and strengthen the hierarchical Design flow process of Fig. 1 by adding step 230,260 and 265.Before the time budget step, that sets up each sub-piece in step 230 abstractly uses for the budget period.Because sub-piece still is unrealized, it does not comprise the physics realization data, has only its net table explanation.Thereby the abstract logic behavior modeling that means an antithetical phrase piece that the budget period uses still can not obtain the details of physical behavio(u)r and electric behavior.Should be initial abstractly use and then discarded in the budget period.
Push away under time budget, place and route, the lead, piece is realized and block check (step 235,240,245,250 and 255) after, set up second abstract (step 260) of each piece.Owing to finished piece design now, this abstract must be to detailed physics and electrical characteristics and its logic behavior modeling of piece.
Because checkout procedure is bottom-up appearance, has checked all children of this piece before piece self is verified independently.Its all sub-pieces (step 263) of abstract replacement in inspection period of piece with each height piece, thus the realization of sub-piece and the fact that behavior has almost been checked utilized.Have only the combinational logic path that surpasses the level border to wait check.In being upward through the process that level moves, I haven't seen you for ages obviously accelerates the check of piece and can reduce memory requirement by this abstract data minus that provides.
Although step 210,215,220 is similar to piece 110,115 and 120 respectively in the operation, all other step 230-270 are owing to the abstract of their Treatment Design rather than handle original design itself and be enhanced.
Main difference between top-down realization flow and the bottom-up realization flow is that piece was realized in the former before its children, and piece is realized after its children in the latter.Should be modified as a piece 240 and 245 to the level realization flow of Fig. 2 is placed among piece 265 and 270.Main influence is in top-down flow process, to realize the top layer piece before the realization of finishing its children.Thereby the present invention's bundle piece budget when realizing its father and mother is used as desirable optimization.On the other hand, in bottom-up flow process, piece must be realized before its father and mother or known realization with mass.Thereby must use its timing budget as desirable optimization aim.
When in bottom-up realization and inspection process, using, with wherein only verify as bottom-up top-down realization flow in the same, can use this illustrated abstract mechanism equivalently.But, in bottom-up realization flow, utilize and abstractly may cause father's piece of realizing it down more high-quality to the sub-piece finished rather than to idealized budget modeling.The back is listed " contrary abstract " mechanism in detail, and it allows to realize identical benefit in top-down flow process.
Existing abstract method depends on the behavior model of simplification, so that the approximate behavior description of the logic of capture block, physics and electric behavior.Usually express them with the mathematical model related with each pin.The logical specification of each pin for example, can be described with scale-of-two process decision chart (BDD).Can catch the electric explanation of each pin with the linearization RC network that is simplified to fixed time quantity.At present, do not exist known being used for to set up the method for the simplification physical message model of the antenna parameter of expressing pin.Owing to lack effectively abstract to this a kind of application in back, need a kind of antenna configuration avoidances technology usually, for example insert diode at each pin place, thus the circuit performance of generation simplification.
Adopt and use the abstract mechanism that the following describes and cause a kind of really approximate to the coordinating and unifying of all complementary timing analysis, electroanalysis, place and route and budget each other.In addition, the traditional abstract mechanism that is similar to mathematical model with traditional dependence is different, and it guarantees accuracy completely.
Timing analysis
Static timing analysis relates generally to the travel-time of calculating data-signal between latch and/or the trigger.This information both had been used for optimizing the logic of father's piece, was used for the timing of each children's piece of check under the environment of the compatriot of children's piece and father's piece again.If one one or more levels border is crossed in the combinational logic path, when only each section that passes each layer of this level when this path all has routing information, just can carry out timing analysis accurately.From static state timing viewpoint, need only the identical timing characteristic of the boundary of piece abstract expression lower level piece to the higher level piece, the higher level piece can not identify the difference between simplified model and the complete model.The timing characteristic that must catch by the lower level piece is the time of arrival of required time and each main output pin of each main input pin.
If the accurate operating environment of congenital known each piece can these two information of calculated in advance.But because inspection process is bottom-up carrying out, the higher level piece can not accurately provide this information.Inaccurately know input conversion (slew) information and the output load information of sub-piece.In addition, can not express such as regularly unusual information with this naive model.
Thereby might utilize the linear delay model of extraction in advance or analyze the structure look-up table, model conversion and load effect modeling by on the lower level piece, repeatedly changing conversion value and load value.But it is so inaccurate that these oversimplify models, can not be exactly to the interconnection network modeling before the position of determining driver and receiver accurately and wiring topology.And the delay or the signal coupling effect (cross (talk) postpones and noise injects) that depend on signal can not be described.
Electroanalysis
Electroanalysis relates to the checking piece and its each assembly can not depart from their idealized electrical characteristics in operation.Two kinds of effect examples that must give modeling comprise IR pressure drop and electromigration.
Comprise the IR drop measurement supply network of power voltage-drop and ground connection knock-on and the imperfect behavior on the ground networks.The lead that constitutes distribution network has the resistance of non-zero, thereby big current loading can make supply voltage depart from their rated range causing on each aspect of these leads.This effect can cause the variation of not expecting in the circuit timing behavior, and can cause falling flat of circuit operation under extreme case.
Electromigration failures causes because of the high current intensity in the nonideal resistive lead equally.But different with the IR pressure drop, these faults cause the physics in the lead to change rather than electric change.These high electric currents of life period at integrated circuit can cause the original position migration of metallic atom from them, and this can cause making non-existent short circuit constantly and open circuit.
The analysis result of IR pressure drop is if indication fault can serve as the feedback to the distribution network design.It also can be used for improving the precision of the chronometric analysis that illustrates previously.The result that electromigration is analyzed, if indication fault can be used to influence the realization of circuit itself, thus the width (resistance) of the lead that uses during requiring to change circuit meshwork list or changing wiring.
These two kinds of electrical effects all require observed definite voltage and current on the every lead of labor circuit.Depend on the model that is used for measuring and predicting these faults, this analysis may be static state or average case analysis, and perhaps it may require dynamic time domain logical OR circuit simulation.As static timing analysis, must be to these effect modelings under abstract situation.
Place and route
Layout processing is physical arrangement piece and sub-piece and connect up and refer to them and how to interconnect on integrated circuit how.The physical layout of piece and its wiring of each pin only needed few information to the physique of piece.The pin physical dimension of piece provides one group of assigned address, allows the wiring personnel to be connected with each pin on these positions.Usually all the other internal geometric sizes that can represent piece with one group of square of simplifying greatly, these are simplified squares and avoid causing short circuit in father's piece or violate the design rule of each unit and avoid connecting up in piece.
But modern deep sub-micron manufacturing technology (minimum feature size is less than the technology of about 250 nanometers) has been added a kind of difficulty to this model.The violation that detects and repair the antenna rule needs detail knowledge leap level border to connect the wiring lead topology of driving gate and reception and understand transistor gate, source and the drain electrode that all are connected with these leads.
Budget
Usually, in order to obtain to be used for optimum and the attainable budget of sub-piece, must on all logical paths on the level border of crossing over piece, carry out static timing analysis.This analysis must arrive all registers that can see from each pin of sub-piece, no matter in one of same mass of the father's piece in this level, sub-piece or this sub-piece which these registers belong to.A benefit is to neglect the combinatorial path that is completely contained in this sub-piece safely, and this reduces the expense of this analysis greatly.
If budget process allows to carry out the logic optimization of crossing the boundary and carries out static timing analysis, might realize real optimum budget allocation.This technology is the middle explanation of patented claim common co-pending (attorney reference 054355-0293259) of " method that generates design limit for the model in the level IC design system " at the title of application on June 10th, 2002.
The piece abstraction process
Aspect, a center of the present invention as back explanation like that, is the abstract method of piece, and this method realizes that desirable logic and physical data simplification step defer to the requirement of summarizing above simultaneously.Its key is not to be the simplification mathematical model that reduces with accuracy but represents design with a subclass of design data itself.The model of this simplification is made of the master pattern copy, but has discarded all unessential informations.Alternatively narration, by only copy those correctly at the father's piece in its level and under with the mass environment to the required logic netlist element of piece modeling and physical block realize element set up abstract, thereby reach the quantity that significantly reduces blocks of data.
The remainder of this paper is listed in detail and is included in level piece being used for to the logic of piece and the logic netlist object and the physical layout object of physical characteristics modeling in abstract, wherein these logics and physical characteristics comprise such key physical effect, for example antenna rule, capacitance-resistance (RC) line delay, cross (talk), noise injection, IR pressure drop and electromigration effect.Utilize the piece of this abstract modeling to be used for top-down budget having under the complete in fact accuracy situation, bottom-up static timing analysis and electroanalysis and top-down or bottom-up one of realize.By the accuracy that optionally only keeps to analyze its father's piece in each piece independently and/or reach this degree with the data subset of mass.The data of these maintenances can comprise logic (net table) data, design limit and physics (layout) data.By comprising physical object itself rather than comprising their simplified model or worst case model, can not lose accuracy.
Abstraction process can be regarded as by two key steps shown in Fig. 3 and constitute.At first, according to step 310, from the scope of the logic " shell " of determining piece.This is the unit group that the combinatorial path along the input and output pin of this piece can reach, and comprises first latch or the trigger that at first run into along each paths.This group also must comprise some other carry the necessary unit of information for unit above-mentioned being provided hold accurately.The register cell that is defined in fully within this piece does not exert an influence to the external definition of this piece, thereby is not included in the logical shell.The figure that utilization is discussed in the chapters and sections of back is across determining the content of logical shell with labeling algorithm.
After the content of having determined logical shell, then in step 320, determine the physical geometry set of dimensions that must in this is abstract, keep.In order to need these physical dimensions to the resistance of the network of logical shell and electric capacity modeling and for cross (talk) and the modeling of noise injection effect.Shown in the back, in order also may in logical abstraction, to comprise some other unit to these effect modelings.
Fig. 4 is the step 310 according at least one embodiment of the present invention, i.e. logical shell mark, detail flowchart.Utilize algorithm of nodes in the timing diagram of a tag block to determine the content of logical shell.Timing diagram is the oriented graph by following information architecture:
(1) net table (how description unit is connected to each other);
(2) cell library (how descriptor flows through the unit); And
(3) regularly restriction (description block, the edge that regularly makes an exception and disconnect).
Node of graph representative unit pin, and the edge representative connects the network of these pins.Reiterate, the purpose of mark be only keep when from each during main pin observation for provide the shell model outside with complete module in the essential unit of existing on all four timing diagram.
The logical shell mark is handled and is started from being derived from the depth-first of data (non-clock) the primary input pin set in this logical shell across (frame 410).The depth-first that then is derived from main output pin group is across (frame 420).At last, according to piece 430, the degree of depth that is derived from clock (non-data) primary input pin set preferably across.
According to following rule be marked at these depth-firsts across during the unit (note allowing a unit to have mark) that runs into more than one:
1) timing unit:
Being defined as one can be from the unit that a primary input or output pin arrive, and these unit collectively define the timing diagram that can see from these main pins.
2) multiple driver load unit:
To be defined as one itself be not a timing unit but drive the unit of network with timing unit the samely.
3) remittance (leaking sink) load unit:
When this driver element was not clock network a part of, being defined as one, what driven by timing unit itself was not the unit of timing unit.
4) clock load unit:
Except being the part of clock network, driver element is similar to the remittance load unit.
Fig. 5 illustrates a piece that handled by this mark.In the sample block shown in this, provide following assembly by the input complete list.This piece comprises major clock input pin a: CLK; Four master data input pin: CG, IN0, IN1, and IN2; And two main outputs: OUT0 and OUT1.Unit R 1, R2, R3, R4 and R5 are register (trigger) elements.Assembly C1, C2, C3, C4 and C5 are the logical circuits (cohort of contiguous location) of combination in any.Unit I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13 and I14 are the examples of each combinational logic gate.
This unit labeling process is based on being designated each unit pin the clock pin or being data pin.By the definition, if pin be not the clock pin it be data pin.It is a standard part of any static timing analysis algorithm that mark is handled, and this paper no longer is illustrated.According to static timing algorithm, all pins on unit I1, I2, I3, I4, I10 and the I11 are designated the clock pin.In addition, last input pin on the unit I5 and the output pin on the I5 are designated the clock pin.And, the pin attached on unit R 1, R2, R3, R4 and the R5 with the triangle sign is labeled as the clock pin.List the unit mark processing procedure of the exemplary circuit that is applied to Fig. 5 below in detail.
The input pin mark is handled
The mark processing procedure is from data (non-clock) primary input.The depth-first that begins to carry out recurrence by any order from each such pin across.During a leaf in running into figure (pin that does not have the succession, for example data pin of trigger or main output) or the pin that is run into when being the clock pin, stop recurrence.At every turn across during the unit that runs into all be labeled as timing unit (node of recalling in the timing diagram is the unit pin).The unit that their output is connected to timing unit output is marked as the multiple driver load unit.An example of this multiple driver load unit is three-state driver (unit I6 and the I7 of Fig. 5).
In Fig. 6 and 7, summarize this process.Fig. 6 general introduction is according to the data pin treatment step (410) of Fig. 4.This process begins and continues to be empty (inspection of frame 620) until this tabulation from setting up a tabulation to all primary inputs of this circuit (frame 610).From this tabulation, taking out a pin (frame 630) back if to be clock pin (checking at frame 640) then skip and continue processing (once more, frame 620 to 640) with next pin for it.If not clock pin (checking) at frame 640, then occur the main forward of this pin is handled at frame 650, in Fig. 7, describe this processing in detail.
Process illustrated in fig. 7 is a recursive procedure that occurs recurrence at frame 750.(frame 710) begins processing and continues downwards to be empty (in frame 715 inspections) until this tabulation in the tabulation by all successions of this initial pin are collected.After from this tabulation, taking out a pin (frame 720), the unit of this pin is labeled as " regularly " unit (frame 725).If being the clock pin, this pin do not need further processing (checking) at frame 730.If being an input pin (checking at frame 735), this pin judges then whether this pin has the forerunner's (checking at frame 740) more than.If find forerunner's (checking), all unit in advance be labeled as " multiple driver load " unit (frame 745) at frame 740 more than one.This process flow diagram is by calling the recurrence of oneself carrying out depth-first at frame 750.
With reference to the exemplary circuit shown in Fig. 5, the input marking Processing Algorithm can be performed as follows.From input pin INO, depth-first is across running into assembly C1 and register R1, and should be across ending at register R1.Specifically across in the assembly C1 that comprises and all unit within the register R1 all be labeled as timing unit.Similarly, from input CG, all unit within assembly C2 and the unit I5 all are labeled as timing unit.Because the output of I5 is that clock pin (I5 is " clock gating " unit) is across ending at I5.From input pin IN1, all unit among the assembly C3 all are labeled as timing unit.In addition, unit I6 and register R2 are labeled as timing unit.Unit I7 is labeled as the multiple driver load unit, because its output is connected to the output of another timing unit.From input pin IN2, all unit in the assembly C4 all are marked as timing unit.Should think this moment and finish the input marking processing.
The output pin mark is handled
Then utilize depth-first to handle across carry out output token from each main output pin with similar method.Equally when running into the leaf pin in the drawings or the pin that is run into stop recurrence when being the clock pin.And equally across in the unit that runs into be labeled as timing unit.A difference of handling with input marking is, needs sign to converge (leakages) load unit, its by it the source from one be not depth-first across in the unit of timing unit of a part define.
In Fig. 8 and 9, summarize this process.The processing output step (420) of Fig. 8 overview diagram 4.Begin this process and before this tabulation is for sky, continue (checking) by setting up all primary input (frame 810) tabulation at frame 820 to this circuit.After from tabulation, taking out a pin (frame 830), forward the frame 840 that in Fig. 9, describes in detail to.
Process illustrated in fig. 9 is one and has the recursive procedure that occurs recurrence in frame 950.(frame 910) begins to handle and (in frame 915 inspections) continuation before this tabulation is sky in the tabulation by all forerunners of initial pin are collected.After from tabulation, taking out a pin (frame 920), the unit of this pin is labeled as " regularly " unit (frame 925).If being a clock pin, this pin do not need further processing (checking) at frame 930 places.If this pin is an output pin (checking at frame 935 places) then to be labeled as all follow-up unit " remittance (leaking sink) load " unit (frame 640).By calling oneself at frame 950, this process flow diagram is carried out the depth-first recurrence.
Referring again to Fig. 5 as an example, from output pin OUT0, all unit among the handle component C5 are labeled as timing unit.Unit I12 and register R3 also are labeled as timing unit.From output OUT1, all unit among the handle component C4 are labeled as timing unit.Should think that this moment finishing output token handles.
Clock pin mark is handled
The mark treatment step of last relate to from the depth-first of each major clock input origin across.In the case during leaf pin in running into figure or the pin that runs into stop when being data pin across.When ending at a data pin, check so that judge the unit of this pin whether be marked as timing unit.Only, just each unit to the path of this unit is labeled as timing unit when when ending at a unit that is labeled as timing unit.Across during, its source is labeled as clock load from the unit of a unmarked timing unit for timing unit.
In Figure 10 and 11, summarize this process.The processing clock input step (430) of Figure 10 overview diagram 4.Begin this processing and before this tabulation is for sky, continue (checking) by setting up a tabulation (frame 1010) at frame 1020 places to all major clock inputs of this circuit.The frame 1040 that this pin describes in detail in by Figure 11 take out a pin from this tabulation after is handled.
Process illustrated in fig. 11 is one and has the recursive procedure that occurs recurrence in frame 1130.(frame 1110) begins to handle and continued (checking at frame 1115 places) in the tabulation before this tabulation is for sky by all successions of initial pin are collected.After from this tabulation, taking out a pin (step 1120), check whether it is designated clock (frame 1125).If this pin is not that the clock pin does not need to do further processing (getting back to frame 1115).Carry out the recurrence of depth-first by call self this process flow diagram at frame 1130.In case return from recurrence, check to judge during recurrence whether once any succession of this pin was labeled as " regularly " (checking at frame 1135 places).If any follow-up unit was not labeled as " regularly " unit, needn't be further processed (getting back to frame 1115).If any follow-up unit is labeled as " regularly " unit, the unit of this pin is labeled as " regularly " unit (frame 1140) and all follow-up unit are labeled as " clock load " (frame 1150).End at frame 1150 stops this processing, because the unit of this pin is labeled as " regularly " unit.
Referring again to the example among Fig. 5, from input pin CLK, across meeting through unit I1 and I2 and then end at unit R 1, R2 and R3.These unit R 1, R2 and R3 are labeled as timing unit.Thereby, also unit I1 and I2 are labeled as timing unit because they along to timing unit across the path.Through I3 across ending at unit R 4.Can not arrive R4 from primary input or main output, it can only arrive through its clock pin.Unit R 4 is not a timing unit, thereby I3 is not labeled as timing unit.But because its source, promptly I1 is a timing unit, and it is labeled as clock load.With respect to R4 unit I4 is used identical argument.I4 is labeled as clock load.Through I5 and I11 across not ending at timing unit, thereby they are labeled as timing unit.Usually should be labeled as clock load to unit I5, still, from the input CG across during it is labeled as timing unit.Thereby I5 is still timing unit.
Mark is handled summary:
| IN0 | The master data input |
| IN1 | The master data input |
| IN2 | The master data input |
| CG | The master data input |
| CLK | The major clock input |
| I1 | Regularly |
| I2 | Regularly |
| I3 | Clock load |
| I4 | Clock load |
| I5 | Regularly |
| I6 | Regularly |
| I7 | The multiple driver load |
| I8 | Mark not |
| I9 | Mark not |
| I10 | Mark not |
| 111 | Regularly |
| I12 | Regularly |
| I13 | Mark not |
| I14 | Leak load |
| C1 | Regularly |
| C2 | Regularly |
| C3 | Regularly |
| C4 | Regularly |
| C5 | Regularly |
| R1 | Regularly |
| R2 | Regularly |
| R3 | Regularly |
| R4 | Mark not |
| R5 | Mark not |
| OUT0 | Master data output |
| OUT1 | Master data output |
After finishing the mark processing procedure, might determine to remain on the full unit collection in the logic timing shell.If the unit is mark in timing diagram not, it does not have direct influence in the interface timing of this piece, thereby can ignore it relievedly.From the net table, delete these unit and represent them with a dead level that is called " group " unit time piece.On this group unit, set up pin for each network of crossing its border.
False path and fixing the propagation
By using restriction of false path and fixing the propagation, reach further minimizing to the element number that is labeled as timing unit.The timing of the part of ifs circuit has infinite space, can not see this part of circuit from main pin.Thereby, can be treated as leaf among the figure to these pins when input and output mark above carrying out is handled with infinite space.
This has makes the final user by utilizing the restriction of false path and use invariable control what is marked as the benefit of timing unit.
Path unusual (exception)
With complete model is applied original unusual the same, the exert one's influence path of timing at main pin place of external shell model is unusual.Because the node that the path is applied on the node in the timing diagram unusually and keep in the shell model all to see from each main pin outside.This is feasible.Needn't attempt on the timing diagram of certain simplification, rewriteeing unusual.In addition, during shell is set up process, in the next higher level in the level required path be exposed unusually (becoming visible).When descending one deck instantiation shell model, this is to need the restriction that exposes and then rewrite them by the mode that can apply them to reach by at first discerning.In this way can be in whole design process consistent and keep crossing over the unusual of level border accurately under the mode.
Design based on latch
In one embodiment of this invention, how the design based on latch produces the desirable shell model that is used for based on the design of trigger on the indexing unit.In addition, in order to reflect the time borrowing character of latch, preserve the information of describing the amount of using for each latch in the shell model outside.This freeze in this shell model latch allowed uses, still allow the next higher level in the level to utilize time borrowing simultaneously.
In an alternate embodiment of the present invention, can handle latch by the mode the same with combinatorial logic unit.Depth-first across in only need be trigger as being leaf, this has exempted the requirement of freezing the time borrowing amount that allowed.But do not provide data to reduce abstract can be provided for this in purely based on the design of latch.
The of the present invention the 3rd may embodiment in, can make a kind of compromise, its allow stop depth-first across before user-defined latch level quantity being treated as assembled unit.The dirigibility that this allows the user to use according to the big or small control time of abstract memory image.
The foundation of physical enclosure
The foundation of logical shell produces one group of required unit of the static timing path of each bar for each pin of representing to stride across piece.This logical shell also can comprise the network that the pin of all and these unit that comprised is connected.
Physical enclosure comprises one group of topology data (interconnecting lead and path), need these group data so that consider the physical influence of integrated circuit layout and manufacturing: resistance, electric capacity, inductance, wiring are crowded and treatment technology influences such as width and interval rule antenna rule and electro-migration rules.
The physical details amount that must comprise during physics is abstract depends on the desired accuracy class of user.Between the accuracy class and the data bulk that must comprise, exist directly compromise.
Topology data is divided into severally is used in the classification of physical influence definition of modeling: 1) place and route, 2 by some) antenna effect, 3) timing analysis (RC postpones and capacitive coupling).4) noise injection effect, 5) the IR pressure drop, and 6) electromigration effect.In order to illustrate that these classifications introduce some technical new terminologies, shown in Figure 12 and in following chapters and sections, they are discussed.
1) place and route
In order during place and route, to use abstract, use a) physical size, the b of block boundary) physical location and the c that allow wiring person to be connected with each pin of piece at its place) wiring person can be used to finish each layer of these connections modeling is sufficient to piece.Model shown in Figure 12 needs block boundary and all by " pin leads " group of the lead of each pin that belongs to this piece definition.
If allow to stride the wiring of piece, then in abstract, must comprise the enough information that is used to refer to wherein and on which layer, allows to stride the piece wiring.With one group of polygon modeling, these polygons are represented the zone that preventions connected up it on each wiring layer to these zones, thereby this group is polygonal against being the zone that wherein allows the outside to connect up.Can organize stop block to this makes needed so big so that reach any resolution that requires degree.But, only needing usually the section that is not stoped is constrained to the fixing wiring channel of one group of relatively little width, these wiring channels interruptedly do not extend to the other end from an end of piece.
2) the antenna rule is checked and is proofreaied and correct
Being used for the rule of a kind of more difficult type in the treatment technology rule of accurate modeling is the antenna rule.The electric charge that accumulates on connection metal (aluminium or copper) the wiring lead of these rules to the mosfet transistor door may be to these infringement modelings that causes.When during the manufacturing these plain conductors being carried out configuration and etching on these leads stored charge, this may cause the thin oxide layer of the MOSFET door that is connected with them to puncture, but can fall this charge discharge by the junction diode that forms at the MOSFET source/drain section place that is connected safely.Can be by a special-purpose diode of implanting specially for this reason safely to this charge discharge.
To the modeling of these antenna effect, in this is abstract, must comprise lead that all are connected with each pin on electric and diode, transistor gate and the transistor source/drain electrode that all are connected with these pins through these leads for exactly.In Figure 12, use these term classifications of pin leads, pin network, pin units and diode mark respectively.By in this is abstract, comprising these physical objecies, might under the elder generation of this piece in level environment, carry out the inspection of antenna rule and carry out the reparation of antenna rule violation.
3) have the static timing analysis that interconnection RC postpones
For piece being carried out static accurately timing analysis, need each unit of logical shell, and each network that need interconnect them.Figure 12 illustrates family unit, boundary register group and other boundary element that constitutes logical shell.
But, except the idealized delay that can utilize the calculating of logical shell net table, the also ghost effect modeling that will cause for how much to layout by piece.In order correctly to extract resistance and the electric capacity of seeing by each unit in the timing shell, must comprise that lead (being called pin leads among Figure 12) that the primary input/output pin of each bar and piece is connected and each bar realize the lead (being designated as the shell lead among Figure 12) of the network that all are connected with unit in this timing shell.
Comprise the comprising of pin leads and shell lead dead resistance and stray capacitance that the lead group by the timing shell produces, but still omitted the sidewall capacitance that causes by their adjacent wires (being called coupled-wires among Figure 12).For piece is extracted and timing analysis accurately, also must comprise these leads.But, note that when simple R C being postponed (do not have to imitate and disturb) modeling, only these coupled-wires need be comprised, and all leads on each coupling network needn't be comprised.Can think that these coupled-wires are positioned under the fixed potential, thereby only work to increase the effective capacitance of pin leads and shell lead.
4) have the static timing analysis that cross (talk) postpones and noise injects
Because well-known the Miller effect, the voltage change meeting on the lead causes corresponding change on all capacitively coupled adjacent wires.Thereby, to the timing modeling on pin leads among Figure 12 and the shell lead, need know the actual signal waveform on each coupled-wires for exactly.In order to calculate the waveform of coupled-wires, require physical enclosure to comprise all leads in the complete coupling network, and logical shell must comprise the unit (group) that is driven by this coupling network and comprise that the driver element (group) from this coupling network gets back to the fullpath of their source-register.
In addition, in order correctly to catch the electric capacity that this coupling network is seen, must comprise all and the capacitively coupled lead of this coupling network.Because these leads transmit ground and pin leads and the coupling of shell lead in some sense, they are called the transmission lead.The coupling network that any electromotive force is fixing, for example power net and grounded screen can play delay of shielding cross (talk) or noise injection to pin net and shell net.These leads are called shielded conductor, and it is irrelevant with them to transmit lead.
The logical organization that depends on the piece design by logic discussed above and the abstract accessible data minimizing degree of physics.That mainly delimit with register and most of connection table is that the piece of inside can reach high minimizing degree for group unit.As opposite extreme, the piece of pure combination can not reach minimizing at all.
When needs high compression (for example to the restriction of database size or working time), the level partition process should be known abstract method and should attempt piece is delimited with register as much as possible.But even on aspect other in good design of dividing, some networks still may face the dark relatively logic of piece in abstract that be in.Can utilize few techniques to simplify the modeling demand of these scramble networks.
If related network is had a mind to conductively-closed, cross (talk) effect or noise can not occur and inject.The loading that every pin leads and shell lead are seen is fixed.Thereby the signal waveform that is provided to this pin is only depended in the delay on each input pin, and the load that this pin is provided is only depended in the delay of each output pin.If these pins do not have near critical delay, can utilize traditional delay model such as look-up table and piecewise linearity delay function safely to they modelings.
Even network is not shielded fully, still can utilize static timing analysis that nonessential pin is formed worst delay model.Like this, only need use the abstract mechanism that increases complicacy of the present invention to the pin that in design, constitutes crucial timing path like that.
Can also utilize common logic gate to have the fact of high relatively electricity gain, thereby input conversion (slew) compliance tend to attenuate after the logic of two layers or three layers.Utilize this supposition after running into the logic of two layers or three layers, can stop the mark of timing unit is handled, and can utilize of the influence modeling of better simply modeling technique based on look-up table other unit that excludes.
5) have the static timing analysis of IR pressure drawdown analysis
As early discussing herein, the IR pressure drop is the effect that is caused by the big electric current that flows through the power distribution net in the chip.The electric current that observed voltage equals to flow through this point on any point in this network multiply by the dead resistance between this point and the power supply.But what occur in this network sends electric capacity and can be offset this effect a little, and this stray capacitance is stored some can be as being the electric charge of the distributed current source of alternation.Can also utilize special-purpose decoupling capacitance device to strengthen this effect.
When using piece abstract, suppose that this piece itself is analyzed and know that its IR pressure drop upsets in bottom-up inspection period.The father and mother of this piece can experimental field utilize this abstract in to the influence modeling of this piece to the IR pressure drop.Interface between this piece and its father and mother comprises power pins, and the electric power network of this piece and its father and mother are connected on these pins.For each pin, the accurate model that is used for the IR pressure drop should comprise that a time-varying current source or remittance add the equivalent network of RC network between this pin and power supply and the ground.
Different with Utopian mathematical model, abstract method of the present invention by circuit the net table and the physical geometry of himself to each imperfect electrical effect modeling of circuit.Sorry be that the IR pressure drop is not based on the path and static timing analysis or cross (talk) local formula, but will be to relating to the overall effect modeling of each unit in whole power supply/ground networks and the piece.Can use simple circuit model for this reason.With an ideal current source or converge, with the result of the worst case electroanalysis of representing this piece to each pin modeling.This analysis can be static analysis or dynamic simulation.Each pin also related a equivalent electrical circuit to inner RC network, it uses the impedance matrix modeling.
6) electromigration analysis
Electromigration also is a kind of imperfect resistance effect related with electric capacity of electric current and these leads of and each the bar lead that flows through circuit.But, different with the IR pressure drawdown analysis it only relate to distribution network, must carry out electromigration analysis (usually only having on the resistive lead of length of big high current driver unit problem is arranged) on supply network and the normal signal line.
For to the electromigration modeling on the supply network lead, need the spurious impedance of lead and how many electric currents to flow through every lead.Electromigratory different model may need electric current maximum or average case, even may need detailed time-domain-simulation.For electric power network, the required information of this information and IR pressure drawdown analysis is identical, thus the abstract mechanism that can use identical front to illustrate.For signal conductor, information is identical with the desired information of static timing analysis model.Thereby, needn't be to other modeling information of abstract interpolation that is used for to electromigration preparation modeling.
" contrary " abstract mechanism
In other embodiment of the present invention, utilize essentially identical technology also may make up " contrary " abstract form in top-down check stream, using.The front has illustrated wherein at first under isolating analysis and proof mass and the then bottom-up block check procedure of check once more under father's piece of piece and compatriot's environment.Under isolating, can only check each unit in " family unit ", promptly not be included in abstract interior unit.Relate to that all timing paths of the unit that comprises in the abstract logical shell and physical geometry size and various electrical effect need to obtain the father and mother of relevant piece before can be analyzed and with the information of mass.
May wish to analyze independently and check a piece, the perhaps checkout procedure that must carry out as piece being released into one section independent utility IP (intellecture property) that re-uses after being provided with.Under this sight can by this block check of instantiation in " test wire harness (harness) " it, this test wire harness is father's piece of representing the abstract of certain form " reference platform " or typical realization.
Can use abstraction process to set up the simplified model of this test wire harness.This technology allows to handle than piece being embedded into the check faster of testing in the complete fiducial chip design.On the contrary, abstract model can be more accurate than typical test wire harness, and the test wire harness does not comprise other thing except one group of simple timing restriction, typical pin load and signal waveform.
The shell of related physical geometry size that this " contrary " abstract to look like a logic and be positioned at the outside, border of this piece.Except carrying out on father's piece and pin begins across the interface pin from sub-piece rather than primary input, output and the power pins of uncle's piece begin, can utilize identical abstract algorithm to make up it.
Figure 13 illustrates a computer system that can realize one or more embodiment of the present invention.Computer system 1310 is shown, and it can be any universal or special calculating or data processor, for example can be for a PC personal computer that is connected to network 1300 with selecting.The storer 1311 of computer system 1310 may be not enough to the whole contents of holding circuit design or its input, thereby may need hierarchically to decompose this design process.In this manner, can be with each and the various piece of computer system 1310 similar several different computer system processor overall designs wherein.When doing like this, extracting the abstract model of the piece and the design of sub-piece (module and submodule) must be uniformly and the various processing of consistent application such as timing analysis, place and route and budget.The present invention as the definition of front, attempts solving the abstract problem in the hierarchical Design.
The insider can be to computer system 1310 programmings, to finish the abstract and submodule design objective of narrating in various embodiments of the present invention.Can utilize such as the processor 1312 of CPU (CPU (central processing unit)) and such as the storer 1311 of RAM (random access memory) and carry out this program code, wherein this storer is used to store/pack into required instruction, address and result data.(a plurality of) that are used for finishing the various functions of abstract and submodule design use and can produce from using the executable file such as the compilation of source code of the language compilation of C++.Can be encased in this executable file in the storer 1311 and and carry out its instruction by processor 1312.The instruction of this executable file (they and finish abstract required instruction correspondence) can be stored in dish 1318, for example floppy drive, hard disk driver or CD-ROM drive 1317 or the storer 1311.Various inputs, for example net table (group), restriction, processing feature, cell library and other this information, can by the form of database and/or platform file to coil 1318, CD-ROM drive 1317 even write/visit by network 1300.
Computer system 1310 has and promotes right/system bus 1313 of transmitting from processor 1312 and storer 1311 information and have the bridge 1314 that is connected with I/O bus 1315.I/O bus 1315 is various I/O parts, and for example network interface unit (NIC) 1316, dish 1318 and CD-ROM drive 1317 are connected to system storage 1311 and processor 1312.The present invention can adopt the combination of various I/O parts, bus and bridge, and the combination shown in this is a kind of example of possible combination.
The present invention has been described being inconjunction with under the preferred embodiment above; But this only provides for illustrational purpose, and the present invention is not subjected to this restriction.In fact, various modification of the present invention is significantly and also within the scope of the invention for the insider.
Claims (78)
1. method of in producing integrated circuit (IC) design, using, described circuit design has unit and interconnection, described circuit is decomposed into a top layer and a plurality of expression with having a kind of level, the piece of at least a portion in described a plurality of can and have father's piece of an association by further Hiberarchy Decomposition, and described method comprises:
Thereby at least one in handling described set up abstract, this is abstract comprise and described at least one piece in each assembly between the relevant physical interconnections information of interconnection, according to of parasitic electrical and the physical influence modeling of the described physical interconnections information of the estimation behavior of described integrated circuit to interconnection; And
In other development phase of realizing described father's piece, utilize described abstract.
2. according to the process of claim 1 wherein that described processing comprises:
Only keep the physics that only influences described father's piece in all described physical interconnections information and the subclass of electric behavior; And
The subset of cells that only keeps the logic behavior of the described father's piece of influence.
3. according to the method for claim 2, wherein utilize to comprise:
Substitute the description of described at least one piece with described abstract description.
4. according to the method for claim 2, wherein keep subclass and comprise:
Determine the content of the net table of described at least one piece.
5. according to the method for claim 4, wherein pass through:
The deal with data input;
Handle output; And
The processing clock input;
Determine the described content of the net table of described at least one piece.
6. according to the method for claim 5, wherein the deal with data input comprises:
Set up the primary input tabulation.
7. according to the method for claim 6, wherein before described tabulation is sky to each pin that runs into:
From described tabulation, take out the described pin that runs into;
If the pin of described taking-up is the clock pin, then skips the pin of described taking-up and continue next pin; And
If the pin of described taking-up is not the clock pin, then forward is handled the pin of described taking-up.
8. according to the method for claim 7, wherein the forward pin of handling described taking-up comprises:
Set up succession's tabulation.
9. method according to Claim 8, wherein described succession's tabulation for before the sky to each pin that runs into:
From described succession's tabulation, take out the described follow-up pin that runs into;
The unit of the follow-up pin of described taking-up is labeled as timing unit;
If the follow-up pin of described taking-up is the clock pin, skip the follow-up pin of described taking-up; And
If the follow-up pin of described taking-up is not the clock pin, check whether the follow-up pin of described taking-up is a unit input.
10. according to the method for claim 9, if wherein the follow-up pin of described taking-up is the unit pin:
Whether the follow-up pin of checking described taking-up has the follow-up unit more than;
If described follow-up unit has the follow-up unit more than, then described follow-up unit is labeled as the multiple driver load unit, and recursively carries out the pin that described forward is handled described taking-up.
11. according to the method for claim 10, wherein:
If the follow-up pin of described taking-up is not the unit input; Perhaps
If the follow-up pin of described taking-up does not have the follow-up unit more than, then recursively carry out the pin that described forward is handled described taking-up.
12., wherein handle output and comprise according to the method for claim 5:
Set up a main output listing.
13. according to the method for claim 12, wherein before described tabulation is sky, to each pin that runs into:
Take out the described pin that runs into from described tabulation;
The pin of the described taking-up of reverse process.
14. according to the method for claim 13, wherein the pin of the described taking-up of reverse process comprises:
Set up forerunner's tabulation.
15. according to the method for claim 14, wherein in described forerunner tabulation for before the sky, to each pin that runs into:
Tabulate from described forerunner and to take out the described pin in advance that runs into;
The unit of pin in advance of described taking-up is labeled as timing unit;
If the pin in advance of described taking-up is the clock pin, skip the pin in advance of described taking-up; And
If the pin in advance of described taking-up is not the clock pin, check whether the pin in advance of described taking-up is a unit output.
16. according to the method for claim 15, if wherein the pin in advance of described taking-up is unit output:
Follow-up unit is labeled as the remittance load unit; And
Recursively carry out the pin of the described taking-up of described reverse process.
17. according to the method for claim 15, wherein:
If the follow-up pin of described taking-up is not unit output, the pin that then recursively carries out the described taking-up of described reverse process.
18. according to the method for claim 5, wherein the processing clock input comprises:
Set up a major clock input tabulation.
19. according to the method for claim 18, wherein before described tabulation is sky, to each pin that runs into:
Take out the described pin that runs into from described tabulation;
Forward is handled the clock pin of described taking-up.
20. according to the method for claim 19, wherein the forward pin of handling described taking-up comprises:
Set up succession's tabulation.
21. according to the method for claim 20, wherein said succession tabulation is for before the sky, for each pin that runs into:
Tabulate from described succession and to take out the described follow-up pin that runs into;
If the follow-up pin of described taking-up is the clock pin, recursively forward is handled the follow-up pin of described taking-up; And
If the follow-up pin of described taking-up is not the clock pin, then skip the follow-up pin of described taking-up.
22. according to the method for claim 21, wherein recursively forward is handled after the follow-up pin of described taking-up:
Check whether any follow-up unit is labeled as timing unit.
23. according to the method for claim 22, if wherein any follow-up unit is labeled as timing unit;
The unit of the follow-up pin of described taking-up is labeled as timing unit; And
Described follow-up unit is labeled as the clock load unit.
24. according to the method for claim 22, if wherein follow-up unit all unmarked be timing unit, skip the follow-up pin of described taking-up.
25. according to the process of claim 1 wherein of physics and the electrical effect modeling of described physical interconnections information to circuit layout and manufacture process.
26. method according to claim 25, wherein said physics and electrical effect comprise at least one in following: the place and route restriction, antenna effect, have the static timing analysis that RC postpones modeling, have the static timing analysis that capacitive coupling and noise inject, have the static timing analysis and the electromigration analysis of IR pressure drop modeling.
27. according to the method for claim 26, wherein utilize the border of described at least one piece physical size, allow the physical location that the pin to described at least one piece connects and be used for finishing one or more place and route effect modelings among each layer of connection of described permission described at least one piece.
28. according to the method for claim 26, wherein by in described all diodes, transistor gate and the transistor source/drain electrode that comprises all pin leads that are connected with each pin on electric in abstract and be connected with these pins through these leads to the antenna effect modeling.
29. method according to claim 26, wherein by being connected to the lead that the pin leads of primary input/output pin of this piece and each bar are realized all the pin network that is connected with unit in this timing shell, to the modeling of the capacitance-resistance during the static timing analysis (RC) interconnect delay at described each bar that comprises in abstract.
30. according to the method for claim 29, wherein by described comprise in abstract each bar potentially can with the sidewall coupling modeling of the capacitively coupled coupled-wires of each bar pin leads during to static timing analysis.
31. according to the method for claim 29, wherein: by comprising in abstract described:
A) all on the coupling network potentially can with the capacitively coupled lead of each bar pin leads,
B) each drives coupling unit and each coupling unit by these network-driven of these networks, wherein utilizes the input pin modeling to driver element of emulation obtains to piece due in and conversion value, and
C) the transmission lead of each bar coupling network coupling that can comprise with described potentially,
In at least one group the noise that causes because of capacitive coupling during the static timing analysis injected and postpone to change modeling.
32. according to the method for claim 29, wherein by comprising in abstract described:
A) all on the coupling network potentially can with the capacitively coupled lead of each bar pin leads,
B) each drives coupling unit and each coupling unit by these network-driven of these networks, wherein by comprise whole combinational logic cone (up to and comprise first latch or the trigger that drives these networks) and these networks on all leads that are connected with pin on the described extra cell to the input pin modeling of driver element, and
C) each bar potentially can with the transmission lead of described " coupling " network coupled that comprises,
In at least one group the noise that causes because of capacitive coupling during the static timing analysis injected and postpone to change modeling.
33. according to the method for claim 26, the simplification electric model that wherein utilizes piece is to the modeling of IR pressure drop effect, wherein each pin is modeled as desirable electric current and converges (leakages)/source, and with the impedance matrix of being correlated with to its inside RC network modeling.
34., wherein be that the required identical information of electric power network utilization and power supply decline effect is to the electromigration effect modeling according to the method for claim 33.
35., wherein be that the required identical information of signal network utilization and static timing analysis is to the electromigration effect modeling according to the method for claim 30.
36. a design has the method for the integrated circuit of unit and interconnection, is broken down into a top layer and a plurality of described circuit level, described can be decomposed by level further, and described method comprises:
Thereby handle described a piece father's piece and any with mass set up one contrary abstract, should be contrary abstractly comprise described father and with the physical interconnections information between each assembly in the mass, according to of the electric and physics ghost effect modeling of the described physical interconnections information of the behavior of described integrated circuit to interconnection; And
In at least one stage of designing and analyzing a described piece, utilize described contrary abstract.
37. according to the method for claim 36, the wherein said stage comprises at least one in following: static timing analysis, noise analysis, power supply analysis, the IR pressure drawdown analysis, the electromigration analysis, the antenna rule violation detects and repairs, place and route is realized, design and check.
38., wherein utilize a uniform data model integrated to the described stage more than one according to the method for claim 37.
39. goods that comprise computer-readable medium, described computer-readable medium has the instruction group that is used for realizing a kind of method of using in producing integrated circuit (IC) design of storage thereon, described circuit has unit and interconnection, described circuit is decomposed into a top layer and a plurality of expression with having a kind of level, the piece of at least a portion in described a plurality of can further be decomposed and have father's piece of an association by level, described instruction causes when carrying out:
Thereby at least one in handling described set up abstract, this is abstract comprise and described at least one piece in each assembly between the relevant physical interconnections information of interconnection, according to of the electric and physics ghost effect modeling of the described physical interconnections information of the estimation behavior of described integrated circuit to interconnection; And
In other development phase of realizing described father's piece, utilize described abstract.
40. according to the goods of claim 39, wherein said processing comprises:
Only keep the physics of the described father's piece of influence in all physics interconnect information and the subclass of electric behavior; And
The subset of cells that only keeps the logic behavior of the described father's piece of influence.
41., wherein utilize to comprise according to the goods of claim 39:
Substitute the description of described at least one piece with described abstract description.
42., wherein keep subclass and comprise according to the goods of claim 40:
Determine the content of the net table of described at least one piece.
43. the goods according to claim 42 wherein pass through:
The deal with data input;
Handle output; And
The processing clock input;
Determine the described content of logical shell.
44. according to the goods of claim 43, wherein the deal with data input comprises:
Set up the primary input tabulation.
45. according to the goods of claim 44, wherein before described tabulation is sky to each pin that runs into:
From described tabulation, take out the described pin that runs into;
If the pin of described taking-up is the clock pin, then skips the pin of described taking-up and continue next pin; And
If the pin of described taking-up is not the clock pin, then forward is handled the pin of described taking-up.
46. according to the goods of claim 45, wherein the forward pin of handling described taking-up comprises:
Set up succession's tabulation.
47. according to the goods of claim 46, wherein described succession tabulation for before the sky to each pin that runs into:
From described succession's tabulation, take out the described follow-up pin that runs into;
The unit of the follow-up pin of described taking-up is labeled as timing unit;
If the follow-up pin of described taking-up is the clock pin, skip the follow-up pin of described taking-up; And
If the follow-up pin of described taking-up is not the clock pin, check whether the follow-up pin of described taking-up is a unit input.
48. according to the goods of claim 47, if wherein the follow-up pin of described taking-up is the unit input:
Whether the follow-up pin of checking described taking-up has the follow-up unit more than;
If described follow-up unit has the follow-up unit more than, then described follow-up unit is labeled as the multiple driver load unit, and recursively carries out the pin that described forward is handled described taking-up.
49. according to the goods of claim 48, wherein:
If the follow-up pin of described taking-up is not the unit input; Perhaps
If the follow-up pin of described taking-up does not have the follow-up unit more than, then recursively carry out the pin that described forward is handled described taking-up.
50., wherein handle output and comprise according to the goods of claim 43:
Set up a main output listing.
51. according to the goods of claim 50, wherein before described tabulation is sky, to each pin that runs into:
Take out the described pin that runs into from described tabulation;
The pin of the described taking-up of reverse process.
52. according to the goods of claim 51, wherein the pin of the described taking-up of reverse process comprises:
Set up forerunner's tabulation.
53. according to the goods of claim 52, wherein in described forerunner tabulation for before the sky, to each pin that runs into:
Tabulate from described forerunner and to take out the described pin in advance that runs into;
The unit of pin in advance of described taking-up is labeled as timing unit;
If the pin in advance of described taking-up is the clock pin, skip the pin in advance of described taking-up; And
If the pin in advance of described taking-up is not the clock pin, check whether the pin in advance of described taking-up is a unit output.
54. according to the goods of claim 53, if wherein the pin in advance of described taking-up is unit output:
Follow-up unit is labeled as the remittance load unit; And
Recursively carry out the pin of the described taking-up of described reverse process.
55. according to the goods of claim 53, wherein:
If the follow-up pin of described taking-up is not unit output, the pin that then recursively carries out the described taking-up of described reverse process.
56. according to the goods of claim 43, wherein the processing clock input comprises:
Set up a major clock input tabulation.
57. according to the goods of claim 56, wherein before described tabulation is sky, to each pin that runs into:
Take out the described pin that runs into from described tabulation;
Forward is handled the clock pin of described taking-up.
58. according to the goods of claim 57, wherein the forward pin of handling described taking-up comprises:
Set up succession's tabulation.
59. according to the goods of claim 58, wherein said succession tabulation is for before the sky, for each pin that runs into:
Tabulate from described succession and to take out the described follow-up pin that runs into;
If the follow-up pin of described taking-up is the clock pin, recursively forward is handled the follow-up pin of described taking-up; And
If the follow-up pin of described taking-up is not the clock pin, then skip the follow-up pin of described taking-up.
60. according to the goods of claim 59, wherein recursively forward is handled after the follow-up pin of described taking-up:
Check whether any follow-up unit is labeled as timing unit.
61. according to the goods of claim 60, if wherein any follow-up unit is labeled as timing unit;
The unit of the follow-up pin of described taking-up is labeled as timing unit; And
Described follow-up unit is labeled as the clock load unit.
62. according to the goods of claim 60, if wherein follow-up unit all unmarked be timing unit, skip the follow-up pin of described taking-up.
63. according to the goods of claim 39, wherein said physical interconnections information comprises the physical influence of circuit layout and manufacture process.
64. goods according to claim 63, wherein said physical influence comprises at least one in following: the place and route restriction, antenna effect, have the static timing analysis that RC postpones modeling, have the static timing analysis that capacitive coupling and noise inject, have the static timing analysis and the electromigration analysis of IR pressure drop modeling.
65. according to the goods of claim 64, wherein utilize the border of described at least one piece physical size, allow the physical location that the pin to described at least one piece connects and be used for finishing one or more place and route effect modelings among each layer of connection of described permission described at least one piece.
66. according to the goods of claim 64, wherein by in described all diodes, transistor gate and the transistor source/drain electrode that comprises all pin leads that are connected with each pin on electric in abstract and be connected with these pins through these leads to the antenna effect modeling.
67. according to the goods of claim 64, wherein by being connected to capacitance-resistance (RC) the interconnect delay modeling during to static timing analysis of lead that the pin leads of primary input/output pin of this piece and each bar realize all the pin network that is connected with unit in this timing shell at described each bar that comprises in abstract.
68. according to the goods of claim 67, wherein by described comprise in abstract each bar potentially can with the sidewall coupling analysis modeling of the capacitively coupled coupled-wires of each bar pin leads during to static timing analysis.
69. according to the goods of claim 67, wherein: by comprising in abstract described:
A) all on the coupling network potentially can with the capacitively coupled lead of each bar pin leads,
B) each drives coupling unit and each coupling unit by these network-driven of these networks, wherein utilizes the input pin modeling to driver element of emulation obtains to piece due in and conversion value, and
C) the transmission lead of each bar coupling network coupling that can comprise with described potentially,
In at least one group the noise that causes because of capacitive coupling during the static timing analysis injected and postpone to change modeling.
70. according to the goods of claim 67, wherein by comprising in abstract described:
A) all on the coupling network potentially can with the capacitively coupled lead of each bar pin leads,
B) each drives coupling unit and each coupling unit by these network-driven of these networks, wherein by comprise whole combinational logic cone (up to and comprise first latch or the trigger that drives these networks) and these networks on all leads that are connected with pin on the described extra cell to the input pin modeling of driver element, and
C) each bar potentially can with the transmission lead of described " coupling " network coupled that comprises,
In at least one group the noise that causes because of capacitive coupling during the static timing analysis injected and postpone to change modeling.
71. according to the goods of claim 64, the simplification electric model that wherein utilizes piece is to the modeling of IR pressure drop effect, wherein each pin is modeled as desirable electric current and converges (leakages)/source, and with the impedance matrix of being correlated with to its inside RC network modeling.
72., wherein be that the required identical information of electric power network utilization and power supply decline effect is to the electromigration effect modeling according to the goods of claim 71.
73., wherein be that the required identical information of signal network utilization and static timing analysis is to the electromigration effect modeling according to the goods of claim 68.
74. one kind comprises the computer-readable medium goods, what described computer-readable medium had thereon a storage has the instruction group that realizes in the method for integrated circuit of unit and interconnection in a kind of design, described circuit by level resolve into a top layer and a plurality of, described can be decomposed by level further, and described instruction causes when carrying out:
Thereby handle described a piece father's piece and any with mass set up one contrary abstract, should be contrary abstractly comprise described father and with the physical interconnections information between each assembly in the mass, according to of the electric and physics ghost effect modeling of the described physical interconnections information of the behavior of described integrated circuit to interconnection; And
In at least one stage of designing and analyzing a described piece, utilize described contrary abstract.
75. according to the goods of claim 74, the wherein said stage comprises at least one in following: static timing analysis, noise analysis, power supply analysis, the IR pressure drawdown analysis, the electromigration analysis, the antenna rule violation detects and repairs, place and route is realized, design and check.
76., wherein utilize a uniform data model integrated to the described stage more than one according to the goods of claim 75.
77. according to the process of claim 1 wherein described interconnection comprise described at least one piece and the expression of the interface between his father's piece.
78. according to the goods of claim 39, wherein said interconnection comprise described at least one piece and the expression of the interface between his father's piece.
Applications Claiming Priority (2)
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|---|---|---|---|
| US29679701P | 2001-06-08 | 2001-06-08 | |
| US60/296,797 | 2001-06-08 |
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| CN1539113A true CN1539113A (en) | 2004-10-20 |
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| CNA028152786A Pending CN1539113A (en) | 2001-06-08 | 2002-06-10 | Representing design of sub-module in hierarchical integrated circuit design and analysis system |
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| EP (1) | EP1407391A2 (en) |
| JP (1) | JP2005518002A (en) |
| KR (1) | KR20040032109A (en) |
| CN (1) | CN1539113A (en) |
| CA (1) | CA2450143A1 (en) |
| IL (1) | IL159224A0 (en) |
| WO (1) | WO2002101601A2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461189C (en) * | 2005-01-21 | 2009-02-11 | 国际商业机器公司 | Circuit design method and system |
| CN102160055B (en) * | 2009-07-28 | 2014-03-12 | 新诺普系统公司 | Hierarchical order ranked simulation of electronic circuits |
| CN103678760A (en) * | 2012-09-21 | 2014-03-26 | 波音公司 | Displaying modeling data and logical data |
| CN105612520A (en) * | 2013-08-06 | 2016-05-25 | Ess技术有限公司 | Constrained placement of connected elements |
| CN106777441A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | Temporal constraint management method and device |
| CN107797051A (en) * | 2016-08-30 | 2018-03-13 | 联发科技股份有限公司 | The circuit modeling approach and automatic test pattern generative circuit of automatic test pattern generation |
| CN112395431A (en) * | 2021-01-18 | 2021-02-23 | 北京晶未科技有限公司 | Method for constructing behavior model, electronic device and electronic equipment |
| CN113642280A (en) * | 2020-04-27 | 2021-11-12 | 中国科学院上海微系统与信息技术研究所 | Layout method of superconducting integrated circuit |
| CN117436379A (en) * | 2023-12-21 | 2024-01-23 | 成都行芯科技有限公司 | Through hole compression method and device, electronic equipment and storage medium |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100382085C (en) * | 2004-07-07 | 2008-04-16 | 华为技术有限公司 | Board pattern designing method of integrated designing element in printed circuit board and its device |
| WO2007002799A1 (en) * | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
| US7752588B2 (en) | 2005-06-29 | 2010-07-06 | Subhasis Bose | Timing driven force directed placement flow |
| US8332793B2 (en) | 2006-05-18 | 2012-12-11 | Otrsotech, Llc | Methods and systems for placement and routing |
| US7840927B1 (en) | 2006-12-08 | 2010-11-23 | Harold Wallace Dozier | Mutable cells for use in integrated circuits |
| CN102339342B (en) * | 2010-07-27 | 2013-06-05 | 中国科学院微电子研究所 | Quick materialization method of parameterized device unit |
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| US5598344A (en) * | 1990-04-06 | 1997-01-28 | Lsi Logic Corporation | Method and system for creating, validating, and scaling structural description of electronic device |
| US5644498A (en) * | 1995-01-25 | 1997-07-01 | Lsi Logic Corporation | Timing shell generation through netlist reduction |
| US5844818A (en) * | 1996-05-10 | 1998-12-01 | Lsi Logic Corporation | Method for creating and using design shells for integrated circuit designs |
| US5920484A (en) * | 1996-12-02 | 1999-07-06 | Motorola Inc. | Method for generating a reduced order model of an electronic circuit |
| US5878053A (en) * | 1997-06-09 | 1999-03-02 | Synopsys, Inc. | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs |
| US6072945A (en) * | 1997-06-26 | 2000-06-06 | Sun Microsystems Inc. | System for automated electromigration verification |
| US6457159B1 (en) * | 1998-12-29 | 2002-09-24 | Cadence Design Systems, Inc. | Functional timing analysis for characterization of virtual component blocks |
-
2002
- 2002-06-10 KR KR10-2003-7016097A patent/KR20040032109A/en not_active Application Discontinuation
- 2002-06-10 IL IL15922402A patent/IL159224A0/en unknown
- 2002-06-10 CN CNA028152786A patent/CN1539113A/en active Pending
- 2002-06-10 WO PCT/US2002/018424 patent/WO2002101601A2/en active Application Filing
- 2002-06-10 EP EP02739817A patent/EP1407391A2/en not_active Withdrawn
- 2002-06-10 JP JP2003504290A patent/JP2005518002A/en active Pending
- 2002-06-10 CA CA002450143A patent/CA2450143A1/en not_active Abandoned
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461189C (en) * | 2005-01-21 | 2009-02-11 | 国际商业机器公司 | Circuit design method and system |
| CN102160055B (en) * | 2009-07-28 | 2014-03-12 | 新诺普系统公司 | Hierarchical order ranked simulation of electronic circuits |
| CN103678760A (en) * | 2012-09-21 | 2014-03-26 | 波音公司 | Displaying modeling data and logical data |
| CN103678760B (en) * | 2012-09-21 | 2018-06-05 | 波音公司 | The display of modeling data and logical data |
| CN105612520A (en) * | 2013-08-06 | 2016-05-25 | Ess技术有限公司 | Constrained placement of connected elements |
| CN106777441A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | Temporal constraint management method and device |
| CN106777441B (en) * | 2015-11-24 | 2020-04-21 | 龙芯中科技术有限公司 | Timing constraint management method and device |
| CN107797051A (en) * | 2016-08-30 | 2018-03-13 | 联发科技股份有限公司 | The circuit modeling approach and automatic test pattern generative circuit of automatic test pattern generation |
| CN113642280A (en) * | 2020-04-27 | 2021-11-12 | 中国科学院上海微系统与信息技术研究所 | Layout method of superconducting integrated circuit |
| CN112395431A (en) * | 2021-01-18 | 2021-02-23 | 北京晶未科技有限公司 | Method for constructing behavior model, electronic device and electronic equipment |
| CN117436379A (en) * | 2023-12-21 | 2024-01-23 | 成都行芯科技有限公司 | Through hole compression method and device, electronic equipment and storage medium |
| CN117436379B (en) * | 2023-12-21 | 2024-04-09 | 成都行芯科技有限公司 | Through hole compression method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040032109A (en) | 2004-04-14 |
| WO2002101601A2 (en) | 2002-12-19 |
| EP1407391A2 (en) | 2004-04-14 |
| CA2450143A1 (en) | 2002-12-19 |
| WO2002101601A3 (en) | 2003-12-11 |
| JP2005518002A (en) | 2005-06-16 |
| IL159224A0 (en) | 2004-06-01 |
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