KR20040032109A - Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system - Google Patents

Abstract

A class that utilizes block abstractions containing within it a set of all database objects (cells, nets, wires, biases, and blockages) required to achieve accurate placement, routing, extraction, simulation, and verification of blocks in the hierarchy. How to model integrated circuit designs in design automation systems.

Description

REPRESENTING THE DESIGN OF A SUB-MODULE IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN AND ANALYSIS SYSTEM}

In an electronic computer aided design (ECAD) software system, integrated circuit design specifications and implementation data must be stored as a set of database records, which records some finite amount based on the virtual memory capacity of the computer on which the software is running. Has a maximum size. In addition, the execution time of the ECAD software usually increases with the design size. Data representing very large integrated circuit designs may be too large to fit in the memory of a computer, or the execution time required to simulate a design or the entire design is enormous. This is particularly true in that the number of components (ie, gates) and the attendant connections in the integrated circuit are within tens or hundreds of millions or more.

Hierarchical decomposition or "partitioning" is a technique that can be used to reduce the complexity of large integrated circuit design specifications in order to maintain controllable memory and / or runtime required to complete the design. to be. Instead of representing the design as a single flat database, the design can be divided into pieces, often referred to as "blocks," and can be designed or verified independently. With a single level of hierarchy, the design specification consists of a set of blocks and top-level interconnections between those blocks. With multiple levels of hierarchy, blocks can themselves be made up of smaller sub-blocks and the interconnection of the sub-blocks.

Hierarchical decomposition can also be used simply as an organizational tool by the design team as a way to partition design projects among multiple designers. However, this logical layer created by the design team in the design specification does not have to be identical to the physical layer used to partition the design for implementation. Often the logical layer is much deeper than the physical layer. The block flattening process can be used to convert the logical layer into an appropriate physical layer.

Conventional hierarchical design projects typically proceed in two main stages: the top-down block planning step after the bottom-up verification step. If the block itself is implemented during the top-down phase (ie, each block is implemented before its children), the flowchart is referred to as a top-down flowchart. Conversely, if a block is implemented during the bottom-up phase (ie, each block is implemented after all the child blocks of the block are completed), the flowchart is referred to as the bottom-up flowchart. Top-down and bottom-up flowcharts have advantages and disadvantages, respectively. Without loss of generality, top-down flowcharts are used as examples in the remainder of this specification. Bottom-up flowcharts may be implemented using the same technique.

Figure 1 shows a general top-down block plan and implementation flowchart. Beginning to divide the design net list (map) to map the logical layer to the physical layer, a top-level block and a set of implemented sub-blocks are defined (S110). Then, the width and height values and the placement in the floor plan are assigned to each sub-block (S115). The location is then assigned to a pin on each sub-block that indicates the location where the net crosses the sub-block boundary (S120). After this step, a time budgeting step is followed by assigning the time constraint required for signal arrival / request to each sub-block pin indicating that a portion of the clock cycle is assigned to the timing path crossing the sub-block boundary. Follow (S135).

At this point in the top-down flowchart, after the top-level block is planned, the process prepares to implement the block. A batch is allocated to all leaf-cells (standard cells or macros) owned by the block, and all nets owned by the block are routed (S140). If any nets are routed across sub-blocks (so-called "feedthrough nets"), these wires are pushed down to sub-blocks that overlap them, and new pins A sub-block intersecting the sub-block boundary is generated (S145). Thereafter, the sub-block is cyclically implemented according to the same process (S150). This involves treating each sub-block as a top-level block, while at the same time carrying out recursive implementation steps 110-170.

For the above process, to successfully complete the shape, pin location, and timing budget assigned to each block S115-135, the constraints that can be achieved must be represented. Otherwise, the system may not be able to complete the implementation of some blocks according to their specifications. In this case, the specification may need to be redefined, and the top-down process may need to be repeated before the correct implementation can be realized. Therefore, how to achieve high quality results at these steps is important statically.

When the circular top-down planning and implementation phase is complete, the bottom-up verification process can begin. In the procedure from the lowest-level block to the top-level, each block is independently interpreted for timing, electrical performance, as well as logical accuracy, and compared against a specification (S155). After all sub-blocks of the block are independently verified, the block itself may be interpreted under the assumption that the sub-blocks are correct (S170).

The present invention relates to the manufacture of electronic circuits. More particularly, the present invention relates to a system for designing and verifying the content and layout of integrated circuits.

1 is a diagram illustrating a general top-down block plan and implementation flowchart;

2 illustrates a hierarchical design process according to one or more embodiments of the present invention;

3 illustrates an abstract process in accordance with one or more embodiments of the present invention;

4 illustrates a logical shell labeling process in accordance with one or more embodiments of the present invention;

5 shows a block undergoing the labeling process;

6 is a summary diagram of the process data input step of FIG. 4;

7 is a summary diagram of the process pin forward step of FIG. 6;

8 is a summary diagram of the process output step of FIG. 4;

9 is a summary diagram of the process pin backward step shown in FIG. 8;

10 is a summary diagram of the process clock input step of FIG. 4;

11 is a summary diagram of the process clock pin forward step shown in FIG. 10;

12 illustrates a physical timing shell model of one embodiment of the present invention;

13 illustrates an example computer system that may implement and apply one or more embodiments of the present invention.

In various embodiments, the present invention consists in the creation and use of a reduced model, referred to as a block “abstraction,” wherein the abstraction is linked to a parent block and the structure of the block in which sibling blocks can be correctly interpreted and Capture the action in sufficient detail. The purpose of the abstraction is to reduce the total amount of memory required to represent a block as an ancestor of the block in the hierarchy, and the total amount of execution time required to interpret each example of the block in relation to its parent and sibling blocks. To reduce.

One method of implementing the top-down hierarchical design process is the hierarchical design flow chart shown and described in FIG. The design flow chart shown in FIG. 2 is a breakdown of the top-down flow chart shown in FIG. 1, with three additional steps 230, 260, and 265. The granularity considers not only the bottom-up verification step, but also the method of modeling the sub-blocks in relation to their parent and sibling blocks during the top-down budget and block implementation steps. These steps represent locations in the flowchart where clean hierarchical boundaries are violated, and cross-boundary analysis is required. Without the effective engineering to manage this cross-boundary analysis, one may lose the main advantage of the hierarchical design process (its ability to reduce the runtime and memory required to design large integrated circuits).

In the top-down budgeting step, one purpose is to interpret a combinational logic path that crosses one or more hierarchical boundaries, and determine which portion of the clock cycle should be budgeted for each segment of the path.

In the top-down block implementation phase, a block is located and routed before its sub-blocks are implemented. In most cases, placement and routing are evenly decoupled across hierarchical boundaries. Many modern manufacturing processes, however, require routing wires to follow a set of rules called "antenna rules" that require detailed knowledge of the routing wires that exist on both sides of the hierarchical boundary.

In the bottom-up verification process, it is also necessary to resolve the combined logic paths that cross hierarchical boundaries. When interpreting a block comprising sub-blocks, it is desirable to take advantage of the fact that the sub-blocks are pre-verified, while avoiding the need to reinterpret the sub-blocks while interpreting their parents.

To this end, certain embodiments of the present invention are reduced, termed block " abstract ", to capture the operation and structure of a block of sufficient detail that its parent block and its sibling blocks can be correctly interpreted. Start using the model. The goal of the abstraction is to reduce the amount of memory needed to represent a block for that ancestor in the hierarchy, and to reduce the total amount of execution time needed to interpret each case of the block in relation to its parent and sibling blocks.

As discussed above, in this regard, the hierarchical design flow chart of FIG. 1 is supplemented and enhanced by additional steps 230, 260, 265. In step 230, prior to the time budgeting step, the abstractions of each sub-block are created for use in budgeting. Since the sub-block has not yet been implemented, it does not contain any physical implementation data, only its netlist description. Thus, the abstraction used in budgeting is intended to model only the logical operation of the sub-blocks, and the details of the physical and electrical operations are not yet available. This initial abstraction is used at budgeting and then discarded.

After time budgeting, placement and routing, wire pushdown, block implementation, and block verification (S235, 240, 245, 250, and 255), a second abstract for each block is generated (S260). As soon as the current block implementation is completed, the abstraction must model physical and electrical details as well as logical operation.

Because the verification process occurs bottom-up, all child blocks of the block are verified independently before the block itself is verified. Upon verification of the block, all sub-blocks of the block are replaced by an abstraction of the sub-block, for example, utilizing the fact that most of the implementation and operation of the sub-block has already been verified (S265). Only these combinatorial logic paths that cross hierarchical boundaries remain unvalidated. The data reduction provided by the abstraction will significantly increase the block's verification efficiency and reduce the memory requirements while rising through the hierarchy.

While steps 210, 215, and 220 are similar to the operations of blocks 110, 115, and 120, respectively, all other steps 230-270 are improved when dealing with the abstraction of the design than the raw design itself in this step.

One key difference between the top-down block implementation flow chart and the bottom-up block implementation flow chart is that blocks are implemented before their child blocks in the former, while blocks are implemented after their child blocks in the latter. The hierarchical implementation flowchart of FIG. 2 is modified to place blocks 240 and 245 between blocks 265 and 270. The main effect is that in the top-down flowchart, the top-level block is implemented before the implementation of its child block is completed. Accordingly, the present invention is to implement sub-block budgets as an ideal optimal target while implementing their parent block. On the other hand, in a bottom-up flowchart, a block must be implemented before the implementation of its parent or sibling block is known. Therefore, the timing budget should also be used as an ideal optimum target.

The abstract apparatus described above can be equally applied when used in a bottom-up implementation and a verification flowchart, just as in a top-down implementation flowchart when verification is performed in a bottom-up. However, in a bottom-up implementation flow chart, the use of abstraction to model a completed sub-block rather than an ideal budget allows the parent block to be implemented with high quality. Described in detail below are "inverse abstraction" devices that enable the same gains realized in top-down flowcharts.

Conventional methods for block abstraction rely on a reduced motion model for capturing similar operational descriptions of the logical, physical, and electrical motion of the block. This is typically represented as a mathematical model associated with each pin. For example, the logical description of each pin can be described with a binary decision diagram (BDD). The electrical description of each pin can be captured in a linearized RC-network which reduces the fixed number of moments. Currently, there is no known method for generating a reduced model of the physical information needed to represent the antenna parameters of the pin. Lack of effective abstraction for this latter application generally requires a constructive antenna avoidance technique that reduces circuit performance, such as diode insertion at each pin.

The use and application of the abstract devices described below all lead to a coherent, unified approach to timing analysis, electrical analysis, placement and routing, and budgeting that depends on each other. In addition, unlike conventional abstract devices according to similar mathematical models, it guarantees perfect precision.

Timing Analysis

Static timing analysis is primarily concerned with calculating the propagation time of the data signal between latch and / or flip-flop. This information is used both for optimization of logic in the parent block and for verification of child block timing in sibling and non-parent relationships. If the combinatorial logic path crosses one or more hierarchical boundaries, an accurate timing interpretation can only be determined when the path information is available for all segments of the path through all levels of the hierarchy. From a static timing point of view, a block abstract exhibits the same timing characteristics at the boundary of a low level block for a high level block, while a high level block cannot tolerate a difference between a reduced model and a complete model. The timing characteristics that must be captured by the low level block are the required times on the primary input pin and the arrival times on the initial output pin.

These two pieces of information can be precomputed if one is known in the stringent operating environment of each block. However, since the verification flow is going to bottom-up, a high level block cannot accurately provide this information. The input slew and output-loading information of the child blocks are not known exactly. Also, information such as timing may be impossible to represent with this simple model.

By constructing a lookup table from multiple interpretations running on low-level blocks with a pre-extracted linear delay model or with varying slew and load values. It is possible to model the slew and rod effects. However, this reduced model will be somewhat inaccurate, not possible to accurately model the interconnect network until the correct driver and receiver location and routing topology has been determined, and not signal-dependent delay or signal coupling. It is not possible to explain the signal coupling (crosstalk delay and noise injection).

Electrical Analysis

Electrical analysis relates to verifying that a block and its individual components will not deviate from idealized electrical properties in operation. Two examples of effects that must be modeled include IR-drop and electromigration.

IR-drops, including voltage drop and ground-bounce supply effects, measure non-ideal behavior on power and ground distribution networks. The wires that mark up the supply distribution network have a non-zero resistance, and large current loads can cause the supply voltage to deviate from a certain range at various points along the wire. This effect can cause unexpected changes in the timing behavior of the circuit, and in extreme cases can lead to complete failure of the circuit in operation.

Electromigration disturbances also result from high current densities in non-ideal resistive wires. However, unlike IR-drops, this disorder causes a physical change rather than an electrical change in the wire. Over the lifetime of integrated circuits, these high currents can generate metal atoms that migrate from their original locations, which can cause short circuits and open circuits that were not present at the time of manufacture.

If the IR-drop interpretation indicates a failure, then the result of the IR-drop can be used as feedback on the power distribution network design. It can also be used to improve the accuracy of the timing interpretation as described above. The results of the electromigration analysis are used to influence the implementation of the circuit itself that requires a change to the circuit netlist or a change in the width (resistance) of the wires used in routing if the electromigration indicates a failure. Can be.

All of these electrical effects require detailed interpretation of the strict voltage and current that can be seen on each wire of the circuit. Depending on the model used to measure and predict failure, this analysis may be a static or average case analysis or may require logic or circuit simulation in a dynamic time-domain. Since the analysis has a static timing analysis, this effect must be modeled in the abstract.

Placement and Routing

Placement deals with how the blocks and sub-blocks are physically placed on the integrated circuit during routing, indicating how the blocks and sub-blocks are interconnected. Physical placement of blocks and routing of block pins requires minimal information about the physical configuration of the block. The pin shape of the block provides a set of legal locations that allow the router to connect to the pins. The remaining internal geometry of the block is usually represented by a greatly reduced set of blockages where routing in the parent block prevents design-rule violations for short circuits and cells and routing within the block. Can be.

However, current deep-submicron manufacturing techniques (those with a minimum feature size of less than about 250 nanometers) add one complex complication to this model. Detection and repair of antenna-rule violations requires knowledge of all transistor gates, sources, and drains connecting these wires, in addition to knowledge of routing wire topologies connecting the gates that drive and receive across hierarchical boundaries. do.

Budgeting

In general, in order to obtain an optimal and achievable budget for the sub-blocks, static timing analysis must be performed on all logic paths crossing the hierarchical boundaries of the blocks. Whether they belong to one of the parent blocks, sub-blocks, and sibling blocks of the sub-blocks in the hierarchy, this interpretation must reach all registers visible from the sub-block pins. One advantage is that all combinatorial paths contained within the sub-block can be ignored, which can significantly reduce the cost of this interpretation.

If the budgeting step is allowed to perform cross-boundary logic optimization as well as static timing analysis, it is possible to implement optimal budget allocation. This technology is disclosed in the pending patent application "Method for Generating Design Constraints for Modules in a Hierarchical Integrated Circuit Design System" of June 10, 2002 (applicant's reference number 054355-0293259).

Block Abstraction Process

As described below, the central aspect of the present invention is a method for block abstraction that achieves the logical and physical data reduction steps required in accordance with the requirements outlined above. The main idea is not to have a simplified mathematical model of reduced accuracy, but to represent the design as a subset of the design data itself. The reduced model consists of a copy of the original model, but does not have all the non-critical information discarded. As another method suggests, the abstraction is created by copying only the elements of the abstract of the logical netlist and physical block implementation required for modeling the block correctly in relation to the parent and sibling blocks in the hierarchy, thus the amount of block data This is greatly reduced.

The remainder of this specification is to model the logical and physical characteristics of a block, including significant physical effects such as antenna rules, resistance-condenser (RC) wire delay, crosstalk, noise injection, IR-drop, and electromigration effects. To this end, the logical netlist object and the physical layout object included in the hierarchical block abstract will be described in detail. These abstractly modeled blocks can be used for top-down budgeting, bottom-up static timing and electrical analysis, as well as either in top-down or bottom-up block implementations with essentially complete accuracy. This level of accuracy can be achieved by selectively maintaining only a subset of the data in each block that cannot be independently interpreted of the parent and / or sibling blocks. Ongoing data may include logical (netlist) data, design constraints, and physical (layout) data. It does not lose its accuracy by including the physical objects themselves instead of the simplified or worst case models for them.

The abstract process can be considered to include the two main steps shown in FIG. First, according to step 310, the logical range of "shells" of the block is determined. This is a set of cells that can be reached along a combined path from the input and output pins of a block that includes a first latch or flip-flop that can meet along each path. The set should also include some additional cells needed to provide accurate capacitive loading information for the previously mentioned cells. Cells that are registers that are fully bounced within a block cannot have any effect on the external timing of the block and therefore are not included in the logical shell. The content of this logical shell is determined by graph traversal and the labeling algorithm discussed in the following paragraphs.

After the content of the logical shell is determined, in step 320 a set of physical shapes that are to be maintained in the abstract are determined. This requires modeling the effects of crosstalk delay and noise injection as well as modeling the resistance and capacitor of the net in the logical shell. As shown below, it may also be necessary to include some additional shell in the logical abstraction to model this effect.

4 is a detailed flowchart of step 310 which is logical shell labeling, in accordance with one or more embodiments of the present invention. The content of the logical shell is determined by an algorithm that labels the nodes of the timing graph of the block. The timing graph has the following information:

(1) netlist (description of how cells are connected to each other)

(2) a cell library (description of how information flows through the cell): and

(3) A direct graph constructed from timing constraints (description of clocks, timing exceptions, and broken edges).

Graph nodes represent cell pins and edges represent nets connecting the pins. In other words, the purpose of the labeling is to preserve only the cells necessary to provide the same timing graph as the shell model present in the entire model when viewed from the first pin.

Logical shell labeling begins with the Dip First Traversal originating from the data (non-clock) first input pin in the logical shell (block 410). Next, a dip first first originating from the first output pin is performed (block 420). Finally, according to block 430, the dips first traversal originating from the clock (non-data) first input pin is performed.

Cells encountered during the DAPs first traversal are labeled according to the following rules (note that one cell is allowed to have more than one label).

1) timing cell:

It is defined as a cell that can be reached from the first input or output pin. Collectively, these cells define a timing graph that is discernible from the first pin.

2) Multi-driver load cell:

It is not itself a timing cell, but is defined as a cell that drives the same net as the timing cell.

3) Sink Load Cell:

If the driving cell is not part of a clock network, it is defined as a cell driven by a timing cell rather than a timing cell itself.

4) Clock Load Cells:

Similar to the sink load cell except the drive cell, it is part of the clock network.

5 is a diagram illustrating a block that goes through this labeling process. In the exemplary block illustrated, the following element is given by input specication. The block includes a primary clock input pin, CLK; It consists of four primary data input pins, CG, IN0, IN1 and IN2; and two primary inputs, OUT0 and OUT1. Cells R1, R2, R3, R4, and R5 are resistor (flip-flop) devices. Components C1, C2, C3, C4 and C5 are any combinational logic circuit (group of connected cells). Cells I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I14 and I14 are examples of separate combinational logic gates.

The cell labeling process is based on being able to identify all cell pins as clock pins or data pins. By identifying, if the pin is not a clock pin, it is a data pin. This labeling is a standard part of any timing analysis algorithm and therefore will not be described herein. According to the static timing algorithm, all the pins on cells I1, I2, I3, I4, I10 and I11 are identified as clock pins. The upper input pin on cell I5 and the output pin on I5 are also identified as clock pins. In addition, the pins attached to the cells R1, R2, R3, R4, and R5 indicated by triangles are labeled as clock pins. This labeling process as applied to the example circuit of FIG. 5 is described below.

Input pin labeling

The labeling process begins with the data (non-clock) primary input. Repetitive depth pulse traversal is performed centered on each such pin in any order. The repetition is encountered when the tree leaves in the graph are met (ie, a pin without a successor, eg, a flip-flop or primary data pin), or terminated if the meeting pin is a clock pin. The cells that meet during each traversal are labeled as timing cells (note that the points in the timing graph are cell pins). Cells with their outputs coupled to the timing cell outputs are labeled as multi-driver load cells. One example of such a multi-driver load cell is a tri-state driver (cells I6 and I7 in FIG. 5).

These processes are summarized in FIGS. 6 and 7. 6 illustrates a process data input step 410 of FIG. 4. This process begins by constructing a list of all primary inputs (block 610) for the circuit and continues until the list is empty (checked at block 620). After the pin is removed from the list (block 630), it is skipped if it is a clock pin (checked at block 640) and continues to be processed with the next pin (again, blocks 620 through 640). If it is not a clock pin (checked at block 640), the main forward processing of the pin occurs at floc 650, which is described in detail in FIG.

The process described in FIG. 7 is a cyclic process in which circulation occurs at block 750. Processing begins by collecting all the successors of the start pin in the list (block 710) and continues until the list is empty (checked in block 715). After the pin is removed from the list (block 720), the cell for the pin is labeled as a "timing" cell (block 725). If the pin is a clock pin, no further processing is required (checked at block 730). If the pin is an input pin (checked at block 735) then it is determined if the pin has at least one preprocessor (checked at block 740). If more than one preprocessor is found (checked at block 740), all preprocessor cells are labeled as "multi-driver load" cells (block 745). The flowchart performs depth-first recursion by calling itself at block 750.

Referring to the example circuit shown in FIG. 5, the input labeling algorithm proceeds as follows. The dips first traversal starts with the input pin INO, meets the component C1 and the register R1, and terminates at the register R1. All cells in component C1 and register R1 included in the traversal are labeled as timing cells. Likewise, all cells and cell I5 in component C2 starting from input CG are also labeled as timing cells. Traversal terminates at I5 because the output of I5 is the clock pin (I5 is a "clock gating" cell). All cells in component C3 starting from input pin IN1 are labeled as timing cells. Cell I6 and register R2 are also labeled as timing cells. Cell I7 is labeled as a multi-driver load because its output is tied to the output of another timing cell. All cells in component C4 starting from input pin IN2 are labeled as timing cells. It is understood that input labeling will be completed at this point.

Output pin labeling

Next, output labeling proceeds in a similar manner using the DAPs first traversal starting at the first output pin. If the leaf pin meets in the graph or if the pin it meets is the clock pin, the cycle is terminated again. Cells that meet along the traversal are then labeled again as timing cells. One of the differences from the input labeling algorithm is that a sync-load cell needs to be identified which is defined as a cell from which a source comes from a timing cell that is not part of the dips first traversal.

The process is summarized in FIGS. 8 and 9. FIG. 8 summarizes the process output step 420 of FIG. The process begins by building a list of all first outputs into the circuit (block 810) and continues until the list is empty (checked in block 820). After the pin is removed from the list (block 830), it proceeds to block 840, which is described in detail in FIG.

The process described in FIG. 9 is a recursive process and the recursion occurs at block 950. Processing begins by collecting all preprocessors of the starting pin in the list (block 910) and continues until the list is empty (checked in block 915). After the pin is removed from the list (block 920), the cell for the pin is labeled as a "timing" cell (block 925). If the pin is a clock pin, no further processing is required (checked at block 930). If the pin is an output pin (checked at block 935), all preprocessors are labeled as "sink load" cells (block 940). The flowchart is cycled by calling itself at block 950.

Referring again to FIG. 5 as an example, all cells in component C5 are labeled as timing cells. Cell I12 and register R3 are also labeled as timing cells. All cells in component C4 are labeled as timing cells. Output labeling is thought to be completed at this point.

Clock Pin Labeling

The final labeling step includes the dips first traversal starting from the first clock input. In this case, the traversal terminates when either the leaf pin of the graph meets or the pin where the pin meets is the data pin. When the traversal ends at the data pin, a check is made to see if the cell on the pin is already labeled as a timing pin. Only when the traversal ends in the cell labeled as the timing cell are cells in the path to the cell labeled as the timing cell. During traversal, cells from timing cells whose source is not labeled as timing cells are marked as clock loads.

This process is summarized in FIGS. 10 and 11. FIG. 10 summarizes the process clock input step 430 of FIG. The process begins by building a list of all first clock inputs into the circuit (block 1010) and continues until the list is empty (checked in block 1020). After the pin is removed from the list (block 1030), it proceeds to block 1040, which is described in detail in FIG.

The process described in FIG. 11 is a recursive process, the recursion occurring at block 1130. The process begins by collecting all the successors of the update pin of the list (block 1110) and continues until the list is empty (checked in block 1115). After the pin is removed from the list (block 1120) a check is made to identify it as a clock (block 1125). If the pin is not a clock pin, no further processing is required (return to block 1115). The flowchart performs the dips first cycle by calling itself at block 1130. Upon returning from the recursive call, a check is made (checked in block 1135) to determine which pin's successors are labeled as "timing" in the recursion. If no successor cell is labeled as a "timing" cell, no further processing is required (return to block 1115). If any successor cell is labeled as a "timing" cell, the cell of the pin is labeled as a "timing" cell (block 1140) and all successor cells are labeled as "clock load" (block 1150). At the end of block 1150, the process ends because the cell of the pin is labeled as a "timing" cell.

Referring again to the example of FIG. 5, the traversal starting from input pin CLK passes through shells I1 and I2 and ends at shells R1, R2 and R3. Thus, shells R1, R2 and R3 are labeled as timing shells. As a result, shells I1 and I2 are also labeled as timing shells because they exist along the traversal path to the timing shell. Traversal through I3 ends in cell R4. R4 cannot reach from either the first input or the first output, but only through its clock pin. Since cell R4 is not a timing cell, I3 is not labeled as a timing cell. However, its source, I1, is labeled as the clock load because it is a timing cell. The same logic applies to cell I4 for R4. I4 is labeled as the clock load. Since traversals through I5 and I11 do not end as timing cells, they are not labeled as timing cells. Cell I5 is usually labeled as clock load, but it has already been labeled as a timing cell at the input CG. Thus, I5 remains as a timing cell.

Labeling Summary:

IN0 First data input IN1 First data input IN2 First data input CG First data input CLK 1st clock input I1 timing I2 timing I3 Clock load I4 Clock load I5 timing I6 timing I7 Multi driver load I8 Unlabeled I9 Mabelling I10 Mabelling I11 timing I12 timing I13 Mabelling I14 Sink rod C1 timing C2 timing C3 timing C4 timing C5 timing R1 timing R2 timing R3 timing R4 Mabelling R5 Mabelling OUT0 First data output OUT2 First data output

After the labeling process is complete, it is possible to determine the set of completed cells that should remain in the logical timing cell. If no cell is labeled in the timing graph, there is no direct impact on the interface timing of the block and it is safe to ignore. These cells are detected by netlists and represented by empty hierarchical blocks called "group" cells. Pins are created on the group cells for every net that crosses its boundary.

False paths and constant propagation

Further reduction in the number of cells labeled as timing cells is achieved through suppression of the application of false paths and continuous propagation. If the timing of the circuit portion has infinite slack, the portion of the circuit is indistinguishable from the first pin. As a result, when the input and output labeling is performed, the pins with infinite slack can be processed leaving in the graph.

This has the advantage of allowing the end user to control the marking as a timing cell through the continued application and to suppress the use of wrong paths.

Path exceptions

Exceptions in the path that affect timing on the first pin apply to the shell model in the same way that the original exceptions apply to the entire model. This is possible because an exception of the path applies to the nodes of the timing graph and all nodes identifiable from the first pin are preserved in the shell model. No effort is needed to rewrite exceptions for some reduced timing graphs. Also, exceptions in the path needed at higher next levels in the hierarchy may be exposed (identifiable) during the shell creation process. This is done by first identifying the constraints that need to be exposed and then rewriting them in such a way that they can be applied if the shell model appears specifically at the next level. In this manner, exceptions to paths that cross hierarchical boundaries can be maintained in a consistent and accurate manner during the design process.

Latch-based designs

In one embodiment of the present invention, a latch-based design creates the same shell model in a flip-flop-based design in terms of how cells are labeled. In addition, in order to reflect the time-borrowing characteristics of the latches, information describing the amount of borrowing for each latch of the shell model is saved. This freezes the borrowing allowed for latches of the shell model, while allowing the next higher level of hierarchy to advantageously utilize time borrowing.

In another embodiment of the present invention, the latch can be processed in the same manner as the combinational logic cell. Only flip-flops are processed leaving the DAPs first traversal, eliminating the need to freeze the amount of time borrowing allowed. However, in the design of pure latch substrates, this results in an abstraction without data reduction.

In a third embodiment of the present invention, a compromise can be made that allows the user-specified number of levels of latches to be treated as a combination cell before terminating the dips first traversal. This allows the user to control the flexibility of time borrowing with respect to the size of the abstract memory image.

Creation of the physical shell

The creation of the logical shell results in the set of cells needed to represent the static timing path crossing through the pins of the block. In addition, the logical shell includes all nets connected to the pins of the cell to be retained.

The physical shell is the layout required to reveal the physical effects of the layout and configuration of the integrated circuit: resistance, capacitance, inductance, routing congestion, and process technology effects such as width and spacing rules, antenna rules, and electromigration rules. Data (wiring wires and vias).

The amount of physical detail that must be maintained in the physical abstraction depends on the level of accuracy required by the user. There can be a direct compromise between the level of accuracy and the amount of data that must be maintained.

The layout data includes the physical effects they use for the model (1) placement and routing, 2) antenna effects, 3) timing analysis (RC delay and capacitive coupling), 4) noise injection effects, and 5) IR-drop, And 6) electrochemical effects). Several new terms for the art have been introduced to describe the category, which are illustrated and described below in FIG. 12.

1) Placement and Routing

In order to be able to use the abstracted block during placement and routing, a) the physical dimensions of its boundary, b) the physical location allowed for the router to connect with the pins of the block, and c) the router to perform the connection. It is enough to model the block using the available layers. The model shown in FIG. 12 requires a block boundary and a set of all “pin-wires” defined as wires belonging to the pins of the block.

If overblock routing is allowed, it should contain sufficient information about the layers and abstractions that indicate where overblock routing is allowed. Since these regions are modeled as a set of polygons representing the regions that remain blocked for routing on each routing layer, the inverse of the polygon set is the region where external routing is allowed. A set of blockages can be made as needed to achieve any desired level of solution. However, it is usually sufficient to limit the non-blocked regions to a relatively small set of fixed width routing channels extending unbroken from one edge of the block to its opposite edge.

2) Antenna Rule Checking and Correction

One of the more difficult forms of the rules of the process description to accurately model is the antenna rule. The rule models the damage that can be caused to the MOSFET transistor gates by the charges accumulated on their connected metal (aluminum or copper) routing wires. While they are patterned and etched at the time of manufacture, charges may accumulate on the metal wire and cause failure of the gate oxide of its attached MOSFET but are safely discharged by junction diodes formed in the attached MOSFET source / drain regions. . The charge may also be safely discharged by a dedicated diode inserted specifically for this purpose.

To accurately model the antenna effect, the abstraction needs to include all wires electrically connected to each pin and all diodes, transistor gates, and transistor sources / drains connected to the pins through the wires. In FIG. 12 these item classes are labeled pin-wire, pin-net, pin-cell and die rod, respectively. By these physical objects included in the abstraction, it is possible to perform antenna rule checks and correction of antenna rule violations with respect to ancestors of blocks in the hierarchy.

3) Static timing analysis by wiring RC delay

In order to perform accurate static timing analysis of the blocks, not only the net that wires them, but also the cells of the logic shell. 12 shows a set of group-cells and boundary registers and other boundary cells that make up the logical shell.

However, in addition to the idealized delay which can be calculated by the logical shell netlist, parasitic effects caused by the geometry of the block's layout are also modeled. In order to accurately extract the resistance and capacitance known by each cell of the timing shell, it is referred to as the pin wire in FIG. 12 as well as the wire implementing all the nets attached to the cells in the timing shell, referred to as shell-wire in FIG. It is necessary to include a wire attached to the first input / output pin of the block.

Inclusion of pin- and shell-wires can encompass all parasitic resistances and capacitances caused by timing shell wires, but this is the sidewall capacitance provided by their adjacent wires, referred to as coupling-wires in FIG. Is ignored. In addition, these wires must be included to perform timing analysis and accurate extraction of the blocks. However, it should be noted that when modeling a simple RC-delay (without crosstalk), only coupling-wires need to be included, not all wire sets on the coupling-net. The coupling-wire can be configured to be at a constant potential, and therefore only serves to increase the effective capacitance of the pin-wire and shell-wire.

4) Static timing analysis by noise injection and crosstalk delay

Because of the well known Miller effect, the voltage change on the wire correspondingly causes a change on all neighboring wires to which it is capacitively coupled. Thus, in order to accurately model the timing on the pin-wire and shell-wire of FIG. 12, it is necessary to know the actual signal waveform on the coupling-wire. In order to calculate the coupling-wire waveform, the physical shell includes all the wires of the completed coupling net, and the logical shell comprises the cell (s) driven by the coupling-net and the driving cell (s) of the coupling-net. You need to include the complete path back to their source register.

In addition, to accurately capture the capacitance known by the coupling-net, it must include all wires that are capacitively coupled to the coupling-net. In a sense, they are called transitive-wires because they are transitively connected to pin-wire and shell-wire. Any coupling-net at a constant potential, such as power and ground nets, serves to protect the pin-net and shell-net from any crosstalk delay or noise injection. These are called shield-wires and transform-wires are involved with them.

The degree of data reduction that can be achieved through the logical and physical abstraction techniques described above depends on the logical structure of the block design. By most of the nature of their netlists for group-cells, largely register bound blocks get a high degree of reduction. Conversely, blocks that are pure combinations do not get any reduction.

If high compression is required (e.g. due to database size or runtime constraints), the hierarchical partitioning process should be aware of the abstraction method and attempt to ensure that the blocks are resist bound as much as possible. However, even in a well-divided design, some nets are likely to exhibit relatively deep logic inside the block abstraction. Several techniques can be used to reduce modeling requirements for the irregular net.

If the net is intentionally protected, crosstalk effects and noise injection do not occur. The loading known by each pin-wire and shell wire will be constant. Thus, the delay at each input pin only depends on the signal waveform shown on the pin, and the delay on each output pin only depends on the load shown on the pin. If these pins do not have near-critical delays, they can be modeled statically using traditional delay models such as lookup tables and piecewise linear delay functions.

If the net is not fully protected, static timing analysis may be used to develop a pessimistic delay model for non-critical pins. Thus, the complexity added to the abstraction mechanism of the present invention is only used for those pins that can contribute to the critical timing path of the design.

Also, since conventional logic gates have a relatively high electrical gain, one may take advantage of the fact that input slew dependencies tend to decline after two or three levels of logic. By this assumption, labeling of Tamil cells can stop after two or three levels of logic are met, and a simpler lookup table based modeling technique can be used to model the effects of additional excluded cells.

5) Static timing analysis by IR-drop analysis

As detailed herein, an IR-drop is an effect generated by high current flowing through a power distrubution network in a chip. The voltage known at any point in the network is equal to the current through the point multiplied by a known parasitic resistance between the points in the power supply. However, the effect can be thought of as an alternate distributed current source and can be somewhat offset by parasitic capacitance present in the network, which serves to store some charge. Dedicated decoupling capacitors may be used to enhance this effect.

When using block abstraction in bottom-up verification, assume that the block itself is interpreted and its IR-drop violation is known. The abstraction can be used to model the contribution of a block to the IR-drop given by the parent of the block. The interface between the block and its parent consists of a power supply pin, and the block's power network is connected to its parent. The exact model for the IR drop would consist of an equivalent circuit for the RC network between the pin and the power and ground supply plus a time-varying current source or sink for each pin.

The abstraction method of the present invention models, in contrast to an ideal mathematical model, a non-ideal electrical effect of the circuit by the netlist of the circuit and its own physical geometry. Unfortunately, IR drop analysis is not a path-based and local like static timing analysis or crosstalk, but rather models a comprehensive impact that encompasses the entire power / ground network and all cells in the block. For this reason, a simple electrical model can be used. Each pin is modeled as an ideal current source or sink, representing the result of the worst electrical analysis of the block. This analysis can be a static analysis or a dynamic simulation. Each pin is also associated with an equivalent circuit for an RC network, which is modeled as an impedance function.

Electromigration analysis

Electromigration is an effect related to the current through the wires of a circuit and its less than ideal resistance and capacitance. However, unlike IR drop analysis involving only the supply distribution network, electromigration analysis is performed on the supply network as well as the normal signal wires (usually with long resistive wires with high high current driver cells). Should be.

In order to model the electromigration of the supply network wires, not only how much current will pass through each wire, but also the parasitic impedance of the wires. Various models of electromigration may require peak or average current or even detailed time-domain simulations. In the supply network, this information is the same as that required for IR drop analysis, so the same abstraction mechanism as described above can be used. For signal wires, the information is the same as that required for the static timing analysis model. Therefore, no additional modeling information is added to model the electromigration effect.

An "inverse" abstraction mechanism

In another embodiment of the present invention, essentially the same technique may be used to construct a form of "inverse" abstraction for use in a bottom-up verification flow. The process of top-down block verification is described above in which a block is first interpreted and verified in isolation and then again verified in relation to its parent and sibling blocks. Only cells in a "group-cell" not included in the abstraction can be verified in isolation. All timing paths and electrical effects contained within the local shell of abstraction require information about the parent and sibling blocks of the block before they are interpreted.

Perhaps you want to interpret and verify the block according to the certification process needed to release the block as an independent IP (Intellectual Property) that can be reused later. In such a scenario a block can be verified by exemplifying it in an abstracted parent block representing some form of "reference platform" or in a "implementation" test harness.

The abstraction process can be used to construct a reduced model of the test harness. This technique, by embedding it in a complete reference chip design, provides a faster verification process than would be possible if the block was verified. Conversely, an abstract model would be more accurate than a typical test harness that could not contain a simple set of timing constraints and more than typical pin load and signal waveforms.

This "inverse" abstraction would be thought of as the logic of the shell and its associated physical geometry outside the boundaries of the block. This can be made using the same abstraction algorithm, except that it runs on the parent block and the traversal pin starts at the interface pins of the sub-block rather than the primary input, output and supply pins of the parent block.

13 illustrates a computer system that may implement one or more embodiments of the present invention. The illustrated computer system 1310 can be any general or special purpose computing or data processing machine such as a personal computer (PC) and can optionally be coupled to the network 1300. Since the memory 1311 of the computer system 1310 may be insufficient to maintain the overall contents of the circuit design or its inputs, a design process for breaking up the hierarchy may be necessary. In this way, pieces of the overall design can be handled by several different computer systems, each of which may be similar to computer system 1310. In doing so, the abstraction model that extracts the design of blocks and subblocks (modules and submodules) must take into account uniform and continuous application of processes such as timing analysis, placement, routing, and budgeting. As described above, the present invention seeks to approach abstraction problems and hierarchical design.

Those skilled in the art can program the computer system G10 to perform the tasks of abstraction and submodule design as described above in various embodiments of the present invention. This program code is executed using a processor 1312, such as a CPU (central processing unit), and a memory 1311, such as RAM (Random Access Storage), used to store / load instructions, addresses, and result data as needed. Can be. Application (s) used to perform the functions of the abstraction and submodule design may be obtained from executable files compiled from source code written in a language such as C ++. The executable file can be loaded into memory 1311 and the instructions are executed by processor 1312. Instructions in the executable file corresponding to the instructions needed to perform the abstraction may be stored in a disk 1318 or memory G11, such as a flip-flop drive, hard drive, or optical drive 1317. Various inputs, such as netist (s), constraints, process characteristics, cell libraries, and other such information, may be generated from the disk 1318, optical drive 1317 or even in the form of databases and / or flat files. 1300 may be written to access.

Computer system 1310 has a bridge 1314 coupled to a system bus 1313 and an I / O bus 1315 to assist in the transfer of information between the processor 1312 and the memory 1311. I / O bus 1315 connects various I / O devices, such as network interface card (NIC) 1316, disk 1318, and optical drive 1317, to system memory 1311 and processor 1312. Many combinations of I / O devices, buses and bridges may be used in the present invention and the combinations shown are merely illustrative of one of the possible combinations.

While the preferred embodiments of the invention have been described above, it is described for illustrative purposes only and does not limit the invention. Those skilled in the art will clearly understand that modifications of the present invention can be made without departing from the spirit of the present invention.

Claims (78)

The circuit has cells and interconnects, the circuit has a top-level and a representation hierarchically decomposed into a plurality of blocks, and at least some of the plurality of blocks may be further decomposed hierarchically. A method used to create an integrated circuit design that can have a parent block associated with it, Processing the one or more blocks to produce an abstraction that includes physical wiring information related to wiring between elements within the one or more blocks, wherein the physical wiring information includes an estimated operation of the integrated circuit. model the parasitic electrical and physical effects of the wires according to their behavior, Utilizing the abstraction in another development phase of executing the parent block. The method of claim 1, The processing step, Retaining only a subset of all the physical wiring information that affects the physical and electrical operation of the parent block; And Retaining only the subset of cells that affect the logical operation of the parent block. The method of claim 2, The step of utilizing, Replacing the description of the one or more blocks with the description of the abstract. The method of claim 2, Retaining the subset, Determining contents of a netlist of said at least one block. The method of claim 4, wherein The content of the netlist of the at least one block is Processing data inputs; Processing the outputs; And Characterized by processing clock inputs. The method of claim 5, Processing the data inputs comprises: Building a list of primary inputs. The method of claim 6, For each pin that is encountered until the list is empty, Removing the encountering pin from the list; If the removed pin is a clock pin, skipping the removed pin and continuing to the next pin; If the removed pin is not a clock pin, processing the removed pin forward. The method of claim 7, wherein Processing the removed pin forward, Constructing a list of successors. The method of claim 8, For each pin that meets, until the list of successors is empty, Removing the encounter successor pin from the list of successors; Labeling the removed successor pin's cells as timing cells; Skipping the removed successor pin if the removed successor pin is a clock pin; And If the removed successor pin is not a clock pin, checking whether the removed successor pin is a cell input. The method of claim 9, If the removed successor pin is a cell input, checking to see if the removed successor pin has more than one predecessor cell; If the removed successor pin has more than one predecessor cell, labeling the predecessor cell as a multi-driver load cell and repeatedly performing the processing of the removed pin forward. Way. The method of claim 10, The removed successor pin is not a cell input, or If the removed successor pin does not have more than one predecessor cell, repeating the processing of the removed pin forward. The method of claim 5, Processing the outputs Constructing a list of primary outputs. The method of claim 12, For each pin it encounters until the list is empty, Removing the encountering pin from the list; Processing the removed pin backwards. The method of claim 13, Processing the removed pin backwards, Constructing a list of predecessors. The method of claim 14, For each pin that meets, until the list of predecessors is empty, Removing the encountering predecessor pin from the list of predecessors; Labeling the removed predecessor pin cell as a timing cell; If the removed predecessor pin is a clock pin, skipping the removed predecessor pin; And If the removed predecessor pin is not a clock pin, checking whether the removed predecessor pin is a cell output. The method of claim 15, If the removed senior pin is a cell output, Labeling the successor cell as a sink load cell; And Iteratively performing the processing step behind the removed pin. The method of claim 15, If the removed successor pin is not a cell output, repeatedly performing the processing of the removed pin backwards. The method of claim 5, Processing the clock inputs Constructing a list of primary clock inputs. The method of claim 18, For each pin it encounters until the list is empty, Removing the encountering pin from the list; Processing the removed clock pin forward. The method of claim 19, Processing the removed pin forward, Constructing a list of successors. The method of claim 20, For each pin it encounters, until the list of successors is empty, Removing the encounter successor pin from the list of successors; If the removed successor pin is a clock pin, iteratively processing the removed successor pin forward; And If the removed successor pin is not a clock pin, skipping the removed successor pin. The method of claim 21, After repeatedly processing the removed successor pin forward, Checking which successor cell is labeled as a timing cell. The method of claim 22, If any successor cell is labeled as a timing cell, Labeling the removed successor pin's cells as timing cells; And Labeling the successor cell as a clock load cell. The method of claim 22, If no successor cell is labeled as a timing cell, skipping the removed successor pin. The method of claim 1, Wherein said physical wiring information models physical and electrical effects of a fabrication process and circuit layout. The method of claim 25, The physical and electrical effects may include placement, routing constraints, antenna influences, static timing analysis by RC delay modeling, static timing analysis by capacitive coupling and noise injection, static timing analysis and electromigration by IR drop modeling. (electromigration) A method comprising at least one of the analysis. The method of claim 26, Placement and routing effects in the one or more blocks are used to create the physical size of the boundaries of the one or more blocks, the physical location where an allowable connection can be made to the pins of the one or more blocks, and the allowed connection. Characterized in that it is modeled using one or more of the layers. The method of claim 26, The antenna effect is modeled by including in the abstract all pin wires electrically connected to each pin and including all diodes, transistor gates and transistor sources / drains connected to the pins through those wires. . The method of claim 26, The resistance-capacitance (RC) wiring delay during static timing analysis is modeled by including pin wires attached to the primary input / output pins of the block in the abstract, wherein the wires are all pin-nets attached to the cells in the timing shell. Method for implementing the. The method of claim 29, Sidewall coupling during static timing analysis is modeled by including in the abstract a coupling wire that can potentially be capacitively coupled to the pin wire. The method of claim 29, Noise injection and delay changes during static timing analysis due to capacitive coupling a) any wire on the coupling net that can potentially be capacitively coupled to the pin wire, b) an input pin of a drive cell modeled with a slew value and arrival time driven during simulation of the block, the coupling cell driving these nets and the coupler cell driven by these nets, and c) one or more of the transitive wires potentially capable of coupling to the included coupling net. The method of claim 29, Noise injection and delay changes during static timing analysis due to capacitive coupling a) any wire on the coupling net that can potentially be capacitively coupled to the pin wire, b) a drive modeled by including the entire cone of combinatorial logic up to and including a first latch or flip flop that drives these nets and all wires on the nets attached to the pins on the additional cell; An input pin of the cell, the coupling cell driving these nets and the coupling cell driven by these nets, c) modeled to include one or more of the "conversion wires" that can potentially be coupled to the included "coupling" nets. The method of claim 26, The IR drop effect is modeled using a simplified electrical model of the block, wherein each pin is modeled as an ideal current sink / source and associated impedance matrix to model the internal RC network. The method of claim 33, wherein Using the same information required for the power drop effect, an electromigration effect is modeled for the power net. The method of claim 30, Using the same information used in the static timing analysis, the electromigration impact is modeled for the signal net. 10. A method of designing an integrated circuit having cells and wiring, wherein the circuit is broken down into top-levels and into a plurality of blocks, wherein the blocks can be broken down more hierarchically. Processing the sibling block and the parent block of the one or more blocks to produce an inverse abstraction including physical wiring between elements within a parent and sibling block, wherein the physical wiring information Model the parasitic electrical and physical effects of the interconnections according to the estimated operation of the integrated circuit, Utilizing said inverse abstraction in at least one phase of designing and interpreting said one block. The method of claim 36, The phase comprises one or more of static timing analysis, noise analysis, power analysis, IR drop analysis and electromigration analysis, antenna rule violation detection and repair, placement and routing, implementation, design and verification. The method of claim 37, And utilizing a unified data model to integrate one or more of the aspects. The circuit has cells and wiring, the circuit has a top-level and hierarchically decomposed into a plurality of blocks, at least some of the plurality of blocks can be further decomposed hierarchically and associated with it An article made of a computer readable medium having instructions stored therein implementing a method used to create an integrated circuit design, which may have a block, When executed, the command Processing the one or more blocks such that an abstract is generated that includes physical wiring information related to the wiring between elements within the one or more blocks, wherein the physical wiring information is configured to determine whether or not the wiring is in accordance with the estimated operation of the integrated circuit. Model parasitic electrical and physical effects, And utilizing said abstraction in another development phase of executing said parent block. The method of claim 39, The processing step, Retaining only a subset of all the physical wiring information that affects the physical and electrical operation of the parent block; And Retaining only the subset of cells that affect the logical operation of the parent block. The method of claim 39, The step of utilizing, And replacing the description of the one or more blocks with the description of the abstract. The method of claim 40, Retaining the subset, Determining contents of a netlist of said at least one block. The method of claim 42, wherein The content of the logic shell is Processing data inputs; Processing the outputs; And And determine clock processing. The method of claim 43, Processing the data inputs comprises: Constructing a list of primary inputs. The method of claim 44, For each pin it encounters until the list is empty, Removing the encountering pin from the list; If the removed pin is a clock pin, skipping the removed pin and continuing to the next pin; And If the removed pin is not a clock pin, processing the removed pin forward. The method of claim 45, Processing the removed pin forward, Constructing a list of successors. 47. The method of claim 46 wherein For each pin that meets, until the list of successors is empty, Removing the encounter successor pin from the list of successors; Labeling the removed successor pin's cells as timing cells; Skipping the removed successor pin if the removed successor pin is a clock pin; And If the removed successor pin is not a clock pin, checking whether the removed successor pin is a cell input. The method of claim 47, If the removed successor pin is a cell input, Checking to see if the removed successor pin has more than one predecessor cell; If the removed successor pin has more than one predecessor cell, labeling the predecessor cell as a multi-driver load cell and repeatedly performing the processing of the removed pin forward. . The method of claim 48, The removed successor pin is not a cell input, or If the removed successor pin does not have more than one predecessor cell, repeating the processing of the removed pin forward. The method of claim 43, Processing the outputs comprises: Constructing a list of primary outputs. 51. The method of claim 50, For each pin it encounters until the list is empty, Removing the encountering pin from the list; Processing said removed pin backwards. The method of claim 51, Processing the removed pin backwards, And constructing a list of predecessors. The method of claim 52, wherein For each pin that meets, until the list of predecessors is empty, Removing the encountering predecessor pin from the list of predecessors; Labeling the removed predecessor pin cell as a timing cell; If the removed predecessor pin is a clock pin, skipping the removed predecessor pin; And If the removed predecessor pin is not a clock pin, checking whether the removed predecessor pin is a cell output. The method of claim 53, If the removed senior pin is a cell output, Labeling the successor cell as a sink load cell; And Iteratively executing the processing step behind the removed pin. The method of claim 53, If the removed successor pin is not a cell output, repeating the processing of the removed pin backwards. The method of claim 43, Processing the clock inputs comprises: Constructing a list of primary clock inputs. The method of claim 56, wherein For each pin it encounters until the list is empty, Removing the encountering pin from the list; Processing the removed clock pin forward. The method of claim 57, Processing the removed pin forward, Constructing a list of successors. The method of claim 58, For each pin it encounters, until the list of successors is empty, Removing the encounter successor pin from the list of successors; If the removed successor pin is a clock pin, iteratively processing the removed successor pin forward; And If the removed successor pin is not a clock pin, skipping the removed successor pin. The method of claim 59, After repeatedly processing the removed successor pin forward, Checking which successor cell is labeled as a timing cell. The method of claim 60, If any successor cell is labeled as a timing cell, Labeling the removed successor pin's cells as timing cells; And Labeling the successor cell as a clock load cell. The method of claim 60, If no successor cell is labeled as a timing cell, skipping the removed successor pin. The method of claim 39, Wherein the physical wiring information includes physical and electrical effects of fabrication process and circuit layout. The method of claim 63, wherein The physical and electrical influences include: placement, routing constraints, antenna influences, static timing analysis by RC delay modeling, static timing analysis by capacitive coupling and noise injection, static timing analysis and electromigration analysis by IR drop modeling. An apparatus comprising the above. 65. The method of claim 64, Placement and routing effects in the one or more blocks are used to create the physical size of the boundaries of the one or more blocks, the physical location where an allowable connection can be made to the pins of the one or more blocks, and the allowed connection. Apparatus, characterized in that modeled using one or more of the layers. 65. The method of claim 64, The antenna influence is modeled by including in the abstract all pin wires electrically connected to each pin and including all diodes, transistor gates and transistor sources / drains connected to the pins through those wires. . 65. The method of claim 64, The resistance-capacitance (RC) wiring delay during static timing analysis is modeled by including pin wires attached to the primary input / output pins of the block in the abstract, wherein the wires are all pin-nets attached to the cells in the timing shell. Apparatus characterized in that to implement. The method of claim 67, Sidewall coupling during static timing analysis is modeled by including in the abstract a coupling wire that can potentially be capacitively coupled to the pin wire. The method of claim 67, Noise injection and delay changes during static timing analysis due to capacitive coupling a) any wire on the coupling net that can potentially be capacitively coupled to the pin wire, b) an input pin of a drive cell modeled with a slew value and arrival time driven during simulation of the block, the coupling cell driving these nets and the coupler cell driven by these nets, and and c) one or more of the conversion wires potentially capable of coupling to the included coupling net. The method of claim 67, Noise injection and delay changes during static timing analysis due to capacitive coupling a) any wire on the coupling net that can potentially be capacitively coupled to the pin wire, b) a drive modeled by including the entire cone of combinatorial logic up to and including a first latch or flip flop that drives these nets and all wires on the nets attached to the pins on the additional cell; An input pin of the cell, the coupling cell driving these nets and the coupling cell driven by these nets, c) an apparatus characterized in that it comprises one or more of the "conversion wires" that can potentially be coupled to the included "coupling" net. 65. The method of claim 64, IR drop effect is modeled using a simplified electrical model of the block, each pin being modeled as an ideal current sink / source and associated impedance matrix to model the internal RC network. The method of claim 71, wherein Using the same information required for the power drop effect, an electromigration effect is modeled for the power net. The method of claim 68, An electromigration effect is modeled for a signal net using the same information used for static timing analysis. A computer readable medium having instructions stored therein embodied in a method of designing an integrated circuit having cells and wiring, where the circuit is broken down into top-level and plurality of blocks, and the blocks can be broken down more hierarchically. In the device consisting of, Processing the sibling block and the parent block of the one or more blocks to produce an inverse abstract including physical wiring between elements within a parent and sibling block, wherein the physical wiring information is included in the integrated circuit. Model the parasitic electrical and physical effects of the wirings according to the estimated behavior, And utilizing said inverse abstraction in at least one aspect of designing and interpreting said one block. The method of claim 74, wherein The aspect includes one or more of static timing analysis, noise analysis, power analysis, IR drop analysis and electromigration analysis, antenna rule violation detection and repair, placement and routing, implementation, design and verification. 76. The method of claim 75, And utilize a unified data model to integrate one or more of the aspects. The method of claim 1, The wiring comprises indications of an interface between at least one block having its parent block. The method of claim 39, And wherein the wiring comprises indications of an interface between at least one block having its parent block.