CN101051332A - Verifying system and method for SOC chip system grade - Google Patents
Verifying system and method for SOC chip system grade Download PDFInfo
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Abstract
A system grade verification system of SOC chip is prepared for setting GPIO module in SOC chip, forming hardware platform by GPIO hardware model and connecting GPIO module to GPIO hardware model, carrying out configuration and relevant data treatment on hardware platform and GPIO module as well as SOC chip by software platform, inputting signal to GPIO module, outputting converted hardware I/O signal to GPIO hardware model, generating control signal of software platform by utilizing hardware platform to receive output signal of GPIO module and inputting control signal to GPIO module to convert control signal to be command variables of software. Its verifying method is also disclosed.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, specifically, relate to a kind of SOC (SystemOn Trip, SOC (system on a chip)) chip system grade verification system and method.
Background technology
Along with microelectric technique develops to Nanoelectronic Technology, the integrated level of chip is also more and more higher, and the design of SOC chip and application are more and more general, but corresponding, and its checking and test job also become increasingly complex.
In the dedicated IC chip design, i.e. in the epoch of ASIC (Application Specific IntegratedCircuit), designing a chips needs several big key steps of completion code design, functional verification and placement-and-routing.The textual description of Code Design stage with chip functions is converted into certain circuit structure, Qualify Phase determines by means such as emulation whether the circuit structure of realizing exists careless omission, and placement-and-routing's stage then converts this circuit structure to can be for the silicon slice pattern of producing.
Owing to need all realize out to each function detail of realization product in the mode of transistor combination in the Code Design stage.Contain up to ten million transistorized designs for one, its complexity is well imagined.And these up to ten million transistors just can't be done any change more in a single day through after the production run, in case wherein wrong, might directly cause whole chips to work.So the functional verification work of design phase is extremely important.Facts have proved of industry member, the time that a chips spends in functional verification is that three times of time in Code Design stage also want many.
The focus that the SoC designing institute is paid close attention to no longer has been that the design of certain new function realizes, but how to go to assess, checking and integrated a plurality of design module that has existed.The method for designing of SoC is the brand-new flow process that is assembled into the basis with function.In order to finish systemic-function, the SoC design must rely on existing IP (Intellectual Property) module.But present many IP are at specific application at the beginning of design, thereby seldom consider and will use with external circuit collocation.If SoC designer wishes to utilize these IP, just must drop into strength revises them, also will consider the validation problem of IP module simultaneously.
The SOC chip generally is made up of unit such as one or more processor cores, bus, storer and IP modules.Wherein the IP module generally has processor bus interface, and its RTL (register transfer level) checking is divided into checking of IP module level and system-level checking.The verification method of checking of IP module level and ASIC (special IC) chip is similar, can utilize hardware description language or high level verification language to set up verification platform, realize the checking of IP functions of modules, whole verification environment can be regarded the debugging of pure hardware as, because the IP module has cpu bus interface.
In the checking and test job of chip, can make up the RTL checking and the test environment of entire chip by the inner addressable register of access chip.SOC chip and common asic chip structurally have very big-difference.The cpu bus interface of asic chip is the pin of chip, can realize visit to the chip internal addressable register by cpu i/f, thereby realizes the configuration to the chip functions and the pattern of use.The SOC chip is embedded one or more processor cores, processor core is realized the addressable register visit to chip internal, thereby realize configuration to the chip functions and the pattern of use, but the pin of chip does not generally have cpu bus interface, therefore can not be directly by the visit of pin realization to the chip internal addressable register.As can be seen, because the access mode difference of inner addressable register, the verification method of SOC chip and asic chip has very big difference.
In SoC chip system level verification, nearly all to use microprocessor and special software and hardware.Be closely-related between the software and hardware, but before system realized, the interaction between the software and hardware normally was difficult to accurately measure, some design mistakes can obviously not show yet.In order to address this problem, must adopt hardware and software co-verification technology.
Generally set up the system-level checking that the software and hardware cooperating simulation verification platform is realized the SOC chip by the software and hardware cooperating simulation instrument, software platform and hardware platform in this verification platform, have been comprised, software platform realizes mainly that to the configuration of system processor with to the visit of chip internal addressable register software platform can be realized by software programming language (C language) programming.Hardware platform is realized monitoring, data feedback and the checking interpretation of result to the chip pin signal, and hardware platform can be realized by programmings such as hardware description language or high level verification language.By the specific pin of chip, can realize the mutual control of the configuration of software platform and hardware platform, process, finally realize the system-level checking and the test of chip.
As can be seen, in the system-level proof procedure of SOC chip, specific pin by chip realizes that the mutual control of software platform and hardware platform is absolutely necessary, in concrete chip, these special chip pins are some common interfaces, for example UART (universal asynchronous receiver) interface, special bus interface etc.
In the SOC chip, the major function of UART is the UART receiving end that sends to peripheral hardware of data serial that parallel transmission in storer or the processor is transmitted, or the data of coming from the UART serial received of peripheral hardware are converted to parallel data.Can utilize the UART serial ports to carry out the control of SOC chip system grade software verification platform and Hardware Verification Platform, but UART interface transfer rate is lower, hardware platform is resolved UART data message more complicated, just need a plurality of UART serial ports if hardware platform carries out comparatively complicated control, but integrated a plurality of UART interfaces are uneconomic in the SOC chip.In some SOC chips, in order to test, control needs such as external chip, processor bus interface is designed to the pin of chip, therefore utilize processor bus interface also can carry out the control of software verification platform and hardware platform.Because processor interface has comprised data bus interface, address bus interface and clock signal etc., in the debugging and control procedure of software verification platform and Hardware Verification Platform, the bus interface utilization factor is lower.As can be seen, UART serial ports and bus interface etc. can be carried out the simple control of software verification platform and Hardware Verification Platform, but carry out and control neatly that certain limitation is then arranged complicated.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of SOC chip system grade verification system and method, utilize this system and method to control flexibly to software platform and hardware platform, thereby improve SOC chip design performance, shorten the design cycle of SOC chip.
In order to solve the problems of the technologies described above, the invention provides a kind of SOC chip system grade verification system, comprise software platform, hardware platform and SOC chip, described SOC chip comprises module to be verified, described SOC chip also comprises the GPIO module, described hardware platform comprises the GPIO hardware model, and described GPIO module links to each other with described GPIO hardware model by the GPIO interface; Described software platform is realized the configuration of hardware platform, GPIO module and SOC chip and related data are handled, and signal is input to described GPIO module, is converted into hardware output and input signal by described GPIO module, outputs to the GPIO hardware model; Described hardware platform receives from the output signal of GPIO module by described GPIO hardware model and produces control signal to software platform, and described control signal is input to the GPIO module, is converted into the software indieating variable by the GPIO module.
Further, described hardware platform also comprises module hardware model to be verified, and described module hardware model to be verified links to each other with described module to be verified.
The present invention also provides a kind of hardware platform of the SOC of being used for chip system grade verification system, comprise results analyses module and memory module, also comprise the GPIO hardware model, described GPIO hardware model links to each other with the data outputting module of SOC chip, receives from the data of the software platform line output of going forward side by side.
Further, described hardware platform also comprises module hardware model to be verified, and described module hardware model to be verified links to each other with the module to be verified of SOC chip.
The method that the present invention also provides a kind of SOC of utilization chip system grade verification system to verify is characterized in that, comprising:
(1) software platform generation checking begins indication, by the GPIO module output of SOC chip; GPIO hardware model in the hardware platform receives GPIO module output described begin indication after, realize output data record number and preparation;
(2) software platform or hardware platform send data to module to be verified, the data that software platform receives module to be verified write the GPIO module, the GPIO module outputs to the GPIO hardware model with described data, and the GPIO hardware model receives after these data its output;
(3) software platform generation system verification finishes indication, and by the GPIO module output of SOC chip, the GPIO hardware model produces Data Receiving and finishes indicator signal after receiving the checking end indication of GPIO module output, finishes checking.
Further, in step (3), also comprise: after described hardware platform carries out collection analysis to the data of GPIO hardware model output, output checking conclusion.
Further, software platform generation checking is carried out writing of software program and hardware model before beginning to indicate in step (1), and the compiling of software program and hardware program.
Further, in step (2), the GPIO hardware model adopts text or simulation waveform output data.
Further, also comprise step (4): GPIO hardware model ends with system process.
The present invention passes through the GPIO Application of Interface in the middle of SOC chip system grade verification system, a kind of system-level verification system and verification method of the GPIO of utilization interface are provided, use this verification system and verification method to provide the controlled RTL of software and hardware system-level checking as the SOC chip, has the control flexible characteristic, and then can constantly adjust chip design according to this verification system and method, improve SOC chip design performance, and shorten the SOC chip design cycle, save SOC chip design cost.
Description of drawings
Fig. 1 is GPIO interface principle figure;
Fig. 2 is the SOC chip system grade verification system synoptic diagram that the present invention carries out the IP module verification;
Fig. 3 is that IP of the present invention is the hardware platform synoptic diagram of the SOC chip system grade verification system of chip pin;
Fig. 4 is that IP of the present invention is the SOC chip system grade verification method process flow diagram of chip pin;
Fig. 5 is that IP of the present invention is not the hardware platform synoptic diagram of the verification system of chip pin;
Fig. 6 is that IP of the present invention is not the SOC chip system grade verification method process flow diagram of chip pin;
Fig. 7 is the verification system synoptic diagram that the present invention carries out the UART module verification;
Fig. 8 is the hardware platform synoptic diagram that the present invention carries out the UART module verification;
Fig. 9 is the SOC chip system grade verification method process flow diagram that the present invention carries out the UART module verification.
Embodiment
The present invention passes through the GPIO Application of Interface in the middle of SOC chip system grade verification system, utilize the GPIO interface that the hardware platform and the software platform of the system-level checking of SOC chip RTL are controlled, a kind of system-level verification method of the GPIO of utilization interface is provided simultaneously, use this method, can provide the controlled RTL of software and hardware system-level checking for the SOC chip, can constantly adjust chip design according to this verification system and method, improve SOC chip design performance.
With reference to shown in Figure 1, be GPIO interface principle figure.The GPIO interface comprises bus interface module 13, register module and GPIO direction control module 14.Bus interface module 13 is connected with processor core or bus bridge, realizes the mutual transmission of bus to the GPIO interface data.Register module comprises that bus data writes register 10, bus data readout register 11 and control register 12, and control register 12 is realized the configuration of GPIO interface direction.GPIO direction control module 14 realizes the input and output direction of GPIO interface as chip pin, and its direction is by the configuration decision of control register 12.
It is simple to utilize the GPIO interface to control implementation method, interface data transmission speed is higher, the software platform programming is simple, flexible, the hardware platform hardware model is realized simple, and can make full use of resources of chip, the control procedure that makes software and hardware is more fast with simple, thus the shortening SOC chip design cycle, saving SOC chip design cost.
In the present invention, software platform is finished the generation that system verification begins, finishes indication, send data, the data that receive are analyzed and exported, input and output control register to the GPIO interface is programmed, determine the direction of GPIO interface, these functions all are converted into hardware output and input signal by the GPIO interface, are connected with hardware platform.Hardware platform is finished transmission, reception and result's output of verification msg, and the hardware of system process feedback and ends with system process, and these functions all are converted into the software indieating variable by the GPIO interface.
Below in conjunction with accompanying drawing to a preferred embodiment of the present invention will be described in detail:
Embodiment one:
With reference to shown in Figure 2, carry out the SOC chip system grade verification system synoptic diagram of IP module verification for the present invention.This verification system comprises SOC chip 20, software platform 21 and hardware platform 22.SOC chip 20 mainly comprises processor module 23, bus bridge module 24, GPIO module 25, IP module 26 and internal memory control module 27.Software platform 21 is realized the configuration of IP module 26, GPIO module 25 and processor 23 and related data are handled.
With reference to shown in Figure 3, be the hardware platform synoptic diagram of the SOC chip system grade verification system of chip pin for IP of the present invention.This hardware platform comprises GPIO hardware model 30, IP hardware model 31, memory module 32 and results analyses module 33.Memory module 32 realizes that by hardware description language other modules and hardware model can be realized by hardware description language or high level verification language.Memory module 32 links to each other with the internal memory control module 27 of SOC chip shown in Figure 2, realizes the transcode storage of software platform.GPIO hardware model 30 links to each other with the interface of the GPIO module 25 of SOC chip shown in Figure 2, realizes the monitoring of GPIO interface output signal and produces control signal to software platform.IP hardware model 31 is connected with IP module 26 interfaces of SOC chip shown in Figure 2, realize the transmission and the reception of SOC chip I P module 26 particular interface data, results analyses module 33 realizes collection and the analysis to GPIO hardware model 30 and IP hardware model 31 output results.
With reference to shown in Figure 4, be the SOC chip system grade verification method process flow diagram of chip pin for IP of the present invention.This method comprises the following steps:
Step 401: in software platform, write software program; In hardware platform, write hardware model;
Step 402: composing software program in software platform; In hardware platform, compile hardware program;
Following steps 403 to step 406 is verified and test for carrying out SOC chip I P module receive direction:
Step 403: software produces IP checking beginning indication, and it is write the register that writes of GPIO module; The checking that GPIO hardware model and IP hardware model detect the GPIO module interface begins indicator signal, carries out output data record number and preparation, starts the IP hardware model;
Step 404:IP hardware model sends data to the IP module interface, and software program detects the data that the IP module receives;
Step 405: the data that the data readout register analyzing IP module of software program by the IP module receives, judge whether it is the ED indication, if then execution in step 407, otherwise execution in step 406;
Step 406: software obtains valid data, valid data are written to writing in the register of GPIO module, the GPIO hardware model receives valid data by the GPIO module interface, by text or simulation waveform output, results analyses module is gathered and is analyzed the data of output with its result; Execution in step 404;
Step 407: software program generates Data Receiving and finishes indication, is written into the GPIO module and writes in the register; The GPIO hardware model produces Data Receiving and finishes indicator signal, results analyses module output SOC IP module verification conclusion after receiving and finishing indication from the Data Receiving of GPIO module interface;
Following steps 408 to step 411 is verified and test for carrying out SOC chip I P module sending direction:
Step 408: software produces IP checking beginning indication, it is write the GPIO module write register; The GPIO hardware model detects IP checking beginning indication of GPIO module interface output, starts the IP hardware model;
Step 409: software produces data, being written to the IP module writes in the register, being written to the GPIO module simultaneously writes in the register, the data that the GPIO hardware model generates by GPIO module interface receiving software platform, the data that the IP hardware model generates by IP module interface receiving software platform are with the output data that receives;
Certainly, this step also can be first written to the IP module and write in the register for after software produces data, is written to the GPIO module subsequently and writes in the register;
Step 410: software produces system verification and finishes indication, is written to the GPIO module and writes in the register; The GPIO hardware model produces Data Receiving and finishes indicator signal, hardware platform results analyses module output SOC IP module verification and test result after receiving this checking end indication;
Step 411:GPIO hardware model ends with system process.
Embodiment two:
With reference to shown in Figure 5, not the verification system hardware platform synoptic diagram of chip pin for IP of the present invention.This hardware platform comprises GPIO hardware model 50, memory module 50 and results analyses module 52.GPIO hardware model 50 is connected with the GPIO module 25 of SOC chip shown in Figure 2, and memory module 51 is connected with the internal memory control module 27 of SOC chip shown in Figure 2.
Verification system difference among verification system in the present embodiment and the embodiment one only is hardware platform, and the composition of software platform and SOC chip is identical.
With reference to shown in Figure 6, not the SOC chip system grade verification method process flow diagram of chip pin for IP of the present invention.This method may further comprise the steps:
Step 601: in software platform, write software program; In hardware platform, write hardware model;
Step 602: composing software program in software platform; In hardware platform, compile hardware program;
Step 603: software produces IP checking beginning indication, and it is write the register that writes of GPIO module; The GPIO hardware model detects from the beginning indicator signal of GPIO module interface output, realizes output data record number and preparation;
Step 604: software produces data, is written to the IP module and writes in the register, is written to the GPIO module subsequently and writes in the register; The GPIO hardware model receives valid data by the GPIO module interface of SOC chip, and its result is exported by text or simulation waveform;
Step 605: software is read data in the IP module readout register, these data are written to the GPIO module to be write in the register, software program has been stored contrast and the analysis that sends data and receive data then, this result is written to the GPIO module writes in the register; The GPIO hardware model receives valid data by the GPIO module interface, and its result is exported by text or simulation waveform;
Step 606: software produces checking and finishes indication, is written to the GPIO module and writes in the register; The GPIO hardware model produces Data Receiving and finishes indicator signal, hardware platform results analyses module output SOC IP module verification and test result after receiving this checking end indication;
Step 607:GPIO hardware model ends with system process.
Embodiment three:
With reference to shown in Figure 7, carry out the SOC chip system grade verification system synoptic diagram of UART module verification for the present invention.This verification system comprises SOC chip 70, software platform 71 and hardware platform 72.SOC chip 70 mainly comprises processor module 73, bus bridge module 74, GPIO module 75, UART module 76 and internal memory control module 77 etc.
With reference to shown in Figure 8, carry out the hardware platform synoptic diagram of UART module verification for the present invention.This hardware platform comprises GPIO hardware model 80, UART hardware model 81, memory module 82 and results analyses module 83.UART hardware model 81 is realized the transmission and the reception of SOC chip UART module 76 particular interface data shown in Figure 7, and results analyses module 83 realizes collection and the analysis to GPIO hardware model 80 and UART hardware model 81 output results.
With reference to shown in Figure 9, carry out the SOC chip system grade verification method process flow diagram of UART module verification for the present invention;
Step 901: in software platform, write software program; In hardware platform, write hardware model;
Step 902: composing software program in software platform; In hardware platform, compile hardware program;
Following steps 903 to 906 are for carrying out checking of SOC chip UART module receive direction and test:
Step 903: software produces UART checking beginning indication, and it is write the register that writes of GPIO module; The checking that GPIO hardware model and UART hardware model detect the GPIO interface begins indicator signal, realizes output data record number and preparation, starts the UART hardware model;
Step 904:UART hardware model sends data to the UART module interface, and software program detects the data that the UART module receives;
Step 905: software program is analyzed the data that the UART module receives by the data readout register of UART module, judges whether it is the ED indication, if then execution in step 907, otherwise execution in step 906;
Step 906: software obtains valid data, and valid data are written to writing in the register of GPIO module, and the GPIO hardware model receives valid data by the GPIO module interface, and its result is exported by text or simulation waveform; Execution in step 904;
Step 907: generate Data Receiving and finish indication, be written into the GPIO module and write in the register; The reception that the GPIO hardware model receives from the GPIO module interface finishes to indicate back generation Data Receiving to finish indicator signal, hardware platform results analyses module output SOC UART module verification and test result;
Following steps 908 to 911 are for carrying out checking of SOC chip UART module sending direction and test:
Step 908: software produces UART checking beginning indication, this indication is write the GPIO module write register; The UART checking that the GPIO hardware model detects the output of GPIO module interface pin begins to refer to, starts the UART hardware model;
Step 909: software produces data, is written to the UART module and writes in the register, is written to the GPIO module simultaneously and writes in the register; The data that the software platform that the GPIO hardware model sends by GPIO module interface receiving chip generates, the data that the software platform that the UART hardware model sends by UART module interface receiving chip generates; GPIO hardware model and UART hardware model are with the data output that receives, and results analyses module is gathered and analyzed the data of output;
Certainly, this step also can be written to the UART module and write in the register for software produces data, is written to the GPIO module subsequently and writes in the register;
Step 910: software produces system verification and finishes indication, is written to SOC chip GPIO module and writes in the register; After the GPIO hardware model receives and finishes indication, produce Data Receiving and finish indicator signal, hardware platform results analyses module output UART module verification and test result;
Step 911:GPIO hardware model ends with system process.
Technique scheme all is applicable to system-level checking of the software-hardware synergism of SOC chip and embedded system and test, can pass through one road GPIO interface or the realization of the multichannel GPIO interface control to software verification platform and Hardware Verification Platform.
The present invention utilizes the GPIO interface to the hardware platform of the system-level checking of SOC chip RTL and the control of software platform, has realized the system integration functional verification to the SOC chip.Use this method, can be for the SOC chip provide system-level checking of the controlled RTL of software and hardware and test platform, thus chip design can constantly be adjusted according to this verification platform, improve SOC chip design performance, and shorten the SOC chip design cycle, save SOC chip design cost.
Claims (9)
1, a kind of SOC chip system grade verification system comprises software platform, hardware platform and SOC chip, and described SOC chip comprises module to be verified, it is characterized in that,
Described SOC chip also comprises the GPIO module, and described hardware platform comprises the GPIO hardware model, and described GPIO module links to each other with described GPIO hardware model by the GPIO interface;
Described software platform is realized the configuration of hardware platform, GPIO module and SOC chip and related data are handled, and signal is input to described GPIO module, is converted into hardware output and input signal by described GPIO module, outputs to the GPIO hardware model;
Described hardware platform receives from the output signal of GPIO module by described GPIO hardware model and produces control signal to software platform, and described control signal is input to the GPIO module, is converted into the software indieating variable by the GPIO module.
2, SOC chip system grade verification system as claimed in claim 1 is characterized in that, described hardware platform also comprises module hardware model to be verified, and described module hardware model to be verified links to each other with described module to be verified.
3, a kind of hardware platform that is used for the described SOC chip system grade of claim 1 verification system, comprise results analyses module and memory module, it is characterized in that, also comprise the GPIO hardware model, described GPIO hardware model links to each other with the data outputting module of SOC chip, receives from the data of the software platform line output of going forward side by side.
4, hardware platform as claimed in claim 3 is characterized in that, described hardware platform also comprises module hardware model to be verified, and described module hardware model to be verified links to each other with the module to be verified of SOC chip.
5, a kind of method of utilizing the described SOC chip system grade of claim 1 verification system to verify is characterized in that, comprising:
(1) software platform generation checking begins indication, by the GPIO module output of SOC chip; GPIO hardware model in the hardware platform receives GPIO module output described begin indication after, realize output data record number and preparation;
(2) software platform or hardware platform send data to module to be verified, the data that software platform receives module to be verified write the GPIO module, the GPIO module outputs to the GPIO hardware model with described data, and the GPIO hardware model receives after these data its output;
(3) software platform generation system verification finishes indication, and by the GPIO module output of SOC chip, the GPIO hardware model produces Data Receiving and finishes indicator signal after receiving the checking end indication of GPIO module output, finishes checking.
6, method as claimed in claim 5 is characterized in that, also comprises in step (3): after described hardware platform carries out collection analysis to the data of GPIO hardware model output, and output checking conclusion.
7, method as claimed in claim 5 is characterized in that, software platform generation checking is carried out writing of software program and hardware model before beginning to indicate in step (1), and the compiling of software program and hardware program.
8, method as claimed in claim 5 is characterized in that, in step (2), the GPIO hardware model adopts text or simulation waveform output data.
9, method as claimed in claim 5 is characterized in that, also comprises step (4): GPIO hardware model ends with system process.
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