CN111709215A - IP management system and IP management method - Google Patents
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Abstract
The invention discloses an IP management system and an IP management method, and relates to the IP management system and the IP management method. The invention aims to solve the problems that the existing IP level SoC design process is complicated and tedious and the accuracy rate is reduced due to excessive repeated work along with the increase of a system. An IP management system includes: the IP management system comprises a configuration management module, a grammar analysis module, a register analysis module, a model generation module, a text generation module, a global check module and an integration module; the configuration file content comprises position information of each soft IP, a hard IP source file or each soft and hard IP model file, macro information of each soft and hard IP, path information of each soft and hard IP, and SystemRDL file position information or self-defined register information description file position information corresponding to each soft and hard IP. The invention is used in the field of digital chip design and its EDA tools.
Description
Technical Field
The present invention relates to an IP management system and an IP management method.
Background
With the continuous evolution of the IC industry, the functions and scale of the chip are gradually improved, so that the scale of the IC is rapidly increased, and the competition between the chip industries is also increased. How quickly a product can react to the market; the system has the advantages that the requirements for multiple functions, high performance and low power consumption are met, and meanwhile, the system development cost is effectively reduced; for continuous updating and iteration, how to shorten the development cycle of the processes such as chip design verification implementation and the like, thereby accelerating the time to market has become the focus of market attention. In the nanometer era, the manufacturing capability of integrated circuits is steadily advancing by various emerging technologies according to moore's law, however, the design method based on cell library can not meet the increasingly complex requirements, the existing design capability and EDA tool capability are far behind the development of semiconductor technology, and how to improve the design capability and efficiency and keep pace with the increase of the complexity of chips becomes a research hotspot.
The reusable concept divides the system into a plurality of modules according to functions, and directly utilizes each component and the prior knowledge and experience to build an integrated chip with specific functions, so that the design level is prevented from directly rising from a unit module to a system structure from zero without mud realized by a deep sinking module, thereby reducing the complexity of the whole system design and improving the efficiency. The advent of reusable design methodologies has become a leap in the history of integrated circuit design, has gained widespread acceptance in the industry, and has become mainstream. However, by using the IP level multiplexing, how to perform compatibility of the IPs of different manufacturers, how to use the IPs quickly and accurately, how to reduce the design workload by using the continuity and the reusability of different project projects, and a set of more complete management method is needed. By using the support of the management platform, the corresponding IP is rapidly configured, searched and used, the design efficiency of the system chip is improved, and the risk of design and development is reduced. Therefore, it is necessary to design a reusable IP management platform with universality, high efficiency and accuracy for the use and management of IP.
Disclosure of Invention
The invention aims to provide an IP management system and an IP management method for solving the problems that the existing IP level SoC design process is complicated and tedious and the accuracy rate is reduced due to excessive repeated work along with the increase of the system.
An IP management system includes:
the IP management system comprises a configuration management module, a grammar analysis module, a register analysis module, a model generation module, a text generation module, a global check module and an integration module.
The IP management method of the IP management system comprises the following specific processes:
step one, carrying out corresponding configuration work on all managed IPs according to the requirements of an IP management system, namely compiling configuration files of the IP management system;
the configuration file content comprises position information of each soft IP, a hard IP source file or each soft and hard IP model file, macro information of each soft and hard IP, path information of each soft and hard IP, and SystemRDL file position information or self-defined register information description file position information corresponding to each soft and hard IP;
step two, after the configuration file is transmitted to the IP management system, a configuration management module of the IP management system extracts and distributes the content of the configuration file in the step one, and simultaneously processes the configuration of the IP management system and the control information of the IP management system;
the configuration management module extracts control information of the IP management system, wherein the control information of the IP management system comprises the starting condition and the configuration of the working state of each module in the IP management system;
the configuration management module of the IP management system analyzes the configuration file, finds source files or model files corresponding to the soft and hard IPs according to the position information and the path information of the soft and hard IPs of the configuration file, finds macros corresponding to the soft and hard IPs, and finds SystemRDL files or custom register information description files corresponding to the soft and hard IPs;
the configuration management module of the IP management system distributes position information and path information of each soft IP and each hard IP, source files or model files corresponding to each soft IP and each hard IP and macros corresponding to each soft IP and each hard IP are transmitted to a Verilog grammar compiler and a grammar analysis module of the IP management system;
the configuration management module of the IP management system distributes the position information and the path information of each soft IP and each hard IP, and SystemRDL files or custom register information description files corresponding to each soft IP and each hard IP are transmitted to a SystemRDLCompiler and a register analysis module of the IP management system;
thirdly, the IP management system utilizes a Verilog grammar compiler to extract and analyze the contents of the source files of the soft and hard IP or the model files of the soft and hard IP to generate an abstract grammar tree;
a syntax analysis module of the IP management system performs traversal search on the AST by using a traversal algorithm to realize the acquisition of three information of soft and hard IP layers, parameterization and ports; further acquiring the top layer of the IP according to the soft and hard IP layers;
transmitting the obtained soft and hard IP layers, parameterizations, ports and top layer information to a model generation module of the IP management system by a syntax analysis module of the IP management system;
the model generation module of the IP management system constructs a port abstract model for each port of the soft and hard IPs by utilizing the hierarchy, parameterization, port and top information of the soft and hard IPs extracted by the syntax analysis module of the IP management system;
fourthly, the IP management system processes SystemRDL file contents obtained by a configuration management module of the IP management system from the configuration file by means of a SystemRDLCompiler tool to generate a tree structure;
the register analysis module of the IP management system processes the tree structure, acquires register bit width, type and address information of each soft IP and each hard IP, and transmits the register bit width, type and address information of each soft IP and each hard IP to the model generation module of the IP management system;
the register analysis module of the IP management system directly extracts the bit width, type and address information of the registers of the soft and hard IPs by using self-defined register description information without passing through SystemRDLCompiler, and transmits the bit width, type and address information to the model generation module of the IP management system, and constructs a register address mapping abstract model for the registers of the soft and hard IPs.
Step five, the configuration management module of the IP management system controls a text generation module of the IP management system according to the control information of the IP management system extracted in the step two, so that the text generation module of the IP management system automatically generates the verification files of SPEC and UVM and the text information of the C language header file containing the IP register address according to the requirement;
step six, the global check module of the IP management system checks the existence and the validity of all the information of the configuration file of the IP management system in the step one;
the global check module of the IP management system can check the legality of the port abstract model and the register address mapping abstract model generated by the model generation module of the IP management system, and the legality of the direction, the bit width, the name and the parameter is checked for each port of the port abstract model of each soft IP and each port of the register address mapping abstract model of each hard IP, the legality of the name, the bit width, the address and the type and the correctness of the address and the bit width which have mathematical relations are checked for the register address mapping abstract model of each soft IP and each register address mapping abstract model of each hard IP, and errors are corrected or error warning is generated;
the method comprises the following steps that a global check module of an IP management system checks a SPEC and UVM verification file generated by a text generation module of the IP management system, and checks the availability of a C language header file containing an IP register address;
step seven, the integration module of the IP management system can acquire the information of the source files or model files of the soft and hard IPs, the macros of the soft and hard IPs, the path information, the SystemRDL files of the soft and hard IPs or the self-defined register information description files acquired by the configuration management module of the IP management system; the soft and hard IP layers, parameterizations, ports and top layer information of each soft and hard IP are analyzed by a syntax analyzing module of the IP management system, and the soft and hard IP layers, parameterizations, ports and top layer information are analyzed; the port abstract model is generated by a model generation module of the IP management system, and the register address maps the information of the abstract model; integrating text information generated by a text generation module of the IP management system to generate a complete IP management system, adding the complete IP management system into a management library, and waiting for the call of a user;
and step eight, repeating the step three to the step seven until all the information of the managed IP in the step one is integrated to generate a complete IP management system, adding the complete IP management system into the management library, and waiting for the call of the user.
The invention has the beneficial effects that:
the invention utilizes the reusable thought, improves the chip design flow through the management platform, can use the configuration file to assist the development, reduces the work of chip designers, improves the design efficiency, ensures the design accuracy, and is an auxiliary development tool which shortens the development flow and improves the efficiency and the accuracy.
In the migration change of different chip development projects or the same project, in the transverse and longitudinal updating of the project, besides the reusability of IP, the configuration file of the management platform can be used for multiple times, and the problem that the project needs to be restarted every time is avoided. As shown in fig. 1, the IPs used by the project a0 are a _0, B _0, and C _0, and with iterative update of different projects, if the configuration file includes all available IPs, the management platform may not need to be changed in all the projects a0-a2, B0, and C0, and if other modules are introduced, the management platform may only need to update the platform configuration to work, thereby increasing the reuse probability and improving the efficiency. And secondly, the management platform can automatically generate the SPEC and UVM verification models and related drive development files, so that the parallelism and accuracy of chip development are improved, the compatibility with other CAD tools is ensured, and the work of developers is reduced. The problem that the existing IP-level SoC design process is too much in repeated work and the accuracy rate is reduced along with the increase of a system is solved, the existing chip development design process is improved, an IP management platform designed by calling IP quickly and accurately is realized, and the design efficiency is improved.
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FIG. 1 is a block diagram of an IP management system according to the present invention;
FIG. 2 is a diagram of an exemplary reusability of IP management in accordance with the present invention;
FIG. 3 is a diagram illustrating an exemplary configuration file format specification according to the present invention;
FIG. 4 is a flow chart of a method for generating a port abstraction model by the model generation module according to the present invention;
FIG. 5 is a flowchart of a method for generating a register address mapping abstraction model by the model generation module according to the present invention.
Detailed Description
The first embodiment is as follows: as shown in fig. 1, an IP management system according to the present embodiment includes:
the IP management system is mainly used for realizing the management and modeling work of soft and hard IP and providing basic service for IP level instantiation and interconnection in chip design;
the IP management system mainly comprises a configuration management module, a grammar analysis module, a register analysis module, a model generation module, a text generation module, a global check module and an integration module.
The second embodiment is as follows: the first difference between the present embodiment and the specific embodiment is: the configuration management module is used for analyzing, extracting and distributing the configuration files of the IP management system;
the configuration file content comprises position information of each soft IP, a hard IP source file or each soft and hard IP model file, macro information of each soft and hard IP, path information of each soft and hard IP, and SystemRDL file position information or self-defined register information description file position information corresponding to each soft and hard IP;
the model files of the soft and hard IP are provided in the IP and are existing as the source file;
the files provided by the soft and hard IPs have at least one source file or model file, all the files or only one file, and the IP management system can manage the IPs;
generally speaking, soft IP is generally in the form of a source file, hard IP is in the form of a model file, but not necessarily, and it is also specifically referred to what IP provides, so that the source file or model file of soft and hard IP is said together;
other steps and parameters are the same as those in the first embodiment.
The third concrete implementation mode: the present embodiment differs from the first or second embodiment in that: the grammar parsing module is specifically as follows:
after the source files of the soft and hard IPs or the model files of the soft and hard IPs are processed by a Verilog syntax compiler (for example, the processing of the Pyverilog, … … compiler should be well known, and the Pyverilog is a compiler front-end tool) to generate an Abstract Syntax Tree (AST), a syntax parsing module processes the abstract syntax tree by using a traversal algorithm, so as to obtain three information of the soft and hard IPs in hierarchy, parameterization, and port.
Other steps and parameters are the same as those in the first or second embodiment.
The fourth concrete implementation mode: the difference between this embodiment and one of the first to third embodiments is that the register analysis module specifically includes:
after a SystemRDL file is processed by a SystemRDLCompiler (SystemRDL compiler) to generate a tree structure, or self-defined register information description files are provided in soft and hard IPs, a register parsing module is used for processing the tree structure or the self-defined register information description files to realize the acquisition of bit width, type and address information of each register (from the representation form, the IPs are presented in the forms of source files or model files and the like, the content of the files is source codes of the IPs, the logic meaning of the source codes comprises register information, and accurate registers can be obtained more clearly from the corresponding SystemRDL file);
the self-defined register information description file is a format file containing bit width, type and address information of each register in the soft IP and the hard IP.
(SystemRDL is also one of the format files, the SystemRDL format is an industrial standard, some IPs do not provide SystemRDL files, so that the IP management platform can customize one format to achieve the same function as the SystemRDL, and people using the IP management platform can use SystemRDL and also can use the customized format, so that the method is flexible);
other steps and parameters are the same as those in one of the first to third embodiments.
The fifth concrete implementation mode: the difference between this embodiment and one of the first to fourth embodiments is: the model generation module is used for port modeling of soft and hard IP and register modeling;
for a port model, according to the obtained IP level, IP parameterization, each port of the IP, bit width, input and output directions and port names of each port, packaging the information, constructing data structures such as classes or structural bodies and the like, and delivering the data structures to a global check module for checking, wherein the check comprises checking bit width (some bit widths contain parameters, and meanwhile, the check parameters and the check are legal if some bit widths do not have parameters), checking the direction to be legal, checking the name to be unique and legal, checking the layer correctness, and returning the check results to a model generation module for outputting;
for the register model, according to the obtained offset address, name, bit width and read-write type of each register, packaging the information, constructing data structures such as classes or structural bodies and the like, checking the global check module, checking the mathematical relationship of the offset address and the bit width, checking that the name is unique and legal and the check type is correct and legal, and returning the check result to the model generation module for output;
other steps and parameters are the same as in one of the first to fourth embodiments.
The sixth specific implementation mode: the difference between this embodiment and one of the first to fifth embodiments is: the text generation module is used for automatically generating a SPEC and UVM verification file, a C language header file containing IP register addresses and other text information according to the information obtained by the register analysis module (the register analysis module is used for processing a tree structure or a self-defined register information description file and realizing the acquisition of bit width, type and address information of each register in soft and hard IPs); (these files may or may not be generated in their entirety, and specifically, what contents are desired to be generated is flexible depending on the use of the user of the IP management platform) (this "text information" may also be generated in accordance with IP-XACT, HTML).
Spec (differentiation): the technical specification document exists in various forms such as pdf, word and web page, and the IP management system mainly generates the technical specification document in the form of web page (HTML);
uvm (universalverication method): the universal verification methodology, specifically, based on a syntax of SystemVerilog, the IP management system mainly generates a verification file of UVM;
other steps and parameters are the same as those in one of the first to fifth embodiments.
The seventh embodiment: the difference between this embodiment and one of the first to sixth embodiments is: the global check module is used for checking the legality and the usability of the soft and hard IP port models, the register models and the text information generated by the text generation module, and correcting errors and warning errors at the same time, so that the correctness of the soft and hard IP port models, the register models and the text information generated by the model generation module is ensured.
Other steps and parameters are the same as those in one of the first to sixth embodiments.
The specific implementation mode is eight: the present embodiment differs from one of the first to seventh embodiments in that: the integration module is used for integrating the source files of the soft and hard IPs, the model files, the port models of the soft and hard IPs generated by the model generation module, the register model and the text information generated by the text generation module to generate a complete IP management system, adding the complete IP management system into a management library and waiting for the call of a user; the IP management system provides services for IP instantiation and interconnection during chip design and system architecture definition of the chip.
Other steps and parameters are the same as those in one of the first to seventh embodiments.
The specific implementation method nine: the IP management method of this embodiment includes the following specific processes:
step one, carrying out corresponding configuration work on all managed IPs according to the requirements of an IP management system, namely compiling configuration files of the IP management system;
the configuration file content comprises position information of each soft IP, a hard IP source file or each soft and hard IP model file, macro information of each soft and hard IP, path information of each soft and hard IP, and SystemRDL file position information or self-defined register information description file position information corresponding to each soft and hard IP;
(SystemRDL is also one of the format files, the SystemRDL format is an industrial standard, some IPs do not provide SystemRDL files, so that the IP management platform can customize one format to achieve the same function as the SystemRDL, and people using the IP management platform can use SystemRDL and also can use the customized format, so that the method is flexible);
step two, after the configuration file is transmitted to the IP management system, the configuration management module of the IP management system extracts and distributes the content of the configuration file in the step one, and simultaneously processes the configuration of the IP management system (the configuration of the working state, such as the operation target address, whether the file generation module is started to generate the file information, the path position of the file information generated by the file generation module, the name of the file generated by the file generation module, whether the register analysis module is started, and the like) and the control information of the IP management system;
the method comprises the steps that a configuration management module extracts control information of an IP management system, wherein the control information of the IP management system comprises the starting conditions of all modules (the configuration management module, a syntax analysis module, a register analysis module, a model generation module, a text generation module, a global inspection module and an integration module) in the IP management system, the configuration of working states (such as an operating target address, whether a file generation module is started to generate file information, a path position of the file generation module to generate the file information, whether the file generation module generates a file name, whether the register analysis module is started, and the like), the operating target address, whether the file generation module is started to generate the file information, the path position of the file generation module to generate the file information, whether the file generation module generates the file name, whether the register analysis module is started, and the like;
the configuration management module of the IP management system analyzes the configuration file, finds source files or model files corresponding to the soft and hard IPs according to the position information and the path information of the soft and hard IPs of the configuration file, finds macros corresponding to the soft and hard IPs, and finds SystemRDL files or custom register information description files corresponding to the soft and hard IPs;
the configuration management module of the IP management system distributes position information and path information of each soft IP and each hard IP, source files or model files corresponding to each soft IP and each hard IP, macros corresponding to each soft IP and each hard IP and transmits the macros to a Verilog grammar compiler (such as Pyverilog) and a grammar parsing module of the IP management system;
the configuration management module of the IP management system distributes the position information and the path information of each soft IP and each hard IP, and SystemRDL files or self-defined register information description files corresponding to each soft IP and each hard IP are transmitted to a SystemRDLCompiler (SystemRDL compiler) and a register analysis module of the IP management system;
thirdly, the IP management system utilizes a Verilog grammar compiler (or a compiler front-end tool such as Pyverilog) to extract and analyze the contents of the soft and hard IP source files or the soft and hard IP model files to generate an Abstract Syntax Tree (AST) (basically all compilers generate the AST, but different compiler generation modes are different possibly, the process is determined according to different compilers, but the result is almost the same);
a syntax analysis module of the IP management system performs traversal search on the AST by using a traversal algorithm to realize the acquisition of three information of soft and hard IP layers, parameterization and ports; and further obtain the top level of IP according to the soft, hard IP hierarchy (an IP is generally formed by multiple modules, the big module is formed by the little module, for example, the long one, so there is the concept of the top level);
transmitting the obtained soft and hard IP layers, parameterizations, ports and top layer information to a model generation module of the IP management system by a syntax analysis module of the IP management system;
the model generation module of the IP management system utilizes the soft and hard IP layers, parameterizations, ports and top layer information extracted by the syntax analysis module of the IP management system to construct a port abstract model for each soft and hard IP port (the information is packaged to construct data structures such as classes or structural bodies);
processing SystemRDL file contents obtained by a configuration management module of the IP management system from a configuration file by the aid of a SystemRDL compiler front-end tool by the IP management system to generate a tree structure;
the register analysis module of the IP management system processes the tree structure, acquires register bit width, type and address information of each soft IP and each hard IP, and transmits the register bit width, type and address information of each soft IP and each hard IP to the model generation module of the IP management system;
the register analysis module of the IP management system can also utilize self-defined register description information without passing through
And the SystemRDLCompier directly extracts the bit width, type and address information of the registers of the soft and hard IPs, transmits the bit width, type and address information to a model generation module of the IP management system, and constructs a register address mapping abstract model (packages the information and constructs data structures such as classes or structural bodies) for the registers of the soft and hard IPs.
Step five, the configuration management module of the IP management system controls a text generation module of the IP management system according to the control information of the IP management system extracted in the step two, so that the text generation module of the IP management system automatically generates the verification files of SPEC and UVM, the C language header file containing the IP register address and other text information according to the requirement;
step six, the global check module of the IP management system checks the existence and the validity of all information (all mentioned in the step one) of the configuration file of the IP management system in the step one;
the global check module of the IP management system can check the legality of the port abstract model and the register address mapping abstract model generated by the model generation module of the IP management system, and the legality of the direction, the bit width, the name and the parameter is checked for each port of the port abstract model of each soft IP and each port of the register address mapping abstract model of each hard IP, the legality of the name, the bit width, the address and the type and the correctness of the address and the bit width which have mathematical relations are checked for the register address mapping abstract model of each soft IP and each register address mapping abstract model of each hard IP, and errors are corrected or error warning is generated;
the global check module of the IP management system checks the SPEC and UVM verification files generated by the text generation module of the IP management system, checks the availability of the C language header file containing the IP register address and ensures the correctness;
step seven, the integration module of the IP management system can acquire the information of the source files or model files of the soft and hard IPs, the macros of the soft and hard IPs, the path information, the SystemRDL files of the soft and hard IPs or the self-defined register information description files acquired by the configuration management module of the IP management system; the soft and hard IP layers, parameterizations, ports and top layer information of each soft and hard IP are analyzed by a syntax analyzing module of the IP management system, and the soft and hard IP layers, parameterizations, ports and top layer information are analyzed; the port abstract model is generated by a model generation module of the IP management system, and the register address maps the information of the abstract model; integrating text information generated by a text generation module of the IP management system to generate a complete IP management system, adding the complete IP management system into a management library, and waiting for the call of a user; and providing services for IP instantiation and interconnection during chip design and chip system architecture definition.
And step eight, repeating the step three to the step seven until all the information of the managed IP in the step one is integrated to generate a complete IP management system, adding the complete IP management system into the management library, and waiting for the call of the user.
The IP management system utilizes a configuration management module, a Pyverilog and SystemRDL analysis tool, a grammar analysis module, a register analysis module, a model generation module, a text generation module, a global check module and an integration module to realize the management of the IP, thereby assisting the chip development process, reducing the content of interest of chip development designers and improving the efficiency. (step seven, basically, one IP management is finished, the configuration file of the step one comprises a plurality of IPs, and the steps three to seven are basically repeated).
As shown in fig. 2, the IPs used by the project a0 are a _0, B _0, and C _0, and with iterative update of different projects, if the configuration file includes all available IPs, the management platform may not need to be changed in all the projects a0-a2, B0, and C0, and if other modules are introduced, the management platform may only need to update the platform configuration to work, thereby increasing the reuse probability and improving the efficiency. And secondly, the management platform can automatically generate the SPEC and UVM verification models and related drive development files, so that the parallelism and accuracy of chip development are improved, the compatibility with other CAD tools is ensured, and the work of developers is reduced. The problem that the existing IP-level SoC design process is too much in repeated work and the accuracy rate is reduced along with the increase of a system is solved, the existing chip development design process is improved, an IP management platform designed by calling IP quickly and accurately is realized, and the design efficiency is improved.
The following examples were used to demonstrate the beneficial effects of the present invention:
the first embodiment is as follows:
the invention uses JSON to realize the configuration of the management platform and uses Python to realize all the functions of the IP management platform. Firstly, for the use of a management platform, corresponding configuration is carried out on different projects or existing IPs through JSON, and source files of each IP, including related information such as paths, SystemRDL files or model files and the like are included. The JSON configuration template for the IP management platform is shown in fig. 3. The configuration management module of the management platform can automatically analyze the configuration file meeting the requirements, acquire the main information of the source file, and distribute and transmit the information to each module in the management platform according to the requirements.
The management platform generates an abstract syntax tree by using information of a Pyverilog tool and a configuration management module, and then, as shown in fig. 4, by using an iterative search algorithm of the platform 1, the instantiated content of each module in each IP is searched in various ways such as precise search, regular search and fuzzy search, so as to determine the hierarchical relationship. According to the top module of the IP, obtaining the parameterization information, the port condition of the top, including the port name, the direction, the bit width and the like of each signal. And then the management platform establishes an IP port abstract model through the model generation module, and checks the structure of the management platform and the generated model to ensure the accuracy of the model. The generated port abstract model provides guarantee for instantiation and interconnection work of each IP in the management platform, so that the design and development efficiency is improved.
The management platform analyzes the SystemRDLCompier file by using a SystemRDLCompier tool, and generates a corresponding tree structure for each IP. Meanwhile, the acquisition of the register information can be realized by utilizing a self-defined analysis module of the platform. Address mapping information, including register name, address, bit width, type, etc., is obtained through further processing of the platform. And the management platform generates a corresponding register abstract model by using the model generation module and checks the accuracy of the model. The model provides support for a system architecture of SoC development in a management platform, improves development efficiency and ensures design accuracy. Furthermore, the management platform utilizes the information to generate information such as UVM files, software development header files, HTML and the like through a text generation module of the platform, so that the work of chip development is reduced, and the parallelism of chip design engineering is improved.
Finally, an integration module of the management platform configures the IP source file, the SystemRDL file and the register description file obtained by the management module; useful macro definitions and parameterization information screened out by iterative searching and analyzing are obtained; the port abstract model and the address mapping abstract model generated by the model generation module are sorted and further checked, and are added into the library. In the chip development process, an IP management platform is used for assisting, macro definition and parameterization information change are realized for each IP of SoC development through controlling the management platform, automatic generation and copying of engineering catalogues and corresponding files are realized, instantiation and interconnection are realized through port model development, and system structure definition is realized through an address mapping model, so that the IP management platform is used for realizing rapid design of IC development project engineering.
The present invention is capable of other embodiments and its several details are capable of modifications in various obvious respects, all without departing from the spirit and scope of the present invention.
Claims (9)
1. An IP management system, characterized by: the system comprises:
the IP management system comprises a configuration management module, a grammar analysis module, a register analysis module, a model generation module, a text generation module, a global check module and an integration module.
2. The IP management system according to claim 1, wherein: the configuration management module is used for analyzing, extracting and distributing the configuration files of the IP management system;
the configuration file content comprises position information of each soft IP, a hard IP source file or each soft and hard IP model file, macro information of each soft and hard IP, path information of each soft and hard IP, and SystemRDL file position information or self-defined register information description file position information corresponding to each soft and hard IP.
3. An IP management system according to claim 1 or 2, characterized in that: the grammar parsing module is specifically as follows:
after the source files of the soft and hard IP or the model files of the soft and hard IP are processed by the Verilog grammar compiler to generate the abstract grammar tree, the grammar parsing module processes the abstract grammar tree by using a traversal algorithm to realize the acquisition of three information of the soft and hard IP layers, parameterization and ports.
4. The IP management system according to claim 3, wherein: the register analysis module specifically comprises:
after the SystemRDL file is processed by the SystemRDL Compiler to generate a tree structure, or self-defined register information description files are provided in the soft IP and the hard IP, the register analysis module is used for processing the tree structure or the self-defined register information description files to realize the acquisition of bit width, type and address information of each register in the soft IP and the hard IP;
the self-defined register information description file is a format file containing bit width, type and address information of each register in the soft IP and the hard IP.
5. The IP management system according to claim 4, wherein: the model generation module is used for port modeling and register modeling of soft and hard IP.
6. The IP management system according to claim 5, wherein: the text generation module is used for automatically generating the verification files of SPEC and UVM and the text information of the C language header file containing the IP register address according to the information obtained by the register analysis module.
7. The IP management system according to claim 6, wherein: the global check module is used for checking the legality and the usability of the soft and hard IP port models, the register models and the text information generated by the text generation module, and correcting errors and warning errors at the same time, so that the correctness of the soft and hard IP port models, the register models and the text information generated by the model generation module is ensured.
8. The IP management system according to claim 7, wherein: the integration module is used for integrating the source files of the soft and hard IPs, the model files, the port models of the soft and hard IPs generated by the model generation module, the register model and the text information generated by the text generation module to generate a complete IP management system, adding the complete IP management system into the management library and waiting for the call of a user.
9. The IP management method of the IP management system according to claim 1, wherein: the method comprises the following specific processes:
step one, carrying out corresponding configuration work on all managed IPs according to the requirements of an IP management system, namely compiling configuration files of the IP management system;
the configuration file content comprises position information of each soft IP, a hard IP source file or each soft and hard IP model file, macro information of each soft and hard IP, path information of each soft and hard IP, and SystemRDL file position information or self-defined register information description file position information corresponding to each soft and hard IP;
step two, after the configuration file is transmitted to the IP management system, a configuration management module of the IP management system extracts and distributes the content of the configuration file in the step one, and simultaneously processes the configuration of the IP management system and the control information of the IP management system;
the configuration management module extracts control information of the IP management system, wherein the control information of the IP management system comprises the starting condition and the configuration of the working state of each module in the IP management system;
the configuration management module of the IP management system analyzes the configuration file, finds source files or model files corresponding to the soft and hard IPs according to the position information and the path information of the soft and hard IPs of the configuration file, finds macros corresponding to the soft and hard IPs, and finds SystemRDL files or custom register information description files corresponding to the soft and hard IPs;
the configuration management module of the IP management system distributes position information and path information of each soft IP and each hard IP, source files or model files corresponding to each soft IP and each hard IP and macros corresponding to each soft IP and each hard IP are transmitted to a Verilog grammar compiler and a grammar analysis module of the IP management system;
the configuration management module of the IP management system distributes the position information and the path information of each soft IP and each hard IP, and SystemRDL files or custom register information description files corresponding to each soft IP and each hard IP are transmitted to a SystemRDL Compiler and a register analysis module of the IP management system;
thirdly, the IP management system utilizes a Verilog grammar compiler to extract and analyze the contents of the source files of the soft and hard IP or the model files of the soft and hard IP to generate an abstract grammar tree;
a syntax analysis module of the IP management system performs traversal search on the AST by using a traversal algorithm to realize the acquisition of three information of soft and hard IP layers, parameterization and ports; further acquiring the top layer of the IP according to the soft and hard IP layers;
transmitting the obtained soft and hard IP layers, parameterizations, ports and top layer information to a model generation module of the IP management system by a syntax analysis module of the IP management system;
the model generation module of the IP management system constructs a port abstract model for each port of the soft and hard IPs by utilizing the hierarchy, parameterization, port and top information of the soft and hard IPs extracted by the syntax analysis module of the IP management system;
fourthly, the IP management system processes SystemRDL file contents obtained by the configuration management module of the IP management system from the configuration file by means of a SystemRDL Compiler tool to generate a tree structure;
the register analysis module of the IP management system processes the tree structure, acquires register bit width, type and address information of each soft IP and each hard IP, and transmits the register bit width, type and address information of each soft IP and each hard IP to the model generation module of the IP management system;
the register analysis module of the IP management system directly extracts the bit width, type and address information of the registers of the soft and hard IPs by using self-defined register description information without passing through SystemRDLCompiler, and transmits the bit width, type and address information to the model generation module of the IP management system to construct a register address mapping abstract model for the registers of the soft and hard IPs;
step five, the configuration management module of the IP management system controls a text generation module of the IP management system according to the control information of the IP management system extracted in the step two, so that the text generation module of the IP management system automatically generates the verification files of SPEC and UVM and the text information of the C language header file containing the IP register address according to the requirement;
step six, the global check module of the IP management system checks the existence and the validity of all the information of the configuration file of the IP management system in the step one;
the global check module of the IP management system can check the legality of the port abstract model and the register address mapping abstract model generated by the model generation module of the IP management system, and the legality of the direction, the bit width, the name and the parameter is checked for each port of the port abstract model of each soft IP and each port of the register address mapping abstract model of each hard IP, the legality of the name, the bit width, the address and the type and the correctness of the address and the bit width which have mathematical relations are checked for the register address mapping abstract model of each soft IP and each register address mapping abstract model of each hard IP, and errors are corrected or error warning is generated;
the method comprises the following steps that a global check module of an IP management system checks a SPEC and UVM verification file generated by a text generation module of the IP management system, and checks the availability of a C language header file containing an IP register address;
step seven, the integration module of the IP management system can acquire the information of the source files or model files of the soft and hard IPs, the macros of the soft and hard IPs, the path information, the SystemRDL files of the soft and hard IPs or the self-defined register information description files acquired by the configuration management module of the IP management system; the soft and hard IP layers, parameterizations, ports and top layer information of each soft and hard IP are analyzed by a syntax analyzing module of the IP management system, and the soft and hard IP layers, parameterizations, ports and top layer information are analyzed; the port abstract model is generated by a model generation module of the IP management system, and the register address maps the information of the abstract model; integrating text information generated by a text generation module of the IP management system to generate a complete IP management system, adding the complete IP management system into a management library, and waiting for the call of a user;
and step eight, repeating the step three to the step seven until all the information of the managed IP in the step one is integrated to generate a complete IP management system, adding the complete IP management system into the management library, and waiting for the call of the user.
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