CN1862266A - Method for testing product fault-tolerant performance and fault inserting device thereof - Google Patents
Method for testing product fault-tolerant performance and fault inserting device thereof Download PDFInfo
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- CN1862266A CN1862266A CN 200510072436 CN200510072436A CN1862266A CN 1862266 A CN1862266 A CN 1862266A CN 200510072436 CN200510072436 CN 200510072436 CN 200510072436 A CN200510072436 A CN 200510072436A CN 1862266 A CN1862266 A CN 1862266A
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Abstract
The present invention provides a product fault-tolerance test method and its fault insertion device. Said invention utilizes the production of fault analog signal to implement fault-tolerance test of product. Said method includes the following steps: setting fault insertion device in product interior, utilizing fault insertion device to produce fault analog signal with different types, utilizing CPU control interface of product interior to gate communication control module of fault insertion device, control contents of fault insertion device, control contents of control register of communication control module and selectively make fault analog signal with different types be inserted into arbitrary chip input/output pin or directly inserted into functional module of chip interior so as to simulate partial failure or complete failure of product interior unit.
Description
Technical field
The present invention relates to the electronic product reliability test, particularly a kind of product fault-tolerance method of testing and fault thereof are inserted device.
Background technology
The design of hyundai electronics series products becomes increasingly complex, and shared status is also more and more important in people's life, and to the increasingly stringent that requires of product reliability aspect, in case product breaks down, for example high-end communication products will bring very big loss to the user.Therefore fault-tolerant reliability design becomes increasingly important in the electronic product, tests also to become becoming more and more important at the product fault-tolerance of product reliability design thereupon.
The fault-tolerance test is certain chip failure of analog equipment inside; internal clock signal is lost; under the situations such as internal state signal error, whether product can take correct protection, warning measure, and whether the wrong back product that recovers can return to correct duty.The fault-tolerant reliability testing of product can verify whether the product reliability design can correctly realize by test on the one hand, be on the other hand to insert the problem of finding product fault-tolerant design aspect by fault, in the hope of just taking corresponding measure at the product initial stage, revise the problem of the fault-tolerant aspect of product, improve reliability of products.The core of product fault-tolerance test is the insertion pattern of fault simulation signal.
At present, the inserted mode of fault simulation signal all is to take external probe to insert the mode of fault-signal basically, be that 02108648 the method that patent adopted is to use external electronic unit to produce rub-out signals such as high and low, pulse as China Patent No., output on the external probe, again probe is attached on the signaling point of product inside, carries out fault and insert.
But there is the problem of following method in the prior art:
1, need extra rub-out signal generating unit, cost is higher, also will consider how to make probe closely to contact with signaling point, and technology realizes comparatively complicated, and versatility is not strong;
2, operability is relatively poor, needs to place manually-operateds such as probe, and for a lot of complex product of internal signal point, the manually-operated testing efficiency of this needs is not high relatively;
3, owing to be to adopt external signal is superimposed upon mode on the inner original signal of product, drive under the stronger situation at internal signal, can only make the distortion of product internal signal during being inserted with of external signal, in addition for high-frequency signal, even there is not fault-signal to insert on the probe that adds, also can produce a very large impact, just can not judge correctly under these situations that the fault of expection is inserted the influence that signal causes product, can not obtain correct fault and insert the test effect signal quality;
4, by can't simulating signal open circuit fault mode under (high-impedance state) of outside inserted mode, still can only adopt the method for artificial disconnection product internal path to test.
Summary of the invention
The objective of the invention is to overcome that the prior art operability is relatively poor, testing efficiency is low, the test effect is inaccurate and the defective of (high-impedance state) fault mode down that can't simulating signal opens circuit, thereby a kind of product tolerating measure method and fault insertion device thereof are provided.
For solving the problems of the technologies described above, the product fault-tolerance method of testing that technical scheme of the present invention provided is at the dissimilar fault simulation signal of the inner generation of product, by fault simulation signal is controlled, automatically determine that fault simulation signal inserts type and insertion position, thereby realize analog equipment built-in function cell mesh or whole the inefficacy.
Described fault simulation signal inserts device by fault and produces, and fault simulation signal comprises: grow tall, long low, high-impedance state, recurrent pulse, monopulse or the adjustable burst of pulses signal of number.
Fault is inserted device between the signaling interface and chip functions module of chip internal, and and has the two-way signaling path between chip signal interface and the chip functions module, by the control of product internal communication interface, fault simulation signal can insert the signaling interface of chip and the signal flow between the chip functions module selectively.
Fault is inserted device can also be arranged in programmable logic device (PLD), and and has the two-way signaling path between the signaling interface of programmable logic device (PLD), by the control of product internal communication interface, fault simulation signal can insert the signaling interface of programmable logic device (PLD) and the signal flow between the described chip signal interface selectively.
The step that fault simulation signal inserts comprises:
(1) definite fault type that needs insertion;
(2) definite abort situation that needs insertion;
(3) enable fault and insert, whether the working condition of checkout object meets expected results, if do not meet then carry out relative recording and analysis;
(4) config failure inserts and to stop, and whether the working condition of checkout object meets expected results, if do not meet then carry out relative recording and analysis.
It is the unit entity that adopts the describing mode realization of hardware language that described fault is inserted device.
A kind of fault provided by the invention is inserted device, it is characterized in that comprising communication control module, fault-signal generation module and fault insertion selection module, and communication control module inserts with fault-signal generation module and fault respectively selects module to link to each other; Associated control signal is passed to the fault-signal generation module to communication control module and fault is inserted the selection module, with the insertion type and the insertion position of definite fault simulation signal, thus analog equipment built-in function cell mesh or all inefficacies.
Described communication control module comprises control signal interface and control register, cpu control bus carries out read-write operation by the control signal interface to control register, and fault-signal type that the control fault signal generator module produces and fault are inserted the fault-signal insertion of selecting module and enabled and the insertion position.
Described control register comprises that fault-signal produces control register and fault is inserted the selection control register;
Described fault-signal produces control register and comprises:
The fault type control register that is used for control fault signal generator module output fault-signal type;
The output pulse width control register that is used for the gating pulse width; With
The output number of pulses control register that is used for gating pulse quantity;
Described fault is inserted the fault-signal insertion of selecting the control register control fault to insert the selection module and is enabled and the insertion position.
Described fault-signal generation module is deciphered the content of fault type control register, obtains the control signal of fault-signal traffic pilot, and control traffic pilot gating is inserted into fault-signal accordingly, and sends into fault and insert in the selection module.
Described fault is inserted the content of selecting module that fault is inserted the selection control register and is deciphered, and produces to select control signal, the insertion position of control fault signal and the insertion of fault-signal and recovery.
Described fault-signal generation module directly adopts the work clock of chip, or utilizes chip and the unnecessary pin of programmable logic device (PLD) to introduce the various types of fault simulation signals of clock generating from the outside.
The invention has the advantages that, by being set in product inside, fault inserts device, thereby inner realize growing tall at product, long low, high-impedance state, pulse signal, periodic signal etc. comprehensively fault-signals produce and insert, the partial failure of analog equipment internal element or all inefficacies, can carry out the fault-tolerant on-line testing of product, for the control and the insertion of fault-signal type provides control interface simply and easily, improved the automatic test degree of fault-tolerance test, and then improved fault-tolerant class reliability testing efficient on the whole and reduce testing cost.
Description of drawings
Fig. 1 inserts the schematic block diagram that device embeds at chip internal for fault;
Fig. 2 is a schematic block diagram of realizing special chip fault insertion test by programmable logic device (PLD);
Fig. 3 inserts the interface synoptic diagram of device for fault;
Fig. 4 inserts the structured flowchart of device for fault;
Fig. 5 is the type map of fault-signal;
Fig. 6 is the structured flowchart of fault-signal generation module;
Fig. 7 inserts the structured flowchart of selecting module for fault;
Fig. 8 inserts operational flowchart for fault.
Embodiment
As shown in Figure 1, we insert the unit at fault-signal of the inner embedding of the special chip of the programmable chip of product inside or design voluntarily, need carry out signal that fault inserts and receive corresponding functional unit again after by this resume module, this trouble unit can carry out fault insertion processing to the input/output signal and the signal between the chip internal functional module of chip interface, but be not restricted to use at chip I/O pin place, also can be used for the insertion of internal chip enable signal fault, insert as the internal module A of chip and the fault of internal module B interface signal, it is inner as phaselocked loop also to can be used for analog chip, Service Processing Module, the inefficacy of chip part functional modules such as CPU communication control module.
As shown in Figure 2, insert the chip of device for can not directly embedding fault, we can introduce programmable logic device (PLD) with its interface signal, realize its fault is inserted in programmable logic device (PLD).
Has the two-way signaling path between the signaling interface of fault insertion device and chip and the chip functions module, control by product innernal CPU control interface, fault simulation signal can be inserted selectively the signaling interface of chip and the signal flow between the chip functions module, that is to say, fault insertion device can be chosen in the chip pin input signal to chip functions processing module direction arbitrarily, or to the chip pin output signal of chip exterior interface direction, and insert fault-signal on the internal interface signal between chip internal functional module A and functional module B.Fault is inserted the describing mode that device adopts hardware languages such as VHDL and Verilog HDL at present, is embedded in generation unit entity in the chip of programmable logic chip or design voluntarily.
As shown in Figure 3, fault insertion device interface comprises:
(1) address/data input bus, cpu control bus such as sheet choosing and read-write control.
(2) work clock signal input.
(3) be inserted into the fault-signal input.
(4) output of the signal after fault processing unit is handled.
Inserting device control by fault is that original signal is sent, or inserts the fault-signal of simulation on signal.
As shown in Figure 4, fault is inserted device and is comprised communication control module, and fault-signal generation module and fault are inserted parts such as selecting module.
Communication control module partly comprises CPU control signal interface and control registers such as fault-signal generation control register, fault insertion selection control such as address, data bus and sheet choosing, read-write control.This part can be equal to a functional component for the treatment of for product inside, by the communication interface of direct use product inside chip, can insert device internal control register to fault and carry out read-write operation.By fault being inserted the content control of device internal control register, realization is controlled the fault-signal type that the fault-signal generation module produces, and realizes that fault is inserted selection module failure signal inserts the control that whether enables with the insertion position.
As shown in Figure 5, the fault-signal generation module is according to the content of fault-signal generation control register in the communication control module, and control produces following various fault modes:
(1) level grows tall;
(2) level is long low;
(3) signal wire high-impedance state;
(4) the adjustable periodic pulse signal of pulsewidth;
(5) the adjustable single pulse signal of pulsewidth;
(6) the burst of pulses signal that number is adjustable, pulse width is adjustable.
As shown in Figure 6 and Figure 7, the fault-signal generation module directly can adopt the work clock of chip, or utilize chip and the unnecessary pin of programmable logic device (PLD) to introduce clock from the outside, and can carry out frequency division to it in inside, the pulse width variation scope of its generation can be provided with easily as required.Fault-signal produces control register and comprises fault type control register, output pulse width and output quantity control register.By fault type control register encoded control gating is inserted into fault-signal accordingly.When output pulse class signal, output pulse width and the width of output quantity control register gating pulse and the number of pulse.The fault-signal generation module is delivered to fault with the fault-signal that produces and is inserted an end of selecting the traffic pilot (MUX) in the module, is inserted by fault and selects module controls whether to insert fault-signal on interface signal.
Fault is inserted and is selected module to insert the content of selecting control register according to fault in the CPU Communications Control Interface, decoding produces selects control signal, deliver on the control end of the traffic pilot on the interface, output original signal or fault-signal on the insertion position of decision fault-signal and the interface signal, thereby the insertion and the recovery of realization fault-signal.
So we just can insert the mode of device internal register by writing fault, realize that very easily the fault of chip interface is inserted, and as shown in Figure 8, its operation steps is as follows:
1, configures test environment, setup test.This moment, product was in normal operating conditions, and is professional normal.
2, by being inserted into the CPU control interface of failure chip, insert the device communication control module with fault and carry out the information transmission, relevant configuration information Write fault is inserted the insertion of device internal fault selects the fault insertion of module to select control register, configure the abort situation that needs insertion, promptly on that signal, carry out fault and insert.
3, by being inserted into the CPU control interface of failure chip, insert the device communication control module with fault and carry out the information transmission, the fault-signal that relevant configuration information Write fault is inserted device internal fault signal generator module produces control register, configures the fault type that needs to insert (high and low, high resistant, pulse etc.).If the insertion pulse fault signal also needs the pulse high-low level width control register of config failure signal generator module, number of pulses control register simultaneously.
4, by being inserted into the CPU control interface of failure chip, insert the device communication control module with fault and carry out the information transmission, relevant configuration information Write fault is inserted the insertion of device internal fault select the fault insertion of module to select control register, enable fault and insert.
5, whether checkout object working condition meets expected results, and incongruent words are carried out relative recording and analysis.
6, by being inserted into the CPU control interface of failure chip, insert the device communication control module with fault and carry out the information transmission, relevant configuration information Write fault is inserted the insertion of device internal fault select the fault insertion of module to select control register, stop fault and insert.If what insert is pulse fault signal, will stops fault automatically after pulse output is finished and insert.
7, whether checkout object working condition meets expected results, and incongruent words are carried out relative recording and analysis.
8, continue test, repeat the 1-7 step, carry out next fault and insert test.
From above-mentioned to specific descriptions of the present invention as can be seen, can improve the measurability of veneer by method of the present invention, enrich the fault-tolerance method of testing, insert means for tolerating measure provides a kind of simple, powerful online fault, can finish the simulation of following polytype signal fault
(1) signal wire grows tall;
(2) the signal line length is low;
(3) signal wire open circuit (high resistant);
(4) the signal wire monopulse inserts;
(5) signal wire burst of pulses signal inserts;
(6) signal line states continuous oscillation;
Thereby finish product inside chip, functional unit partial failure or all failure of removal simulations, do not need extra rub-out signal generating unit, reduced cost; The fault microcosmic that inserts is controlled, and favorable repeatability can guarantee to insert the rub-out signal of expection, each fault-signal unanimity of inserting.Can solve outside artificial fault when inserting control accuracy low, the fault-signal consistance is bad, signal line states and the inconsistent problems such as (can't drag down fully as clock signal) of expection.Improved the test effect; Operability is good, need not to put manually-operateds such as probe and welding, has improved testing efficiency; Easy to use, software inserts the control of the cpu i/f realization of device to fault insertion apparatus module by fault, can specify arbitrarily which signal is carried out fault insertion, the fault type of insertion, the trouble duration that inserts, packaged test event can well incorporate automatic test; Fault is inserted the portable good of apparatus module, its inner core rub-out signal generation module, the signal that produces can be shared for all pins, take resource seldom, irrelevant with the function that veneer and logic itself realize, as long as the veneer inside chip has cpu i/f, just can adopt this method.
Claims (12)
1, a kind of product fault-tolerance method of testing, this method is at the dissimilar fault simulation signal of the inner generation of product, by control to fault simulation signal, determine the insertion type and the insertion position of fault simulation signal automatically, thus analog equipment built-in function cell mesh or all inefficacies.
2, product fault-tolerance method of testing according to claim 1, it is characterized in that: described fault simulation signal inserts device by fault and produces, and fault simulation signal comprises: grow tall, long low, high-impedance state, recurrent pulse, monopulse or the adjustable burst of pulses signal of number.
3, product fault-tolerance method of testing according to claim 2, it is characterized in that: fault is inserted device between the signaling interface and chip functions module of chip internal, and and has the two-way signaling path between chip signal interface and the chip functions module, by the control of product internal communication interface, fault simulation signal can insert the signaling interface of chip and the signal flow between the chip functions module selectively.
4, product fault-tolerance method of testing according to claim 2, it is characterized in that: fault is inserted device and is arranged in programmable logic device (PLD), and and has the two-way signaling path between the signaling interface of programmable logic device (PLD), by the control of product internal communication interface, fault simulation signal can insert the signaling interface of programmable logic device (PLD) and the signal flow between the described chip signal interface selectively.
5, product fault-tolerance method of testing according to claim 1 is characterized in that: the step that fault simulation signal inserts comprises:
(1) definite fault type that needs insertion;
(2) definite abort situation that needs insertion;
(3) enable fault and insert, whether the working condition of checkout object meets expected results, if do not meet then carry out relative recording and analysis;
(4) config failure inserts and to stop, and whether the working condition of checkout object meets expected results, if do not meet then carry out relative recording and analysis.
6, according to claim 3 or 4 described product fault-tolerance method of testings, it is characterized in that: it is the unit entity that adopts the describing mode realization of hardware language that described fault is inserted device.
7, a kind of fault is inserted device, it is characterized in that comprising communication control module, fault-signal generation module and fault insertion selection module, and communication control module inserts with fault-signal generation module and fault respectively selects module to link to each other; Associated control signal is passed to the fault-signal generation module to communication control module and fault is inserted the selection module, with the insertion type and the insertion position of definite fault simulation signal, thus analog equipment built-in function cell mesh or all inefficacies.
8, fault according to claim 7 is inserted device, it is characterized in that: described communication control module comprises control signal interface and control register, cpu control bus carries out read-write operation by the control signal interface to control register, and fault-signal type that the control fault signal generator module produces and fault are inserted the fault-signal insertion of selecting module and enabled and the insertion position.
9, fault according to claim 8 is inserted device, it is characterized in that: described control register comprises that fault-signal produces control register and fault is inserted the selection control register;
Described fault-signal produces control register and comprises:
The fault type control register that is used for control fault signal generator module output fault-signal type;
The output pulse width control register that is used for the gating pulse width; With
The output number of pulses control register that is used for gating pulse quantity;
Described fault is inserted the fault-signal insertion of selecting the control register control fault to insert the selection module and is enabled and the insertion position.
10, fault according to claim 9 is inserted device, it is characterized in that: described fault-signal generation module is deciphered the content of fault type control register, obtain the control signal of fault-signal traffic pilot, control traffic pilot gating is inserted into fault-signal accordingly, and sends into fault and insert in the selection module.
11, fault according to claim 9 is inserted device, it is characterized in that: described fault is inserted the content of selecting module that fault is inserted the selection control register and is deciphered, produce and select control signal, the insertion position of control fault signal and the insertion of fault-signal and recovery.
12, fault according to claim 10 is inserted device, it is characterized in that: described fault-signal generation module directly adopts the work clock of chip, or utilizes chip and the unnecessary pin of programmable logic device (PLD) to introduce the various types of fault simulation signals of clock generating from the outside.
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| CNB2005100724362A CN100439930C (en) | 2005-05-11 | 2005-05-11 | Method for testing product fault-tolerant performance and fault inserting device thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2009127160A1 (en) * | 2008-04-17 | 2009-10-22 | 华为技术有限公司 | Disaster-tolerant testing method, apparatus and server |
| CN102832791A (en) * | 2011-06-15 | 2012-12-19 | 电力集成公司 | Method and apparatus for programming power converter controller with external programming terminal |
| CN110632408A (en) * | 2018-06-25 | 2019-12-31 | 北京天诚同创电气有限公司 | Electronic equipment testing method and device for simulating power grid fault |
| CN117539703A (en) * | 2024-01-10 | 2024-02-09 | 长城信息股份有限公司 | Memory bank anti-reverse-insertion device and method |
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| TWI463153B (en) * | 2012-03-30 | 2014-12-01 | Atomic Energy Council | Triple-redundant failure auto-detector of analog output module |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4875209A (en) * | 1988-04-04 | 1989-10-17 | Raytheon Company | Transient and intermittent fault insertion |
| US6108807A (en) * | 1997-07-28 | 2000-08-22 | Lucent Technologies Inc. | Apparatus and method for hybrid pin control of boundary scan applications |
| CN1231768C (en) * | 2002-04-08 | 2005-12-14 | 华为技术有限公司 | Signal fault injection machine |
| CN1192525C (en) * | 2002-04-08 | 2005-03-09 | 华为技术有限公司 | Multi-function fault implanting machine |
| CN1230885C (en) * | 2002-05-28 | 2005-12-07 | 华为技术有限公司 | Fault-telerance method and system of testing chip for boundary scanning |
| CN100406899C (en) * | 2003-05-10 | 2008-07-30 | 华为技术有限公司 | Apparatus for testing electric power system |
-
2005
- 2005-05-11 CN CNB2005100724362A patent/CN100439930C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009127160A1 (en) * | 2008-04-17 | 2009-10-22 | 华为技术有限公司 | Disaster-tolerant testing method, apparatus and server |
| CN101262370B (en) * | 2008-04-17 | 2011-09-14 | 华为技术有限公司 | Disaster tolerance rehearsal method, device and server |
| CN102832791A (en) * | 2011-06-15 | 2012-12-19 | 电力集成公司 | Method and apparatus for programming power converter controller with external programming terminal |
| US9287786B2 (en) | 2011-06-15 | 2016-03-15 | Power Integrations, Inc. | Method and apparatus for programming a power converter controller with an external programming terminal having multiple functions |
| CN110632408A (en) * | 2018-06-25 | 2019-12-31 | 北京天诚同创电气有限公司 | Electronic equipment testing method and device for simulating power grid fault |
| CN117539703A (en) * | 2024-01-10 | 2024-02-09 | 长城信息股份有限公司 | Memory bank anti-reverse-insertion device and method |
| CN117539703B (en) * | 2024-01-10 | 2024-04-23 | 长城信息股份有限公司 | Memory bank anti-reverse-insertion device and method |
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